>
> But with 5-level paging enabled the reset vector should be able to
> fallback to 4-level paging in case the CPU does not support 5-level
> paging.
The fallback makes sense. Otherwise, forcing to use 5L in an incapable CPU
would be a silent failure because IDT and debug log are not enabled at
> Using 5level paging when the below two conditions are both true:
> 1. CPU support 5level paging
> 2. Platform choose to use 5level paging. (by specifing macro
> USE_5_LEVEL_PAGE_TABLE)
>
> There is an assumption that if platform choose to use 5level paging,
> then 5level paging should be su
nal Message-
> From: devel@edk2.groups.io On Behalf Of Gerd
> Hoffmann
> Sent: Monday, April 3, 2023 7:56 PM
> To: Liu, Zhiguang
> Cc: devel@edk2.groups.io; Dong, Eric ; Ni, Ray
> ; Kumar, Rahul R ; De,
> Debkumar ; West, Catharine
>
> Subject: Re: [edk2-devel] [PATCH 2/
On Mon, Apr 03, 2023 at 05:28:14PM +0800, Zhiguang Liu wrote:
> Use a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create
> 5 level page table. Whether creating it or not, the highest level
> page table address is fixed.
Can we create the 5level page table unconditionally?
We should have
Use a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create
5 level page table. Whether creating it or not, the highest level
page table address is fixed.
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Cc: Debkumar De
Cc: Catharine West
Signed-off-by: Zhiguang Liu
---
...
