> > But with 5-level paging enabled the reset vector should be able to > fallback to 4-level paging in case the CPU does not support 5-level > paging.
The fallback makes sense. Otherwise, forcing to use 5L in an incapable CPU would be a silent failure because IDT and debug log are not enabled at this early stage. Later CpuPei/Dxe module could dump the paging status to tell platform owner that what level is used in this boot. With that, that means a 4L reset vector can save 4K space by excluding the PML5 page. But a 5L reset vector could set CR3 to PML4 page if CPU is incapable. Thanks, Ray -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103030): https://edk2.groups.io/g/devel/message/103030 Mute This Topic: https://groups.io/mt/98031298/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/9847357/21656/1706620634/xyzzy [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
