> > index 91b19f832f00..bc782e7e3873 100644
> > --- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> > +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> > @@ -12,6 +12,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> >
> > /**
> > @@ -89,10 +90,2
ping!!
> -Original Message-
> From: Pankaj Bansal (OSS)
> Sent: Saturday, July 4, 2020 9:22 PM
> To: devel@edk2.groups.io; Eric Jin ; G Edhaya Chandran
>
> Cc: Pankaj Bansal ; Paul Yang ;
> Samer El-Haj-Mahmoud ; Gaurav Jain
>
> Subject: [PATCH edk2-test 1/1]
Please don't merge this Patch.
This patch needs update. The ReservedRam needs to be reported to UEFI.
I will send v2 for this patch. other patches in this series can be reviewed.
Regards,
Pankaj Bansal
> -Original Message-
> From: Pankaj Bansal (OSS)
> Sent: Wednesday, J
From: Pankaj Bansal
For DXE_RUNTIME_DRIVER runtime safe version of DebugLib should be
used. Otherwise, any DEBUG print in code can result in abort in OS.
Signed-off-by: Pankaj Bansal
---
Silicon/NXP/NxpQoriqLs.dsc.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/Silicon/NXP
From: Pankaj Bansal
Some NXP SOCs have some specialized IP blocks (like MC), which
require DDR memory to operate. This DDR memory should not be managed
by OS or UEFI.
Moreover to ensure that these IP blocks always get memory, and maximum
contiguous RAM is available for UEFI and OS to use, add
From: Pankaj Bansal
This patch adds the Support for printing the git commit information
in linux build environment.
Ideal place of retrieving this information should be python script in
BaseTools.
A Feature request for the same has been created:
https://bugzilla.tianocore.org/show_bug.cgi?id
From: Pankaj Bansal
This patch series adds some useful features to NXP platforms.
- runtime safe version of DebugLib
- Add support for reserving a chunk from RAM
- Add Support for git commit info print
Pankaj Bansal (3):
Silicon/NXP: Use runtime safe version of DebugLib
Silicon/NXP: Add
From: Pankaj Bansal
Add VarStore Fd. This Fd is used to store non volatile variables in
flash.
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V3:
- Added Reviewed-by: Leif Lindholm
V2:
- No change
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 1
From: Pankaj Bansal
LS1046A Freeway (FRWY) is a high-performance development
platform that supports the QorIQ LS1046A Layerscape Architecture SOCs.
Co-authored-by: Pramod Kumar
Signed-off-by: Pankaj Bansal
---
Notes:
V3:
- Squashed previous commit to this commit
V2:
- No
From: Pankaj Bansal
LS1046A is QorIq Layerscape multicore communications processor with
four Arm Cortex-A72 cores.
This SOC is based on Layerscape Chassis v2.
Co-authored-by: Vabhav Sharma
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V3:
- Removed Co-authored
From: Pankaj Bansal
The Layerscape LS1046A Freeway (FRWY-LS1046A) board is a high-performance
development platform that supports the QorIQ LS1046A architecture
processor.
The LS1046A SOC is based on Layerscape Chassis2.
The code structure is same as Chassis2 and LS1043A SOC and LS1043ARDB
From: Pankaj Bansal
For LS1043A SOC the DCFG registers are read in big endian format.
After Reading the registers in code we have the registers in Little
Endian Bit format i.e. LSBit 0.
However, the RCW bits in RCWSR registers in LS1043A SOC are in MSBit 0
format.
Currently, we are parsing the
From: Pankaj Bansal
RCW bits parsing and their interpretation varies between various SOCs.
Add the comments that explain this parsing scheme.
Based on this explanation, fix the comments for SYS_PLL_RAT parsing
in LX2160A.
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes
From: Pankaj Bansal
RCW bits parsing and their interpretation varies between various SOCs.
Add the comments that explain this parsing scheme.
Based on this explanation, fix the comments for SYS_PLL_RAT parsing
in LX2160A.
Signed-off-by: Pankaj Bansal
---
Silicon/NXP/LS1043A/Include/Soc.h
From: Pankaj Bansal
LS1046A Freeway (FRWY) is a high-performance development
platform that supports the QorIQ LS1046A Layerscape Architecture SOCs.
Co-authored-by: Pramod Kumar
Co-authored-by: Pankaj Bansal
Signed-off-by: Pankaj Bansal
---
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
From: Pankaj Bansal
Add ArmPlatformLib for LS1046AFRWY platform that is based on
ArmPlatformPkg/Library/ArmPlatformLibNull.
Signed-off-by: Pankaj Bansal
---
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
| 38
Platform/NXP/LS1046aFrwyPkg/Library
From: Pankaj Bansal
For LS1043A SOC the DCFG registers are read in big endian format.
After Reading the registers in code we have the registers in Little
Endian Bit format i.e. LSBit 0.
However, the RCW bits in RCWSR registers in LS1043A SOC are in MSBit 0
format.
Currently, we are parsing the
From: Pankaj Bansal
LS1046A is QorIq Layerscape multicore communications processor with
four Arm Cortex-A72 cores.
This SOC is based on Layerscape Chassis v2.
Co-authored-by: Vabhav Sharma
Co-authored-by: Pankaj Bansal
Signed-off-by: Pankaj Bansal
---
Silicon/NXP/LS1046A/LS1046A.dec
From: Pankaj Bansal
Add VarStore Fd. This Fd is used to store non volatile variables in
flash.
Signed-off-by: Pankaj Bansal
---
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 1 +
Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc | 91
2 files changed, 92 insertions
From: Pankaj Bansal
The Layerscape LS1046A Freeway (FRWY-LS1046A) board is a high-performance
development platform that supports the QorIQ LS1046A architecture
processor.
The LS1046A SOC is based on Layerscape Chassis2.
The code structure is same as Chassis2 and LS1043A SOC and LS1043ARDB
From: Pankaj Bansal
The BBTestAllocatePagesInterfaceTest tries to allocate pages for
different memory types.
While doing so, it tries to fix up the Start and PageNum for 64K
Page size. There are multiple issues with this:
1. 64K alignment is being done regardless of Processor type and Memory
Hi Leif,
Sorry for late reply.
Actually I had asked the design team to check this point.
I am waiting for their reply.
I will add comments in code based on their reply and send new version.
Regards,
Pankaj Bansal
> -Original Message-
> From: Leif Lindholm
> Sent: Friday, June
> -Original Message-
> From: Leif Lindholm
> Sent: Monday, June 8, 2020 7:52 PM
> To: Pankaj Bansal (OSS)
> Cc: Meenakshi Aggarwal ; Michael D Kinney
> ; devel@edk2.groups.io; Varun Sethi
> ; Samer El-Haj-Mahmoud mahm...@arm.com>; Augustine Philips ; Ard
&g
> On Tue, Jun 02, 2020 at 18:54:59 +0530, Pankaj Bansal wrote:
> > From: Pankaj Bansal
> >
> > for LS1043A SOC the DCFG registers are read in big endian format.
> > However current Platofmr PLL calculation is being done assuing the
>
> >>
> >> (since I've been copied)
> >>
> >> I have not been aware of the header name collision scenario (nor that
> >> the [Packages] ordering was supposed to work around such issues).
> >>
> >> I work strictly with edk2 proper, where a name collision like this can
> >> be detected, and so should
> -Original Message-
> From: Laszlo Ersek
> Sent: Tuesday, June 2, 2020 7:00 PM
> To: Leif Lindholm ; devel@edk2.groups.io;
> michael.d.kin...@intel.com
> Cc: Andrew Fish ; Pankaj Bansal (OSS)
>
> Subject: Re: [edk2-devel] [PATCH edk2-InfSpecification] Dro
From: Pankaj Bansal
LS1046A Freeway (FRWY) is a high-performance development
platform that supports the QorIQ LS1046A Layerscape Architecture SOCs.
Co-authored-by: Pramod Kumar
Co-authored-by: Pankaj Bansal
Signed-off-by: Pankaj Bansal
---
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
From: Pankaj Bansal
Add ArmPlatformLib for LS1046AFRWY platform that is based on
ArmPlatformPkg/Library/ArmPlatformLibNull.
Signed-off-by: Pankaj Bansal
---
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
| 38
Platform/NXP/LS1046aFrwyPkg/Library
From: Pankaj Bansal
LS1046A is QorIq Layerscape multicore communications processor with
four Arm Cortex-A72 cores.
This SOC is based on Layerscape Chassis v2.
Co-authored-by: Vabhav Sharma
Co-authored-by: Pankaj Bansal
Signed-off-by: Pankaj Bansal
---
Silicon/NXP/LS1046A/LS1046A.dec
From: Pankaj Bansal
Add VarStore Fd. This Fd is used to store non volatile variables in
flash.
Signed-off-by: Pankaj Bansal
---
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 1 +
Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc | 91
2 files changed, 92 insertions
From: Pankaj Bansal
for LS1043A SOC the DCFG registers are read in big endian format.
However current Platofmr PLL calculation is being done assuing the
little endian format.
Fix the Platform PLL calculation
Signed-off-by: Pankaj Bansal
---
Silicon/NXP/LS1043A/Include/Soc.h | 2 +-
1 file
From: Pankaj Bansal
The Layerscape LS1046A Freeway (FRWY-LS1046A) board is a high-performance
development platform that supports the QorIQ LS1046A architecture
processor.
The LS1046A SOC is based on Layerscape Chassis2.
The code structure is same as Chassis2 and LS1043A SOC and LS1043ARDB
From: Pankaj Bansal
LX2160A Reference Design Board (RDB) is a high-performance development
platform that supports the QorIQ LX2160A Layerscape Architecture SOCs.
Signed-off-by: Pankaj Bansal
---
Notes:
V4:
- Alphabetically sorted Packages in
Platform/NXP/LX2160aRdbPkg/Library
From: Pankaj Bansal
Monotonic counter module from EmbeddedPkg doesn't treat the
high 32 bit as non volatile, which is needed as per spec.
Therefore, use Monotonic counter module from MdeModulePkg
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V4:
- No c
From: Pankaj Bansal
when MDEPKG_NDEBUG flag is enabled, RELEASE build fails with this error:
error: mPciHostBridgeLibAcpiAddressSpaceTypeStr defined but not used
[-Werror=unused-variable]
Fix this error by protecting mPciHostBridgeLibAcpiAddressSpaceTypeStr
with MDEPKG_NDEBUG macro.
Suggested
From: Pankaj Bansal
edk2 recommends to use MDEPKG_NDEBUG for release builds and to use
DISABLE_NEW_DEPRECATED_INTERFACES for all new platforms.
Therefore, enable these flags for NXP platforms as well
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V4:
- No change
From: Pankaj Bansal
In NXP SOCs the UART clock is derived from System clock after PLL
multiplication. Therefore, add the PL011UartClockLib implementation
for NXP platforms.
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V4:
- No change
V3:
- No change
From: Pankaj Bansal
LX2160A is QorIq Layerscape multicore communications processor with
sixteen Arm Cortex-A72 cores.
This SOC is based on Layerscape Chassis v3.2.
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V4:
- No change
V3:
- No change
V2
From: Pankaj Bansal
There are two implementations of Metronome protocol.
EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
MdeModulePkg/Universal/Metronome/Metronome.inf
Although nowhere it has been specified, which one to use, but we are
going by the general practice of preferring MdeModulePkg/MdePkg
From: Pankaj Bansal
Chassis3V2 is the new chassis on which LS1028A and LX2160A SOCs
are based.
Add the Chassis3V2 package.
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V4:
- No change
V3:
- No change
V2:
- No change
Silicon/NXP/Chassis3V2
From: Pankaj Bansal
Add VarStore Fd. This Fd is used to store non volatile variables in
flash.
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V4:
- No change
V3:
- No change
V2:
- No change
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf | 1
From: Pankaj Bansal
LX2160A Reference Design Board (RDB) is a high-performance development
platform that supports the QorIQ LX2160A Layerscape Architecture SOCs.
This Platform is based on Layerscape Chassis3V2.
The code structure is same as Chassis2 and LS1043A SOC and LS1043ARDB
platform.
v3
From: Pankaj Bansal
Add ArmPlatformLib for LX2160ARDB platform that is based on
ArmPlatformPkg/Library/ArmPlatformLibNull.
Apart from the the interfaces exposed by ArmPlatformLibNull, this
library also implements gPlatformGetClockPpi, which is specific to NXP
SOCs' based platforms.
Refer
t
is used by MdePkg / MdeModulePkg.
Which one to follow ??
Regards,
Pankaj Bansal
> -Original Message-
> From: Kinney, Michael D
> Sent: Monday, June 1, 2020 10:45 AM
> To: Pankaj Bansal (OSS) ; Leif Lindholm
> ; devel@edk2.groups.io; Kinney, Michael D
>
> Cc:
Hi Mike,
This means any port of edk2, should it so wish to override the include file
provided by edk2 packages (MdePkg or MdeModulePkg),
must be listed after these dec files (MdePkg.dec or MdeModulePkg.dec) in an inf
file?
Regards,
Pankaj Bansal
> -Original Message-
> From
> On Fri, May 29, 2020 at 12:25:43 +0000, Pankaj Bansal (OSS) wrote:
> > > > I intentionally kept these in this order. because Soc depends on Chassis
> for any
> > > include files
> > > > Chassis depends on NxpQoriqLs.dec for any include files.
> > &g
> On Fri, May 29, 2020 at 05:21:24 +0000, Pankaj Bansal (OSS) wrote:
> > > > ---
> > >
> a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > > > +++
> > >
> b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformL
From: Pankaj Bansal
edk2 recommends to use MDEPKG_NDEBUG for release builds and to use
DISABLE_NEW_DEPRECATED_INTERFACES for all new platforms.
Therefore, enable these flags for NXP platforms as well
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V3:
- No change
From: Pankaj Bansal
Monotonic counter module from EmbeddedPkg doesn't treat the
high 32 bit as non volatile, which is needed as per spec.
Therefore, use Monotonic counter module from MdeModulePkg
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V3:
- No c
From: Pankaj Bansal
when MDEPKG_NDEBUG flag is enabled, RELEASE build fails with this error:
error: mPciHostBridgeLibAcpiAddressSpaceTypeStr defined but not used
[-Werror=unused-variable]
Fix this error by protecting mPciHostBridgeLibAcpiAddressSpaceTypeStr
with MDEPKG_NDEBUG macro.
Suggested
From: Pankaj Bansal
Add ArmPlatformLib for LX2160ARDB platform that is based on
ArmPlatformPkg/Library/ArmPlatformLibNull.
Apart from the the interfaces exposed by ArmPlatformLibNull, this
library also implements gPlatformGetClockPpi, which is specific to NXP
SOCs' based platforms.
Refer
From: Pankaj Bansal
LX2160A is QorIq Layerscape multicore communications processor with
sixteen Arm Cortex-A72 cores.
This SOC is based on Layerscape Chassis v3.2.
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V3:
- No change
V2:
- No change
Silicon
From: Pankaj Bansal
In NXP SOCs the UART clock is derived from System clock after PLL
multiplication. Therefore, add the PL011UartClockLib implementation
for NXP platforms.
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V3:
- No change
V2:
- No change
From: Pankaj Bansal
Chassis3V2 is the new chassis on which LS1028A and LX2160A SOCs
are based.
Add the Chassis3V2 package.
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V3:
- No change
V2:
- No change
Silicon/NXP/Chassis3V2/Chassis3V2.dec
From: Pankaj Bansal
Add VarStore Fd. This Fd is used to store non volatile variables in
flash.
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V3:
- No change
V2:
- No change
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf | 1 +
Platform/NXP/LX2160aRdbPkg
From: Pankaj Bansal
LX2160A Reference Design Board (RDB) is a high-performance development
platform that supports the QorIQ LX2160A Layerscape Architecture SOCs.
Signed-off-by: Pankaj Bansal
---
Notes:
V3:
- Alphabetically sorted LibraryClasses in
Platform/NXP/LX2160aRdbPkg
From: Pankaj Bansal
There are two implementations of Metronome protocol.
EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
MdeModulePkg/Universal/Metronome/Metronome.inf
Although nowhere it has been specified, which one to use, but we are
going by the general practice of preferring MdeModulePkg/MdePkg
From: Pankaj Bansal
LX2160A Reference Design Board (RDB) is a high-performance development
platform that supports the QorIQ LX2160A Layerscape Architecture SOCs.
This Platform is based on Layerscape Chassis3V2.
The code structure is same as Chassis2 and LS1043A SOC and LS1043ARDB
platform.
v2
> > ---
> a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > +++
> b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > @@ -19,9 +19,12 @@
> >ArmPkg/ArmPkg.dec
> >ArmPlatformPkg/ArmPlatformPkg.dec
> >Silicon/NXP/NxpQoriqLs.dec
> > + Silicon
From: Pankaj Bansal
Monotonic counter module from EmbeddedPkg doesn't treat the
high 32 bit as non volatile, which is needed as per spec.
Therefore, use Monotonic counter module from MdeModulePkg
Signed-off-by: Pankaj Bansal
---
Notes:
V2:
- No change
Silicon/NXP/NxpQoriqLs.ds
From: Pankaj Bansal
LX2160A is QorIq Layerscape multicore communications processor with
sixteen Arm Cortex-A72 cores.
This SOC is based on Layerscape Chassis v3.2.
Signed-off-by: Pankaj Bansal
---
Notes:
V2:
- No change
Silicon/NXP/LX2160A/LX2160A.dec | 13
From: Pankaj Bansal
In NXP SOCs the UART clock is derived from System clock after PLL
multiplication. Therefore, add the PL011UartClockLib implementation
for NXP platforms.
Signed-off-by: Pankaj Bansal
---
Notes:
V2:
- No change
Silicon/NXP/Library/PL011UartClockLib
From: Pankaj Bansal
Add VarStore Fd. This Fd is used to store non volatile variables in
flash.
Signed-off-by: Pankaj Bansal
---
Notes:
V2:
- No change
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf | 1 +
Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc | 91
2 files
From: Pankaj Bansal
Chassis3V2 is the new chassis on which LS1028A and LX2160A SOCs
are based.
Add the Chassis3V2 package.
Signed-off-by: Pankaj Bansal
---
Notes:
V2:
- No change
Silicon/NXP/Chassis3V2/Chassis3V2.dec| 22 ++
Silicon/NXP/Chassis3V2/Chassis3V2
From: Pankaj Bansal
LX2160A Reference Design Board (RDB) is a high-performance development
platform that supports the QorIQ LX2160A Layerscape Architecture SOCs.
Signed-off-by: Pankaj Bansal
---
Notes:
V2:
- split Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ in two parts
From: Pankaj Bansal
edk2 recommends to use MDEPKG_NDEBUG for release builds and to use
DISABLE_NEW_DEPRECATED_INTERFACES for all new platforms.
Therefore, enable these flags for NXP platforms as well
Signed-off-by: Pankaj Bansal
---
Notes:
V2:
- No change
Silicon/NXP
From: Pankaj Bansal
Add ArmPlatformLib for LX2160ARDB platform that is based on
ArmPlatformPkg/Library/ArmPlatformLibNull.
Apart from the the interfaces exposed by ArmPlatformLibNull, this
library also implements gPlatformGetClockPpi, which is specific to NXP
SOCs' based platforms.
Refer
From: Pankaj Bansal
LX2160A Reference Design Board (RDB) is a high-performance development
platform that supports the QorIQ LX2160A Layerscape Architecture SOCs.
This Platform is based on Layerscape Chassis3V2.
The code structure is same as Chassis2 and LS1043A SOC and LS1043ARDB
platform.
v1
From: Pankaj Bansal
There are two implementations of Metronome protocol.
EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
MdeModulePkg/Universal/Metronome/Metronome.inf
Although nowhere it has been specified, which one to use, but we are
going by the general practice of preferring MdeModulePkg/MdePkg
From: Pankaj Bansal
edk2 recommends to use MDEPKG_NDEBUG for release builds and to use
DISABLE_NEW_DEPRECATED_INTERFACES for all new platforms.
Therefore, enable these flags for NXP platforms as well
Signed-off-by: Pankaj Bansal
---
Silicon/NXP/NxpQoriqLs.dsc.inc | 7 ++-
1 file changed
From: Pankaj Bansal
LX2160A Reference Design Board (RDB) is a high-performance development
platform that supports the QorIQ LX2160A Layerscape Architecture SOCs.
Signed-off-by: Pankaj Bansal
---
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
| 23 +++
Platform
From: Pankaj Bansal
Chassis3V2 is the new chassis on which LS1028A and LX2160A SOCs
are based.
Add the Chassis3V2 package.
Signed-off-by: Pankaj Bansal
---
Silicon/NXP/Chassis3V2/Chassis3V2.dec| 22 ++
Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc| 10
From: Pankaj Bansal
In NXP SOCs the UART clock is derived from System clock after PLL
multiplication. Therefore, add the PL011UartClockLib implementation
for NXP platforms.
Signed-off-by: Pankaj Bansal
---
Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf | 24
From: Pankaj Bansal
LX2160A Reference Design Board (RDB) is a high-performance development
platform that supports the QorIQ LX2160A Layerscape Architecture SOCs.
This Platform is based on Layerscape Chassis3V2.
The code structure is same as Chassis2 and LS1043A SOC and LS1043ARDB
platform
From: Pankaj Bansal
Add VarStore Fd. This Fd is used to store non volatile variables in
flash.
Signed-off-by: Pankaj Bansal
---
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf | 1 +
Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc | 91
2 files changed, 92 insertions(+)
diff
From: Pankaj Bansal
There are two implementations of Metronome protocol.
EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
MdeModulePkg/Universal/Metronome/Metronome.inf
Although nowhere it has been specified, which one to use, but we are
going by the general practice of preferring MdeModulePkg/MdePkg
From: Pankaj Bansal
Monotonic counter module from EmbeddedPkg doesn't treat the
high 32 bit as non volatile, which is needed as per spec.
Therefore, use Monotonic counter module from MdeModulePkg
Signed-off-by: Pankaj Bansal
---
Silicon/NXP/NxpQoriqLs.dsc.inc | 2 +-
Pla
From: Pankaj Bansal
LX2160A is QorIq Layerscape multicore communications processor with
sixteen Arm Cortex-A72 cores.
This SOC is based on Layerscape Chassis v3.2.
Signed-off-by: Pankaj Bansal
---
Silicon/NXP/LX2160A/LX2160A.dec | 13
Silicon/NXP/LX2160A/LX2160A.dsc.inc
From: Pankaj Bansal
This patch series adds PEI phase to NXP LS1043ARDB Platform.
V4 series can be referred here:
https://edk2.groups.io/g/devel/message/58367
I have taken care of the review comments received on V4.
I am only sending the patch in V5 that needed rework.
rest of the patches can be
From: Pankaj Bansal
RAM retrieval using SMC commands is common to all Layerscape SOCs.
Therefore, move it to common MemoryInit Pei Lib.
Signed-off-by: Pankaj Bansal
---
Notes:
V5:
- Add SMC_DRAM_TOTAL_DRAM_ARG1 to denote the x1 argument to pass to
SMC call to retrieve the total
>
> On Thu, May 07, 2020 at 07:28:30 +, Pankaj Bansal (OSS) wrote:
> > Hi Leif,
> >
> > > > + ARM_SMC_ARGS ArmSmcArgs;
> > > >
> > > > -Routine Description:
> > > > + ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
> > >
Hi Leif,
> > + ARM_SMC_ARGS ArmSmcArgs;
> >
> > -Routine Description:
> > + ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
> > + ArmSmcArgs.Arg1 = -1;
>
> Should this be SMC_UNK?
No. SMC_OK / SMC_UNK is returned values.
While x0, x1 are arguments.
I have explained this in the MemoryInitPeiLib.h
// T
From: Pankaj Bansal
The structures elements and functions that are not necessary for booting
for now are being deleted.
Once the directory structure has been changed (i.e. we have clear
distinction between chassis code and header files and SOC code and header
files), we will put back the code
From: Pankaj Bansal
A Chassis is a base framework used for building SoCs.
We can think of Chassis/Soc/Platform(a.k.a Board) in Object model terms.
Chassis is base. Soc is based on some Chassis.
Platform is based on some Soc.
SOCs that are designed around same chassis, reuse most of the
From: Pankaj Bansal
The SocLib contains code specific to an Soc. it should be part of
SOC package.
Therefore, move the SocLib to Soc Package.
Since we are moving the files to Soc Package, no need to mention the
Soc name in file names. Their location is enough to indicate for which
Soc the files
From: Pankaj Bansal
The Soc info being printed can be removed from SOC lib.
We are in the process of implementing PEI Phase.
After PEI phase implementation this info would be printed in
common PEIM based on the information retrieved from PPIs.
e.g. gArmMpCoreInfoPpiGuid can be used to print
From: Pankaj Bansal
SocInit can be defined in SocLib.h
No need to make it extern in ArmPlatformLib
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V4:
- No change
V3:
- Moved commit three commits before in series
Silicon/NXP/Include/Library/SocLib.h
From: Pankaj Bansal
Soc specific components ought to be part of Soc files and not
platform files. move the same to SOC files
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V4:
- No change
V3:
- No change
Platform/NXP/NxpQoriqLs.dsc.inc | 2
From: Pankaj Bansal
FVRules.fdf.inc is being replaced by the ArmVirtPkg/ArmVirtRules.fdf.inc
at commit hash 746c5b6238f1ee55deb4b3ec32a6d732e27eeeaa
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V4:
- No change
V3:
- Modify commit description
Platform
From: Pankaj Bansal
As per convention being followed in edk2-platforms, keep the dec
file and dsc file together.
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V4:
- No change
V3:
- No change
{Platform => Silicon}/NXP/NxpQoriqLs.dsc.inc | 0
Platf
From: Pankaj Bansal
Keep the names and location of files as mentioned in ArmPlatformPkg.
This helps in porting the common changes (if any in future) easily.
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V4:
- No change
V3:
- No change
Platform/NXP
From: Pankaj Bansal
Now the we have added Chassis Package, move the chassis specific common
code for all SOCs belonging to same chassis to ChassisLib.
Use ChassisLib APIs in SocLib.
Signed-off-by: Pankaj Bansal
---
Notes:
V4:
- No change
V3:
- No change
Silicon/NXP
From: Pankaj Bansal
Use NXP_PLATFORM_GET_CLOCK_PPI in various Layerscape IP modules.
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V4:
- No change
V3:
- Added clock retrieval APIs to DUartPortLib
Silicon/NXP/NxpQoriqLs.dec| 5
From: Pankaj Bansal
ArmPlatformHelper.S is being replaced by the ArmPlatformPkg version at
commit hash f4dfad05dda2c7b29e8105605621f2b413f0af2b.
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V4:
- fixed line adds whitespace error
V3:
- Modify commit
From: Pankaj Bansal
Add VarStore Fd. This Fd is used to store non volatile variables in
flash.
Signed-off-by: Pankaj Bansal
Reviewed-by: Leif Lindholm
---
Notes:
V4:
- No change
V3:
- No change
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 3 +-
Platform/NXP
From: Pankaj Bansal
The SwapMmio** APIs are supposed to be called indirectly via
GetMmioOperations** APIs.
Therefore, remove the SwapMmio** APIs from IoAccessLib.h and make
these APIs STATIC to IoAccessLib.c, so that no accidental call can
be made to these.
Signed-off-by: Pankaj Bansal
From: Pankaj Bansal
The memory map of an SOC is fixed in hardware. it doesn't change with
platform that uses SOC. So, there is no need to keep PCDs for these values
and we can use macros for these in SOC header file.
Any Platform using the SOC, can make use of the SOC header file.
Signe
From: Pankaj Bansal
Add PEI phase to LS1043aRdb. This is needed because we need to have
dynamic PCDs support to be able to reserve memory before reporting
memory to UEFI firmware.
Using PEI phase we are now also dynamically setting the
PcdSystemMemoryBase and PcdSystemMemorySize depending upon
From: Pankaj Bansal
RAM retrieval using SMC commands is common to all Layerscape SOCs.
Therefore, move it to common MemoryInit Pei Lib.
Signed-off-by: Pankaj Bansal
---
Notes:
V4:
- fixed line adds white space error in MemoryInitPeiLib.h
- Added SMC_OK and SMC_UOK Macros to denote
From: Pankaj Bansal
The SOC takes primary clocking input from the external signal (a clock
generator on board). The input (frequency) is multiplied using multiple
phase locked loops (PLL) to create a variety of frequencies which can
then be passed to a variety of internal logic, including cores
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