+ Get CpuCacheInfo data array. The data array is sorted by CPU package ID from
smallest to largest,
+ by core type from largest to smallest and by cache level from smallest to
largest.
Why is core type sorted from largest to smallest but the other twos are sorted
from smallest to largest?
Wh
02.08.2021 06:51:39 Jeff Fan :
Marvin,
ImageBase was saved in DR2 to help HOST debugger to locate the image
base more easily, even though the HOST debugger could find the image
base through searching the DOS image signagure.
The reason choosing DR1 and DR2 to save PDB & ImageBase contexts i
02.08.2021 05:09:29 Ni, Ray :
> Marvin,
> Host assumes first 8-byte (little endian) of memory pointed by DR2 is the
> value of Image base address.
Thanks Ray! So I can be confident no further data from the context are or will
be queried and I can just publish the Image base from the stack for
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Wu, Hao
> A
> Sent: Monday, August 2, 2021 12:36 PM
> To: Sunny Wang ; Gao, Zhichao
> ; Grzegorz Bernacki ;
> devel@edk2.groups.io; Wang, Jian J
> Cc: l...@nuviainc.com; ardb+tianoc...@kernel.org; Samer El-Haj-Mahmoud
> ; m...
I see most failures are coding style. The function header comment style is /**
.. **/.
--*/ should be replaced by **/
Thanks
Liming
> -邮件原件-
> 发件人: Ard Biesheuvel
> 发送时间: 2021年8月2日 2:04
> 收件人: Grzegorz Bernacki
> 抄送: edk2-devel-groups-io ; Leif Lindholm
> ; Ard Biesheuvel ; Samer
> El
The ICU to GIC interrupt mapping was fixed to support
the maximum of two CP11x south bridge units. Rework
the default map to use only the interrupts wired
to controllers supported in the ACPI tables.
Thanks to above all necessary IRQs from the CN913x
SoCs (maximum 3 CP11x) can be mapped and passed
Introduce new board description library extension that allows
to execute custom initialization sequence. Add stubs for all
existing platforms.
Signed-off-by: Marcin Wojtas
---
Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf
| 1 +
Silicon/Marvell/Inc
From: Kamil Koczurek
In order to support more than one PCIE port, PciHostBridgeLib must
generate appropriate device paths according to the board description
and assign correct segment numbers instead of a hard-coded 0.
Additionally, PciSegmentLib has to operate on a proper
config spaces base add
On CN913x-based platforms it is possible to have up to 9 PCIE
root complexes. In such case it may be necessary to configure
more configuration spaces with smaller bus count, so that
to fit the memory layout constraints. For that purpose remove
forcing ECAM base to be divisible by SIZE_256MB.
Signe
Until now it was assumed that the configuration space size is 256MB.
Allow setting different values in the board description library
instance for each platform.
Signed-off-by: Marcin Wojtas
---
Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h| 1 +
Silicon/Marvell/Armada7k8k/
Until now the virtual memory map for the single PCIE configuration space
was hardcoded via PCDs and assumed adjacency to the SoC MMIO region
(0xf000 - 4GB). Remove this limitation by splitting the regions
and allowing to obtain the PCIE configuration space settings
from ArmadaBoardDescLib. It i
This patchset is a preparation for adding a new platform
(CN913x CEx7 Evaluation Board). It modifies a common
Marvell code in order to enable multiple PCIE controllers.
Moreover a default interrupt map is reworked, so that to
support all CP11x south bridge units.
Last but not least, a custom init
Marvin,
ImageBase was saved in DR2 to help HOST debugger to locate the image base more
easily, even though the HOST debugger could find the image base through
searching the DOS image signagure.
The reason choosing DR1 and DR2 to save PDB & ImageBase contexts is just
implementation only. And it
> -Original Message-
> From: Sunny Wang
> Sent: Monday, August 2, 2021 11:16 AM
> To: Grzegorz Bernacki ; devel@edk2.groups.io; Wang,
> Jian J ; Wu, Hao A
> Cc: l...@nuviainc.com; ardb+tianoc...@kernel.org; Samer El-Haj-Mahmoud
> ; m...@semihalf.com;
> upstr...@semihalf.com; p...@akeo.ie;
Hi Hao, Jian, and MdeModulePkg maintainers,
Could you help merge this patch? This patch already got Reviewed-by from
Zhichao and me. If we still need to get others' reviews, feel free to let us
know.
By the way, we do have an edk2-platform change below that is waiting for this
patch to get merg
Marvin,
Host assumes first 8-byte (little endian) of memory pointed by DR2 is the value
of Image base address.
DR1 points to the PDB path (I am sure you noticed that in the
SourceLevelDebugPkg code).
There is no plan to provide detailed documentation of host/client communication
protocol. So fa
I also vote "using HOB passing policy". This design helps the new
bootloader/payload architecture.
EDKII library class design was a good design which mimics C++ class to provide
same interface for:
1. different phases (PEI, DXE, runtime. E.g.: HobLib, PcdLib,
MemoryAllocationLib)
2. different s
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Wu, Hao
> A
> Sent: Friday, July 30, 2021 4:51 PM
> To: devel@edk2.groups.io; shpark.zi...@gmail.com
> Cc: Chen, Chen A ; Seonghyun Park
>
> Subject: Re: [edk2-devel] [edk2 PATCH] MdeModulePkg: Fix typo in error
> message
>
>
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Wu, Hao
> A
> Sent: Thursday, July 29, 2021 4:26 PM
> To: Wenyi Xie ; devel@edk2.groups.io; Wang, Jian
> J
> Cc: songdongku...@huawei.com
> Subject: Re: [edk2-devel] [PATCH EDK2 v2 1/1]
> MdeModulePkg/UefiSortLib:Add UefiSortL
Reviewed-by: Yuwei Chen
> -Original Message-
> From: Feng, Bob C
> Sent: Wednesday, July 28, 2021 7:45 PM
> To: devel@edk2.groups.io
> Cc: Liming Gao ; Chen, Christine
>
> Subject: [Patch] BaseTools: use shutil.copyfile instead shutil.copy2
>
> In Split tool, the copy file actions only
01.08.2021 18:33:47 Ard Biesheuvel :
On Sat, 31 Jul 2021 at 21:08, Marvin Häuser wrote:
On 23.07.21 16:34, Ard Biesheuvel wrote:
On Fri, 23 Jul 2021 at 16:27, Marvin Häuser
wrote:
On 23.07.21 16:09, Ard Biesheuvel wrote:
On Fri, 23 Jul 2021 at 12:47, Marvin Häuser
wrote:
…
...
…
Do
On Fri, 30 Jul 2021 at 12:23, Grzegorz Bernacki wrote:
>
> This patchset adds support for initialization of default
> Secure Boot variables based on keys content embedded in
> flash binary. This feature is active only if Secure Boot
> is enabled and DEFAULT_KEY is defined. The patchset
> consist a
On Mon, 19 Jul 2021 at 11:30, Marcin Wojtas wrote:
>
> Hi,
>
> This new series comes with the remaining improvements that allow
> the ACS3.0 test suite to pass the SBSA/FWTS/SCT to the
> maximum non-HW related extent. Missing _STA methods
> and DBG2 description are added to the ACPI tables.
> More
On Fri, 30 Jul 2021 at 11:57, Marcin Wojtas wrote:
>
> Hi Ard,
>
> czw., 29 lip 2021 o 11:58 Ard Biesheuvel napisał(a):
> >
> > On Thu, 29 Jul 2021 at 11:46, Marcin Wojtas wrote:
> > >
> > > Hi Ard,
> > >
> > > pon., 19 lip 2021 o 17:06 Marcin Wojtas napisał(a):
> > > >
> > > > Hi Ard,
> > > >
(correct Achin's email address, cc other replyers)
On Sun, 1 Aug 2021 at 18:36, Ard Biesheuvel wrote:
>
> On Fri, 30 Jul 2021 at 19:35, Sayanta Pattanayak
> wrote:
> >
> > Introduce support to populate StMM boot data via DTS parsing.
>
> Why? Don't we have FF-A manifests for this? I would expect
On Fri, 30 Jul 2021 at 19:35, Sayanta Pattanayak
wrote:
>
> Introduce support to populate StMM boot data via DTS parsing.
Why? Don't we have FF-A manifests for this? I would expect the secure
partition manager to marshall this data into the appropriate format
when necessary.
> The DTB is
> passe
On Sat, 31 Jul 2021 at 21:08, Marvin Häuser wrote:
>
> On 23.07.21 16:34, Ard Biesheuvel wrote:
> > On Fri, 23 Jul 2021 at 16:27, Marvin Häuser wrote:
> >>
> >>
> >> On 23.07.21 16:09, Ard Biesheuvel wrote:
> >>> On Fri, 23 Jul 2021 at 12:47, Marvin Häuser wrote:
> On 23.07.21 12:13, Ard Bi
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