On CN913x-based platforms it is possible to have up to 9 PCIE
root complexes. In such case it may be necessary to configure
more configuration spaces with smaller bus count, so that
to fit the memory layout constraints. For that purpose remove
forcing ECAM base to be divisible by SIZE_256MB.
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
---
Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
| 1 -
1 file changed, 1 deletion(-)
diff --git
a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
index 067e57a2dc..87e57aeae3 100644
---
a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
+++
b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
@@ -219,7 +219,6 @@ Armada7k8kPciHostBridgeLibConstructor (
PcieController = &(BoardPcieDescription->PcieControllers[Index]);
ASSERT (PcieController->PcieBusMin == 0);
- ASSERT (PcieController->ConfigSpaceAddress % SIZE_256MB == 0);
if (PcieController->HaveResetGpio == TRUE) {
/* Reset PCIE slot */
--
2.29.0
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