The ICU to GIC interrupt mapping was fixed to support
the maximum of two CP11x south bridge units. Rework
the default map to use only the interrupts wired
to controllers supported in the ACPI tables.
Thanks to above all necessary IRQs from the CN913x
SoCs (maximum 3 CP11x) can be mapped and passed to the OS.
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
---
Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h | 48 ++++----
Silicon/Marvell/Library/IcuLib/IcuLib.h | 6 +-
Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h | 61 +++++++----
Silicon/Marvell/Library/IcuLib/IcuLib.c | 115
++++++--------------
4 files changed, 95 insertions(+), 135 deletions(-)
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h
b/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h
index b106790913..a2b7b00b0d 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h
@@ -11,28 +11,28 @@
**/
-#define CP_GIC_SPI_CP0_PCI0 64
-#define CP_GIC_SPI_CP0_PCI1 65
-#define CP_GIC_SPI_CP0_PCI2 66
-#define CP_GIC_SPI_CP0_SDMMC 67
-#define CP_GIC_SPI_PP2_CP0_PORT0 69, 72, 75, 78, 81, 127
-#define CP_GIC_SPI_PP2_CP0_PORT1 70, 73, 76, 79, 82, 126
-#define CP_GIC_SPI_PP2_CP0_PORT2 71, 74, 77, 80, 83, 125
-#define CP_GIC_SPI_CP0_EIP_RNG0 105
-#define CP_GIC_SPI_CP0_USB_H1 112
-#define CP_GIC_SPI_CP0_USB_H0 113
-#define CP_GIC_SPI_CP0_SATA_H0 114
-#define CP_GIC_SPI_CP0_UART0 121
-#define CP_GIC_SPI_CP0_UART1 122
+#define CP_GIC_SPI_CP0_SDMMC 64
+#define CP_GIC_SPI_PP2_CP0_PORT0 65, 68, 71, 74, 77, 90
+#define CP_GIC_SPI_PP2_CP0_PORT1 66, 69, 72, 75, 78, 89
+#define CP_GIC_SPI_PP2_CP0_PORT2 67, 70, 73, 76, 79, 88
+#define CP_GIC_SPI_CP0_EIP_RNG0 80
+#define CP_GIC_SPI_CP0_USB_H1 81
+#define CP_GIC_SPI_CP0_USB_H0 82
+#define CP_GIC_SPI_CP0_SATA_H0 83
+#define CP_GIC_SPI_CP0_UART0 84
+#define CP_GIC_SPI_CP0_UART1 85
+#define CP_GIC_SPI_CP0_UART2 86
+#define CP_GIC_SPI_CP0_UART3 87
-#define CP_GIC_SPI_CP1_PCI0 288
-#define CP_GIC_SPI_CP1_PCI1 289
-#define CP_GIC_SPI_CP1_PCI2 290
-#define CP_GIC_SPI_CP1_SDMMC 291
-#define CP_GIC_SPI_PP2_CP1_PORT0 293, 296, 299, 302, 305, 351
-#define CP_GIC_SPI_PP2_CP1_PORT1 294, 297, 300, 303, 306, 350
-#define CP_GIC_SPI_PP2_CP1_PORT2 295, 298, 301, 304, 307, 349
-#define CP_GIC_SPI_CP1_EIP_RNG0 329
-#define CP_GIC_SPI_CP1_USB_H1 336
-#define CP_GIC_SPI_CP1_USB_H0 337
-#define CP_GIC_SPI_CP1_SATA_H0 338
+#define CP_GIC_SPI_CP1_SDMMC 96
+#define CP_GIC_SPI_PP2_CP1_PORT0 97, 100, 103, 106, 109, 122
+#define CP_GIC_SPI_PP2_CP1_PORT1 98, 101, 104, 107, 110, 121
+#define CP_GIC_SPI_PP2_CP1_PORT2 99, 102, 105, 108, 111, 120
+#define CP_GIC_SPI_CP1_EIP_RNG0 112
+#define CP_GIC_SPI_CP1_USB_H1 113
+#define CP_GIC_SPI_CP1_USB_H0 114
+#define CP_GIC_SPI_CP1_SATA_H0 115
+#define CP_GIC_SPI_CP1_UART0 116
+#define CP_GIC_SPI_CP1_UART1 117
+#define CP_GIC_SPI_CP1_UART2 118
+#define CP_GIC_SPI_CP1_UART3 119
diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.h
b/Silicon/Marvell/Library/IcuLib/IcuLib.h
index 22027f6bc0..cc1fc5754b 100644
--- a/Silicon/Marvell/Library/IcuLib/IcuLib.h
+++ b/Silicon/Marvell/Library/IcuLib/IcuLib.h
@@ -22,7 +22,7 @@
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
-#define ICU_REG_BASE(Cp) (ArmadaSoCDescCpBaseGet (CpIndex) + 0x1E0000)
+#define ICU_REG_BASE(CpIndex) (ArmadaSoCDescCpBaseGet (CpIndex) + 0x1E0000)
#define ICU_GROUP_REGISTER_BASE_OFFSET 0x10
#define ICU_SET_SPI_AL(x) (0x10 + (ICU_GROUP_REGISTER_BASE_OFFSET * x))
@@ -35,7 +35,7 @@
#define ICU_IS_EDGE_OFFSET 28
#define ICU_GROUP_OFFSET 29
-#define ICU_MAX_SUPPORTED_UNITS 2
-#define ICU_MAX_IRQS_PER_CP 64
+#define ICU_MAX_SUPPORTED_UNITS 3
+#define ICU_SPI_OFFSET(CpIndex) ((CpIndex) * 32)
#define MAX_ICU_IRQS 207
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
b/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
index 83006ebd8a..fea820f9ed 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
@@ -11,28 +11,41 @@
**/
-#define CP_GIC_SPI_CP0_PCI0 64
-#define CP_GIC_SPI_CP0_PCI1 65
-#define CP_GIC_SPI_CP0_PCI2 66
-#define CP_GIC_SPI_CP0_SDMMC 67
-#define CP_GIC_SPI_PP2_CP0_PORT0 69, 72, 75, 78, 81, 127
-#define CP_GIC_SPI_PP2_CP0_PORT1 70, 73, 76, 79, 82, 126
-#define CP_GIC_SPI_PP2_CP0_PORT2 71, 74, 77, 80, 83, 125
-#define CP_GIC_SPI_CP0_EIP_RNG0 105
-#define CP_GIC_SPI_CP0_USB_H1 112
-#define CP_GIC_SPI_CP0_USB_H0 113
-#define CP_GIC_SPI_CP0_SATA_H0 114
-#define CP_GIC_SPI_CP0_UART0 121
-#define CP_GIC_SPI_CP0_UART1 122
+#define CP_GIC_SPI_CP0_SDMMC 64
+#define CP_GIC_SPI_PP2_CP0_PORT0 65, 68, 71, 74, 77, 90
+#define CP_GIC_SPI_PP2_CP0_PORT1 66, 69, 72, 75, 78, 89
+#define CP_GIC_SPI_PP2_CP0_PORT2 67, 70, 73, 76, 79, 88
+#define CP_GIC_SPI_CP0_EIP_RNG0 80
+#define CP_GIC_SPI_CP0_USB_H1 81
+#define CP_GIC_SPI_CP0_USB_H0 82
+#define CP_GIC_SPI_CP0_SATA_H0 83
+#define CP_GIC_SPI_CP0_UART0 84
+#define CP_GIC_SPI_CP0_UART1 85
+#define CP_GIC_SPI_CP0_UART2 86
+#define CP_GIC_SPI_CP0_UART3 87
-#define CP_GIC_SPI_CP1_PCI0 288
-#define CP_GIC_SPI_CP1_PCI1 289
-#define CP_GIC_SPI_CP1_PCI2 290
-#define CP_GIC_SPI_CP1_SDMMC 291
-#define CP_GIC_SPI_PP2_CP1_PORT0 293, 296, 299, 302, 305, 351
-#define CP_GIC_SPI_PP2_CP1_PORT1 294, 297, 300, 303, 306, 350
-#define CP_GIC_SPI_PP2_CP1_PORT2 295, 298, 301, 304, 307, 349
-#define CP_GIC_SPI_CP1_EIP_RNG0 329
-#define CP_GIC_SPI_CP1_USB_H1 336
-#define CP_GIC_SPI_CP1_USB_H0 337
-#define CP_GIC_SPI_CP1_SATA_H0 338
+#define CP_GIC_SPI_CP1_SDMMC 96
+#define CP_GIC_SPI_PP2_CP1_PORT0 97, 100, 103, 106, 109, 122
+#define CP_GIC_SPI_PP2_CP1_PORT1 98, 101, 104, 107, 110, 121
+#define CP_GIC_SPI_PP2_CP1_PORT2 99, 102, 105, 108, 111, 120
+#define CP_GIC_SPI_CP1_EIP_RNG0 112
+#define CP_GIC_SPI_CP1_USB_H1 113
+#define CP_GIC_SPI_CP1_USB_H0 114
+#define CP_GIC_SPI_CP1_SATA_H0 115
+#define CP_GIC_SPI_CP1_UART0 116
+#define CP_GIC_SPI_CP1_UART1 117
+#define CP_GIC_SPI_CP1_UART2 118
+#define CP_GIC_SPI_CP1_UART3 119
+
+#define CP_GIC_SPI_CP2_SDMMC 288
+#define CP_GIC_SPI_PP2_CP2_PORT0 289, 292, 295, 298, 301, 314
+#define CP_GIC_SPI_PP2_CP2_PORT1 290, 293, 296, 299, 302, 313
+#define CP_GIC_SPI_PP2_CP2_PORT2 291, 294, 297, 300, 303, 312
+#define CP_GIC_SPI_CP2_EIP_RNG0 304
+#define CP_GIC_SPI_CP2_USB_H1 305
+#define CP_GIC_SPI_CP2_USB_H0 306
+#define CP_GIC_SPI_CP2_SATA_H0 307
+#define CP_GIC_SPI_CP2_UART0 308
+#define CP_GIC_SPI_CP2_UART1 309
+#define CP_GIC_SPI_CP2_UART2 310
+#define CP_GIC_SPI_CP2_UART3 311
diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.c
b/Silicon/Marvell/Library/IcuLib/IcuLib.c
index 4d9f17445e..e4cb993c7e 100644
--- a/Silicon/Marvell/Library/IcuLib/IcuLib.c
+++ b/Silicon/Marvell/Library/IcuLib/IcuLib.c
@@ -16,73 +16,34 @@
STATIC EFI_EVENT mEfiExitBootServicesEvent;
STATIC CONST ICU_IRQ IrqMapNonSecure[] = {
- {22, 0, IcuIrqTypeLevel}, /* PCIx4 INT A interrupt */
- {23, 1, IcuIrqTypeLevel}, /* PCIx1 INT A interrupt */
- {24, 2, IcuIrqTypeLevel}, /* PCIx1 INT A interrupt */
- {27, 3, IcuIrqTypeLevel}, /* SD/MMC */
- {33, 4, IcuIrqTypeLevel}, /* PPv2 DBG AXI monitor */
- {34, 4, IcuIrqTypeLevel}, /* HB1 AXI monitor */
- {35, 4, IcuIrqTypeLevel}, /* AP AXI monitor */
- {36, 4, IcuIrqTypeLevel}, /* PPv2 AXI monitor */
- {39, 5, IcuIrqTypeLevel}, /* PPv2 Irq */
- {40, 6, IcuIrqTypeLevel}, /* PPv2 Irq */
- {41, 7, IcuIrqTypeLevel}, /* PPv2 Irq */
- {43, 8, IcuIrqTypeLevel}, /* PPv2 Irq */
- {44, 9, IcuIrqTypeLevel}, /* PPv2 Irq */
- {45, 10, IcuIrqTypeLevel}, /* PPv2 Irq */
- {47, 11, IcuIrqTypeLevel}, /* PPv2 Irq */
- {48, 12, IcuIrqTypeLevel}, /* PPv2 Irq */
- {49, 13, IcuIrqTypeLevel}, /* PPv2 Irq */
- {51, 14, IcuIrqTypeLevel}, /* PPv2 Irq */
- {52, 15, IcuIrqTypeLevel}, /* PPv2 Irq */
- {53, 16, IcuIrqTypeLevel}, /* PPv2 Irq */
- {55, 17, IcuIrqTypeLevel}, /* PPv2 Irq */
- {56, 18, IcuIrqTypeLevel}, /* PPv2 Irq */
- {57, 19, IcuIrqTypeLevel}, /* PPv2 Irq */
- {59, 20, IcuIrqTypeLevel}, /* PPv2 Irq */
- {60, 21, IcuIrqTypeLevel}, /* PPv2 Irq */
- {61, 22, IcuIrqTypeLevel}, /* PPv2 Irq */
- {63, 23, IcuIrqTypeLevel}, /* PPv2 Irq */
- {64, 24, IcuIrqTypeLevel}, /* PPv2 Irq */
- {65, 25, IcuIrqTypeLevel}, /* PPv2 Irq */
- {67, 26, IcuIrqTypeLevel}, /* PPv2 Irq */
- {68, 27, IcuIrqTypeLevel}, /* PPv2 Irq */
- {69, 28, IcuIrqTypeLevel}, /* PPv2 Irq */
- {71, 29, IcuIrqTypeLevel}, /* PPv2 Irq */
- {72, 30, IcuIrqTypeLevel}, /* PPv2 Irq */
- {73, 31, IcuIrqTypeLevel}, /* PPv2 Irq */
- {78, 32, IcuIrqTypeLevel}, /* MG Irq */
- {79, 33, IcuIrqTypeLevel}, /* GPIO 56-63 */
- {80, 34, IcuIrqTypeLevel}, /* GPIO 48-55 */
- {81, 35, IcuIrqTypeLevel}, /* GPIO 40-47 */
- {82, 36, IcuIrqTypeLevel}, /* GPIO 32-39 */
- {83, 37, IcuIrqTypeLevel}, /* GPIO 24-31 */
- {84, 38, IcuIrqTypeLevel}, /* GPIO 16-23 */
- {85, 39, IcuIrqTypeLevel}, /* GPIO 8-15 */
- {86, 40, IcuIrqTypeLevel}, /* GPIO 0-7 */
- {88, 41, IcuIrqTypeLevel}, /* EIP-197 ring-0 */
- {89, 42, IcuIrqTypeLevel}, /* EIP-197 ring-1 */
- {90, 43, IcuIrqTypeLevel}, /* EIP-197 ring-2 */
- {91, 44, IcuIrqTypeLevel}, /* EIP-197 ring-3 */
- {92, 45, IcuIrqTypeLevel}, /* EIP-197 int */
- {95, 46, IcuIrqTypeLevel}, /* EIP-150 Irq */
- {102, 47, IcuIrqTypeLevel}, /* USB3 Device Irq */
- {105, 48, IcuIrqTypeLevel}, /* USB3 Host-1 Irq */
- {106, 49, IcuIrqTypeLevel}, /* USB3 Host-0 Irq */
- {107, 50, IcuIrqTypeLevel}, /* SATA Host-1 Irq */
- {109, 50, IcuIrqTypeLevel}, /* SATA Host-0 Irq */
- {115, 52, IcuIrqTypeLevel}, /* NAND Irq */
- {117, 53, IcuIrqTypeLevel}, /* SPI-1 Irq */
- {118, 54, IcuIrqTypeLevel}, /* SPI-0 Irq */
- {120, 55, IcuIrqTypeLevel}, /* I2C 0 Irq */
- {121, 56, IcuIrqTypeLevel}, /* I2C 1 Irq */
- {122, 57, IcuIrqTypeLevel}, /* UART 0 Irq */
- {123, 58, IcuIrqTypeLevel}, /* UART 1 Irq */
- {124, 59, IcuIrqTypeLevel}, /* UART 2 Irq */
- {125, 60, IcuIrqTypeLevel}, /* UART 3 Irq */
- {127, 61, IcuIrqTypeLevel}, /* GOP-3 Irq */
- {128, 62, IcuIrqTypeLevel}, /* GOP-2 Irq */
- {129, 63, IcuIrqTypeLevel}, /* GOP-0 Irq */
+ {27, 0, IcuIrqTypeLevel}, /* SD/MMC */
+ {39, 1, IcuIrqTypeLevel}, /* PPv2 Irq */
+ {40, 2, IcuIrqTypeLevel}, /* PPv2 Irq */
+ {41, 3, IcuIrqTypeLevel}, /* PPv2 Irq */
+ {43, 4, IcuIrqTypeLevel}, /* PPv2 Irq */
+ {44, 5, IcuIrqTypeLevel}, /* PPv2 Irq */
+ {45, 6, IcuIrqTypeLevel}, /* PPv2 Irq */
+ {47, 7, IcuIrqTypeLevel}, /* PPv2 Irq */
+ {48, 8, IcuIrqTypeLevel}, /* PPv2 Irq */
+ {49, 9, IcuIrqTypeLevel}, /* PPv2 Irq */
+ {51, 10, IcuIrqTypeLevel}, /* PPv2 Irq */
+ {52, 11, IcuIrqTypeLevel}, /* PPv2 Irq */
+ {53, 12, IcuIrqTypeLevel}, /* PPv2 Irq */
+ {55, 13, IcuIrqTypeLevel}, /* PPv2 Irq */
+ {56, 14, IcuIrqTypeLevel}, /* PPv2 Irq */
+ {57, 15, IcuIrqTypeLevel}, /* PPv2 Irq */
+ {88, 16, IcuIrqTypeLevel}, /* EIP-197 ring-0 */
+ {105, 17, IcuIrqTypeLevel}, /* USB3 Host-1 Irq */
+ {106, 18, IcuIrqTypeLevel}, /* USB3 Host-0 Irq */
+ {107, 19, IcuIrqTypeLevel}, /* SATA Host-1 Irq */
+ {109, 19, IcuIrqTypeLevel}, /* SATA Host-0 Irq */
+ {122, 20, IcuIrqTypeLevel}, /* UART 0 Irq */
+ {123, 21, IcuIrqTypeLevel}, /* UART 1 Irq */
+ {124, 22, IcuIrqTypeLevel}, /* UART 2 Irq */
+ {125, 23, IcuIrqTypeLevel}, /* UART 3 Irq */
+ {127, 24, IcuIrqTypeLevel}, /* GOP-3 Irq */
+ {128, 25, IcuIrqTypeLevel}, /* GOP-2 Irq */
+ {129, 26, IcuIrqTypeLevel}, /* GOP-0 Irq */
};
/*
@@ -177,7 +138,7 @@ IcuConfigure (
/* Get the base of the GIC SPI ID in the MSI message */
SpiBase = IcuDesc->IcuSpiBase;
/* Get multiple CP110 instances SPI ID shift */
- SpiOffset = CpIndex * ICU_MAX_IRQS_PER_CP;
+ SpiOffset = ICU_SPI_OFFSET (CpIndex);
/* Get MSI addresses per interrupt group */
Msi = IcuDesc->IcuMsi;
@@ -230,7 +191,7 @@ IcuClearGicSpi (
/* Get the base of the GIC SPI ID in the MSI message */
SpiBase = IcuDesc->IcuSpiBase;
/* Get multiple CP110 instances SPI ID shift */
- SpiOffset = CpIndex * ICU_MAX_IRQS_PER_CP;
+ SpiOffset = ICU_SPI_OFFSET (CpIndex);
/* Get MSI addresses per interrupt group */
Msi = IcuDesc->IcuMsi;
@@ -254,10 +215,6 @@ IcuCleanUp (
IcuDesc = Context;
CpCount = FixedPcdGet8 (PcdMaxCpCount);
- if (CpCount > ICU_MAX_SUPPORTED_UNITS) {
- CpCount = ICU_MAX_SUPPORTED_UNITS;
- }
-
for (CpIndex = 0; CpIndex < CpCount; CpIndex++) {
IcuClearGicSpi (CpIndex, IcuDesc);
}
@@ -272,18 +229,8 @@ ArmadaIcuInitialize (
UINTN CpCount, CpIndex;
EFI_STATUS Status;
- /*
- * Due to limited amount of interrupt lanes, only 2 units can be
- * wired to the GIC.
- */
CpCount = FixedPcdGet8 (PcdMaxCpCount);
- if (CpCount > ICU_MAX_SUPPORTED_UNITS) {
- DEBUG ((DEBUG_ERROR,
- "%a: Default ICU to GIC mapping is available for maximum %d CP110 units",
- __FUNCTION__,
- ICU_MAX_SUPPORTED_UNITS));
- CpCount = ICU_MAX_SUPPORTED_UNITS;
- }
+ ASSERT (CpCount <= ICU_MAX_SUPPORTED_UNITS);
/* Obtain SoC description of the ICU */
Status = ArmadaSoCDescIcuGet (&IcuDesc);
--
2.29.0
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