Implement QueryPerformanceCounter() and QueryPerformanceFrequency()
for both Unix and Windows.
This has been tested in both Unix and Windows in an application using
TimerLib.
Signed-off-by: Derek Lin
Signed-off-by: Kitty Chen
---
EmulatorPkg/Unix/Host/EmuThunk.c | 40 +-
Reviewed-by: Sai Chaganty
-Original Message-
From: Kubacki, Michael A
Sent: Monday, January 27, 2020 11:01 PM
To: devel@edk2.groups.io
Cc: Bi, Dandan ; Chaganty, Rangasai V
; Chiu, Chasel ;
Desimone, Nathaniel L ; Dong, Eric
; Gao, Liming
Subject: [edk2-platforms][PATCH V1 1/1] Feat
https://bugzilla.tianocore.org/show_bug.cgi?id=2420
Based on the following package with changes to merge into
CryptoPkg.
https://github.com/microsoft/mu_plus/tree/dev/201908/SharedCryptoPkg
Add Crypto library instances and modules that consume/produce
the EDK II Crypto Protocols/PPIs to the Cryp
https://bugzilla.tianocore.org/show_bug.cgi?id=2420
Add X509ConstructCertificateStackV() to BaseCryptLib that is
identical in behavior to X509ConstructCertificateStack(), but
it takes a VA_LIST parameter for the variable argument list.
The VA_LIST form of this function is required for BaseCryptLi
https://bugzilla.tianocore.org/show_bug.cgi?id=2420
Based on the following package with changes to merge into CryptoPkg.
https://github.com/microsoft/mu_plus/tree/dev/201908/SharedCryptoPkg
* Add X509ConstructCertificateStackV() to BaseCryptLib. This is required to
have a VA_LIST version of X
ASSERT in SetTime_Conf and SetWakeupTime_Conf Consistency Test.
SCT Test expect return as Invalid Parameter.
So removed ASSERT().
Signed-off-by: Gaurav Jain
---
EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClock.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/Em
Reviewed-by: Chasel Chiu
> -Original Message-
> From: Kubacki, Michael A
> Sent: Tuesday, January 28, 2020 3:01 PM
> To: devel@edk2.groups.io
> Cc: Bi, Dandan ; Chaganty, Rangasai V
> ; Chiu, Chasel ;
> Desimone, Nathaniel L ; Dong, Eric
> ; Gao, Liming
> Subject: [edk2-platforms][PAT
https://bugzilla.tianocore.org/show_bug.cgi?id=2495
https://bugzilla.tianocore.org/show_bug.cgi?id=2496
Structured PCD processing requires a host POSIX build
environment. If the Structure PCD application can not
be built using the default environment under Windows, then
retry the build after sett
This commit introduces a Unified Hash API to calculate hash using a
hashing algorithm specified by the PCD, PcdHashApiLibPolicy. This library
interfaces with the various hashing API, such as, MD4, MD5, SHA1, SHA256,
SHA512 and SM3_256 implemented in BaseCryptLib. The user can calculate
the desired
Added CryptoPkg Token Space GUID to be able to define PCDs.
Cc: Jiewen Yao
Cc: Jian J Wang
Cc: Michael D Kinney
Signed-off-by: Sukerkar, Amol N
---
Notes:
v6
- removed file CryptoPkgTokenSpace.h
v7
- fixed typo
CryptoPkg/CryptoPkg.dec | 6 +-
1 file changed, 5 inser
Currently, the UEFI drivers using the SHA/SM3 hashing algorithms use hard-coded
API to calculate the hash, for instance, sha_256(...), etc. Since SHA384 and/or
SM3_256 are being increasingly adopted for robustness, it becomes cumbersome to
modify each driver that calls into hash calculating API.
T
https://bugzilla.tianocore.org/show_bug.cgi?id=2494
When using structured PCDs, a C application is auto generated
to fill in the structured PCD value. The C application uses
the standard include files , , and .
This C application also supports include paths from package DEC
files when a structure
The copyright dates needed to be updated to 2020. I updated those locally
before being pushed.
Reviewed-by: Michael Kubacki
Thanks,
Michael
> -Original Message-
> From: Agyeman, Prince
> Sent: Tuesday, January 14, 2020 9:28 AM
> To: devel@edk2.groups.io
> Cc: Zhang, Shenglei ; Chiu, C
https://bugzilla.tianocore.org/show_bug.cgi?id=2493
The BaseCryptLib was expanded to add the HkdfSha256ExtractAndExpand()
service in the following commit:
https://github.com/tianocore/edk2/commit/4b1b7c1913092d73d689d8086dcfa579c0217dc8
When BaseCryptLibNull was added in the commit below, this n
Ah, OK! It is clear to me now. Thanks, Mike!
~ Amol
-Original Message-
From: Kinney, Michael D
Sent: Wednesday, January 29, 2020 4:16 PM
To: Sukerkar, Amol N ; devel@edk2.groups.io; Kinney,
Michael D
Cc: Yao, Jiewen ; Wang, Jian J ;
Agrawal, Sachin ; Musti, Srinivas
; Lakkimsetti, S
Hi Amol,
The feedback I received was for the use of the term
"Base" in library class names. You did the correct
change by changing the class name from "BaseHashLib"
to "HashApiLib".
It is correct to use the term "Base" in the name of
a library instance if the library as implemented is
compatibl
Hi Mike,
Question about point 4. Could you help me clear the confusion?
4) The name of the HashApiLib instance should be "BaseHashApiLib" and the
should be in the CryptoPkg/Library/BaseHashApiLib directory with
files BashHashApiLib.inf, BaseHashApiLib.c, and BaseHashApiLib.uni.
BASE_NAME
For supporting VCPU hotplug with SMM enabled/required, QEMU offers the
(dynamically detectable) feature called "SMRAM at default SMBASE". When
the feature is enabled, the firmware can lock down the 128 KB range
starting at the default SMBASE; that is, the [0x3_, 0x4_]
interval. The goal is
Before adding another SMM-related, and therefore Q35-only, dynamically
detectable feature, extract the current board type check from
Q35TsegMbytesInitialization() to a standalone function.
Cc: Ard Biesheuvel
Cc: Jordan Justen
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1512
Signed-off-by
In a subsequent patch, we'll introduce new DRAM controller macros in
"Q35MchIch9.h". Their names are too long for the currently available
vertical whitespace, so increase the latter first.
There is no functional change in this patch ("git show -b" displays
nothing).
Cc: Ard Biesheuvel
Cc: Jordan
Introduce the Q35SmramAtDefaultSmbaseInitialization() function for
detecting the "SMRAM at default SMBASE" feature.
For now, the function is only a skeleton, so that we can gradually build
upon the result while the result is hard-coded as FALSE. The actual
detection will occur in a later patch.
C
In Intel datasheet 316966-002 (the "q35 spec"), Table 5-1 "DRAM Controller
Register Address Map (D0:F0)" leaves the byte register at config space
offset 0x9C unused.
On QEMU's Q35 board, for detecting the "SMRAM at default SMBASE" feature,
firmware is expected to write MCH_DEFAULT_SMBASE_QUERY (0x
During normal boot, when EFI_DXE_SMM_READY_TO_LOCK_PROTOCOL is installed
by platform BDS, the SMM IPL locks SMRAM (TSEG) through
EFI_SMM_ACCESS2_PROTOCOL.Lock(). See SmmIplReadyToLockEventNotify() in
"MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c".
During S3 resume, S3Resume2Pei locks SMRAM (TSEG) throug
Now that the SMRAM at the default SMBASE is honored everywhere necessary,
implement the actual detection. The (simple) steps are described in
previous patch "OvmfPkg/IndustryStandard: add MCH_DEFAULT_SMBASE* register
macros".
Regarding CSM_ENABLE builds: according to the discussion with Jiewen at
The permanent PEI RAM that is published on the normal boot path starts
strictly above MEMFD_BASE_ADDRESS (8 MB -- see the FDF files), regardless
of whether PEI decompression will be necessary on S3 resume due to
SMM_REQUIRE. Therefore the normal boot permanent PEI RAM never overlaps
with the SMRAM
When OVMF runs in a SEV guest, the initial SMM Save State Map is
(1) allocated as EfiBootServicesData type memory in OvmfPkg/PlatformPei,
function AmdSevInitialize(), for preventing unintended information
sharing with the hypervisor;
(2) decrypted in AmdSevDxe;
(3) re-encrypted in OvmfPk
In the DXE phase and later, it is possible for a module to dynamically
determine whether a CSM is enabled. An example can be seen in commit
855743f71774 ("OvmfPkg: prevent 64-bit MMIO BAR degradation if there is no
CSM", 2016-05-25).
SEC and PEI phase modules cannot check the Legacy BIOS Protocol
Ref:https://bugzilla.tianocore.org/show_bug.cgi?id=1512
Repo: https://github.com/lersek/edk2.git
Branch: smram_at_default_smbase_bz_1512_wave_1_v2
Supersedes: <20190924113505.27272-1-ler...@redhat.com>
V1 is archived at:
- http://mid.mail-archive.com/20190924113505.27272-1-lersek
The 128KB SMRAM at the default SMBASE will be used for protecting the
initial SMI handler for hot-plugged VCPUs. After platform reset, the SMRAM
in question is open (and looks just like RAM). When BDS signals
EFI_DXE_MM_READY_TO_LOCK_PROTOCOL (and so TSEG is locked down), we're
going to lock the SM
Amol,
1) Typo in CryptoPkg.dec. Should be Crypto Package, not Security package.
[Guids]
## Security package token space guid.
2) CryptoPkg.dec/uni. I see the default value for PcdHashApiLibPolicy
is 0x04. This is documented to be SHA256. The DEC/UNI file
descriptions of this PCD
On Wed, Jan 29, 2020 at 11:50:15 +0100, Ard Biesheuvel wrote:
> On Wed, 29 Jan 2020 at 11:43, Leif Lindholm wrote:
> >
> > On Wed, Jan 29, 2020 at 14:48:38 +0530, Meenakshi Aggarwal wrote:
> > > Add Maintainer and Reviewer for NXP Package.
> > >
> > > Signed-off-by: Meenakshi Aggarwal
> > > ---
>
On 01/29/20 15:43, Philippe Mathieu-Daudé wrote:
> Hi Laszlo,
>
> On 1/24/20 12:40 PM, Laszlo Ersek wrote:
>> On 10/24/19 17:12, Philippe Mathieu-Daudé wrote:
>>> This patch is fine then.
>>>
>>> Since the QEMU spec is RFC and not merged, I'm worried it might
>>> change. I'd rather review this pa
On 01/29/20 13:12, Anthony PERARD wrote:
> Update gEfiMdePkgTokenSpaceGuid.PcdFSBClock so it can have the correct
> value when SecPeiDxeTimerLibCpu start to use it for the APIC timer.
>
> Currently, nothing appear to use the value in PcdFSBClock before
> XenPlatformPei had a chance to set it even
On 01/29/20 13:12, Anthony PERARD wrote:
> Calculate the frequency of the APIC timer that Xen provides.
>
> Even though the frequency is currently hard-coded, it isn't part of
> the public ABI that Xen provides and thus may change at any time. OVMF
> needs to determine the frequency by an other me
On 01/29/20 13:12, Anthony PERARD wrote:
> We are going to use new fields from the Xen headers. Apply the EDK2
> coding style so that the code that is going to use it doesn't look out
> of place.
>
> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2490
> Signed-off-by: Anthony PERARD
> ---
>
On 01/29/20 13:12, Anthony PERARD wrote:
> We are going to want to change the value of PcdFSBClock at run time in
> OvmfXen, so move it to the PcdsDynamic section.
>
> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2490
> Signed-off-by: Anthony PERARD
> ---
> CC: Bob Feng
> CC: Liming Gao
On 01/29/20 13:12, Anthony PERARD wrote:
> To avoid nasm generating a warning, replace the macro by the value
> expected to be stored in eax.
> Ia32/XenPVHMain.asm:76: warning: dword data exceeds bounds
>
> Reported-by: Laszlo Ersek
> Signed-off-by: Anthony PERARD
> ---
> OvmfPkg/XenResetVect
Hi Laszlo,
On 1/24/20 12:40 PM, Laszlo Ersek wrote:
On 10/24/19 17:12, Philippe Mathieu-Daudé wrote:
On 10/24/19 12:29 PM, Laszlo Ersek wrote:
On 10/23/19 14:05, Philippe Mathieu-Daudé wrote:
Hi Laszlo,
On 10/23/19 12:15 AM, Laszlo Ersek wrote:
In v1.5.0, QEMU's "pc" (i440fx) board gained a
We are going to use new fields from the Xen headers. Apply the EDK2
coding style so that the code that is going to use it doesn't look out
of place.
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2490
Signed-off-by: Anthony PERARD
---
OvmfPkg/Include/IndustryStandard/Xen/xen.h | 17
Patch series available in this git branch:
git://xenbits.xen.org/people/aperard/ovmf.git br.apic-timer-freq-v1
Hi,
OvmfXen uses the APIC timer, but with an hard-coded frequency that may change
as pointed out here:
https://edk2.groups.io/g/devel/message/45185
<20190808134423.ybqg3qkpw5ucfzk4@A
To avoid nasm generating a warning, replace the macro by the value
expected to be stored in eax.
Ia32/XenPVHMain.asm:76: warning: dword data exceeds bounds
Reported-by: Laszlo Ersek
Signed-off-by: Anthony PERARD
---
OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm | 2 +-
1 file changed, 1 insertio
We are going to want to change the value of PcdFSBClock at run time in
OvmfXen, so move it to the PcdsDynamic section.
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2490
Signed-off-by: Anthony PERARD
---
CC: Bob Feng
CC: Liming Gao
---
MdePkg/MdePkg.dec | 8
1 file changed, 4 in
Calculate the frequency of the APIC timer that Xen provides.
Even though the frequency is currently hard-coded, it isn't part of
the public ABI that Xen provides and thus may change at any time. OVMF
needs to determine the frequency by an other mean.
Fortunately, Xen provides a way to determines
Update gEfiMdePkgTokenSpaceGuid.PcdFSBClock so it can have the correct
value when SecPeiDxeTimerLibCpu start to use it for the APIC timer.
Currently, nothing appear to use the value in PcdFSBClock before
XenPlatformPei had a chance to set it even though TimerLib is included
in modules runned befor
On Wed, 29 Jan 2020 at 11:43, Leif Lindholm wrote:
>
> On Wed, Jan 29, 2020 at 14:48:38 +0530, Meenakshi Aggarwal wrote:
> > Add Maintainer and Reviewer for NXP Package.
> >
> > Signed-off-by: Meenakshi Aggarwal
> > ---
> > Maintainers.txt | 7 ++-
> > 1 file changed, 6 insertions(+), 1 dele
On Wed, Jan 29, 2020 at 14:48:38 +0530, Meenakshi Aggarwal wrote:
> Add Maintainer and Reviewer for NXP Package.
>
> Signed-off-by: Meenakshi Aggarwal
> ---
> Maintainers.txt | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/Maintainers.txt b/Maintainers.txt
> index
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