On 1/13/2018 1:09 AM, Thomas Monjalon Wrote:
04/12/2017 02:50, Jia He:
move the common part of rte_ring.h into rte_ring_generic.h.
move the memory barrier part into update_tail().
no functional changes here.
[...]
--- /dev/null
+++ b/lib/librte_ring/rte_ring_generic.h
@@ -0,0 +1,195
cific implementation for enqueue/dequeue barrier
V2: let users choose whether using load_acquire/store_release
V1: rte_smp_rmb() between 2 loads
Jia He (3):
eal/arm64: remove the braces {} for dmb() and dsb()
ring: introduce new header file to include common functions
ring: introduce new he
for the code as follows:
if (condition)
rte_smp_rmb();
else
rte_smp_wmb();
Without this patch, compiler will report this error:
error: 'else' without a previous 'if'
Fixes: 84733fd0d75e ("eal/arm64: fix memory barrier definition")
Signed-off-by:
Move the common part of rte_ring.h into rte_ring_generic.h.
Move the memory barrier part into update_tail().
No functional changes here.
Signed-off-by: Jia He
Suggested-by: Jerin Jacob
Suggested-by: Ananyev Konstantin
Acked-by: Jerin Jacob
Acked-by: Olivier Matz
---
lib/librte_eventdev
ml/archives/dev/2017-October/080861.html
Signed-off-by: Jia He
Suggested-by: Jerin Jacob
Acked-by: Jerin Jacob
Acked-by: Olivier Matz
Acked-by: Jianbo Liu
---
config/common_linuxapp | 2 +
lib/librte_ring/Makefile | 3 +-
lib/librte_ring/rte_ring.h | 14 ++-
Hi Thomas
On 1/17/2018 4:24 PM, Thomas Monjalon Wrote:
17/01/2018 05:03, Jia He:
To support C11 memory model barrier, 2 options are suggested by Jerin:
1. use rte_smp_rmb
2. use load_acquire/store_release(refer to [1]).
CONFIG_RTE_RING_USE_C11_MEM_MODEL is provided, and by default it is &q
On 1/19/2018 7:52 AM, Thomas Monjalon Wrote:
17/01/2018 10:09, Thomas Monjalon:
17/01/2018 09:47, Jia He:
Hi Thomas
On 1/17/2018 4:24 PM, Thomas Monjalon Wrote:
17/01/2018 05:03, Jia He:
To support C11 memory model barrier, 2 options are suggested by Jerin:
1. use rte_smp_rmb
2. use
Hi Hermant
On 1/20/2018 12:47 AM, Hemant Agrawal Wrote:
Hi Olivier,
On Fri, Jan 19, 2018 at 07:45:30PM +0530, Hemant Agrawal wrote:
Hi Jia,
On 1/17/2018 9:33 AM, Jia He wrote:
Move the common part of rte_ring.h into rte_ring_generic.h.
Move the memory barrier part into update_tail().
No
for the code as follows:
if (condition)
rte_smp_rmb();
else
rte_smp_wmb();
Without this patch, compiler will report this error:
error: 'else' without a previous 'if'
Fixes: 84733fd0d75e ("eal/arm64: fix memory barrier definition")
Signed-off-by:
mall patches
V3: arch specific implementation for enqueue/dequeue barrier
V2: let users choose whether using load_acquire/store_release
V1: rte_smp_rmb() between 2 loads
Jia He (3):
eal/arm64: remove the braces {} for dmb() and dsb()
ring: introduce new header file to include common functions
ring
-October/080861.html
Signed-off-by: Jia He
Suggested-by: Jerin Jacob
Acked-by: Jerin Jacob
Acked-by: Olivier Matz
Acked-by: Jianbo Liu
---
config/common_armv8a_linuxapp | 2 +
config/common_base | 5 +
lib/librte_ring/Makefile | 3 +-
lib/librte_ring/rte_
Move the common part of rte_ring.h into rte_ring_generic.h.
Move the memory barrier part into update_tail().
No functional changes here.
Signed-off-by: Jia He
Suggested-by: Jerin Jacob
Suggested-by: Ananyev Konstantin
Acked-by: Jerin Jacob
Acked-by: Olivier Matz
---
lib/librte_eventdev
Hi hermant
On 1/22/2018 1:15 PM, Hemant Agrawal Wrote:
Hi Jia,
On 1/22/2018 7:23 AM, Jia He wrote:
This is BSD-2-freebsd, which is not a approved license for DPDK.
Can you ask Kip Macy, if he/she is ok to re-license it with BSD-3?
Please check with legal, if you can just keep the copyright
Signed-off-by: Jia He
---
lib/librte_ring/rte_ring.c | 66 +++---
lib/librte_ring/rte_ring.h | 66 +++---
lib/librte_ring/rte_ring_c11_mem.h | 65 +++--
lib/librte_ring
ecause X86 is strong memory order model
Signed-off-by: Jia He
Signed-off-by: jia...@hxt-semitech.com
Signed-off-by: jie2@hxt-semitech.com
Signed-off-by: bing.z...@hxt-semitech.com
---
lib/librte_ring/rte_ring.h | 8
1 file changed, 8 insertions(+)
diff --git a/lib/librte_ring/rte_ri
Hi Jerin
On 10/13/2017 1:23 AM, Jerin Jacob Wrote:
-Original Message-
Date: Thu, 12 Oct 2017 17:05:50 +
From: "Ananyev, Konstantin"
To: Olivier MATZ , Jia He
CC: "dev@dpdk.org" , "jia...@hxt-semitech.com"
, "jie2@hxt-semitech.c
On 10/13/2017 9:02 AM, Jia He Wrote:
Hi Jerin
On 10/13/2017 1:23 AM, Jerin Jacob Wrote:
-Original Message-
Date: Thu, 12 Oct 2017 17:05:50 +
[...]
On the same lines,
Jia He, jie2.liu, bing.zhao,
Is this patch based on code review or do you saw this issue on any of
the
Hi
On 10/13/2017 9:02 AM, Jia He Wrote:
Hi Jerin
On 10/13/2017 1:23 AM, Jerin Jacob Wrote:
-Original Message-
Date: Thu, 12 Oct 2017 17:05:50 +
[...]
On the same lines,
Jia He, jie2.liu, bing.zhao,
Is this patch based on code review or do you saw this issue on any of
the
Hi Jerin
On 10/13/2017 9:49 AM, Jerin Jacob Wrote:
-Original Message-
Date: Fri, 13 Oct 2017 09:16:31 +0800
From: Jia He
To: Jerin Jacob , "Ananyev, Konstantin"
Cc: Olivier MATZ , "dev@dpdk.org" ,
"jia...@hxt-semitech.com" ,
"jie2@h
Hi
On 10/13/2017 3:33 PM, Jianbo Liu Wrote:
The 10/13/2017 07:19, Jerin Jacob wrote:
-Original Message-
Date: Fri, 13 Oct 2017 09:16:31 +0800
From: Jia He
To: Jerin Jacob , "Ananyev, Konstantin"
Cc: Olivier MATZ , "dev@dpdk.org" ,
"jia...@hxt-semite
On 10/20/2017 4:02 AM, Ananyev, Konstantin Wrote:
-Original Message-
From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Ananyev, Konstantin
Sent: Thursday, October 19, 2017 3:15 PM
To: Zhao, Bing ; Jia He ; Jerin Jacob
Cc: Olivier MATZ ; dev@dpdk.org;
jia...@hxt-semitech.com
Hi Jerin
On 10/20/2017 1:43 PM, Jerin Jacob Wrote:
-Original Message-
[...]
dependant on each other.
Thus a memory barrier is neccessary.
Yes. The barrier is necessary.
In fact, upstream freebsd fixed this issue for arm64. DPDK ring
implementation is derived from freebsd's buf_ring
Hi Jerin
On 10/23/2017 6:06 PM, Jerin Jacob Wrote:
-Original Message-
Date: Mon, 23 Oct 2017 16:49:01 +0800
From: Jia He
To: Jerin Jacob
Cc: "Ananyev, Konstantin" , "Zhao, Bing"
, Olivier MATZ ,
"dev@dpdk.org" , "jia...@hxt-semitech.
Hi Jerin
On 10/25/2017 9:26 PM, Jerin Jacob Wrote:
-Original Message-
Date: Tue, 24 Oct 2017 10:04:26 +0800
From: Jia He
To: Jerin Jacob
Cc: "Ananyev, Konstantin" , "Zhao, Bing"
, Olivier MATZ ,
"dev@dpdk.org" , "jia...@hxt-semitech.
-
Date: Tue, 24 Oct 2017 10:04:26 +0800
From: Jia He
To: Jerin Jacob
Cc: "Ananyev, Konstantin" , "Zhao, Bing"
, Olivier MATZ ,
"dev@dpdk.org" , "jia...@hxt-semitech.com"
, "jie2@hxt-semitech.com"
, "bing.z...@hxt-semitech.com&quo
cons.head, __ATOMIC_ACQUIRE);
+ const uint32_t prod_tail = __atomic_load_n(&r->prod.tail,
__ATOMIC_ACQUIRE);
Cheers,
Jia
On 10/31/2017 7:14 PM, Jerin Jacob Wrote:
-Original Message-
Date: Tue, 31 Oct 2017 10:55:15 +0800
From: Jia He
To: Jerin Jacob
Cc: "Ananyev,
Hi Jerin
On 10/31/2017 7:14 PM, Jerin Jacob Wrote:
-Original Message-
Date: Tue, 31 Oct 2017 10:55:15 +0800
From: Jia He
To: Jerin Jacob
Cc: "Ananyev, Konstantin" , "Zhao, Bing"
, Olivier MATZ ,
"dev@dpdk.org" , "jia...@hxt-semitech.
Hi Jerin
On 11/2/2017 3:04 AM, Jerin Jacob Wrote:
Date: Thu, 2 Nov 2017 00:27:46 +0530
From: Jerin Jacob
To: Jia He
Cc: "Ananyev, Konstantin" ,
"Zhao, Bing" ,
Olivier MATZ ,
"dev@dpdk.org" ,
"jia...@hxt-semitech.com&qu
:
V2: let users choose whether using load_acquire/store_release
V1: rte_smp_rmb() between 2 loads
Signed-off-by: Jia He
Signed-off-by: jie2@hxt-semitech.com
Signed-off-by: bing.z...@hxt-semitech.com
Signed-off-by: jia...@hxt-semitech.com
Suggested-by: jerin.ja...@caviumnetworks.com
---
lib
ason.
I ever tested the difference with my debug patch, the difference is
minor, less than +-1%
--
Cheers,
Jia
Cheers,
Jia
On 10/31/2017 7:14 PM, Jerin Jacob Wrote:
-Original Message-
Date: Tue, 31 Oct 2017 10:55:15 +0800
From: Jia He
To: Jerin Jacob
Cc: "Ananyev,
Hi Ananyev
On 11/2/2017 9:26 PM, Ananyev, Konstantin Wrote:
Hi Jia,
-Original Message-
From: Jia He [mailto:hejia...@gmail.com]
Sent: Thursday, November 2, 2017 8:44 AM
To: jerin.ja...@caviumnetworks.com; dev@dpdk.org; olivier.m...@6wind.com
Cc: Ananyev, Konstantin ; Richardson
Hi Jerin
On 11/3/2017 1:23 AM, Jerin Jacob Wrote:
-Original Message-
Date: Thu, 2 Nov 2017 08:43:30 +
From: Jia He
To: jerin.ja...@caviumnetworks.com, dev@dpdk.org, olivier.m...@6wind.com
Cc: konstantin.anan...@intel.com, bruce.richard...@intel.com,
jianbo@arm.com
Hi Jerin
On 11/2/2017 4:57 PM, Jia He Wrote:
Hi， Jerin
please see my performance test below
On 11/2/2017 3:04 AM, Jerin Jacob Wrote:
[...]
Should it be like instead?
+#else
+ *old_head = __atomic_load_n(&r->cons.head, __ATOMIC_ACQUIRE);
+ const uint32_t pr
Hi Jerin
On 11/3/2017 8:56 PM, Jerin Jacob Wrote:
-Original Message-
[...]
g like that.
Ok, but how to distinguish following 2 options?
No clearly understood this question. For arm64 case, you can add
CONFIG_RTE_RING_USE_C11_MEM_MODEL=y in config/defconfig_arm64-armv8a-*
Sorry for
On 11/7/2017 12:36 PM, Jerin Jacob Wrote:
-Original Message-
On option could be to change the prototype of update_tail() and make
compiler accommodate it for zero cost for arm64(Which I think, it it the
case. But you can check the generated instructions)
If not, move, __rte_ring_do_deq
2017 16:34:30 +0800
From: Jia He
To: Jerin Jacob
Cc: dev@dpdk.org, olivier.m...@6wind.com, konstantin.anan...@intel.com,
bruce.richard...@intel.com, jianbo@arm.com, hemant.agra...@nxp.com,
jie2@hxt-semitech.com, bing.z...@hxt-semitech.com,
jia...@hxt-semitech.com
Subject: Re: [PATC
bsd/blob/master/sys/sys/buf_ring.h#L170
[3] http://dpdk.org/ml/archives/dev/2017-October/080861.html
---
Changelog:
V3: arch specific implementation for enqueue/dequeue barrier
V2: let users choose whether using load_acquire/store_release
V1: rte_smp_rmb() between 2 loads
Signed-off-by: Jia He
for the code as follows:
if (condition)
rte_smp_rmb();
else
rte_smp_wmb();
Without this patch, compiler will report this error:
error: 'else' without a previous 'if'
Signed-off-by: Jia He
Signed-off-by: jia...@hxt-semitech.com
---
lib/librte_eal/com
by default, CONFIG_RTE_RING_USE_C11_MEM_MODEL is y on arm64
Signed-off-by: Jia He
Signed-off-by: jia...@hxt-semitech.com
---
config/common_armv8a_linuxapp | 1 +
1 file changed, 1 insertion(+)
diff --git a/config/common_armv8a_linuxapp b/config/common_armv8a_linuxapp
index 6732d1e..1bf6e4d
move the common part of rte_ring.h into rte_ring_generic.h
move the memory barrier part into update_tail()
no functional changes here
Signed-off-by: Jia He
Suggested-by: Jerin Jacob
Suggested-by: Ananyev, Konstantin
---
lib/librte_eventdev/rte_event_ring.h | 6 +-
lib/librte_ring/Makefile
arm64 with CONFIG_RTE_RING_USE_C11_MEM_MODEL=n
---
Changelog:
V4: split into small patches
V3: arch specific implementation for enqueue/dequeue barrier
V2: let users choose whether using load_acquire/store_release
V1: rte_smp_rmb() between 2 loads
Jia He (4):
eal/arm64: remove the braces {} for dmb() and dsb()
ring: guar
ns.head will be recaculated after failure of
rte_atomic32_cmpset
There is no such issue on X86, because X86 is strong memory order model.
Signed-off-by: Jia He
Signed-off-by: jie2@hxt-semitech.com
Signed-off-by: bing.z...@hxt-semitech.com
---
lib/librte_ring/rte_ring.h | 10 ++
1 fil
_ring.h#L170
[2] http://dpdk.org/ml/archives/dev/2017-October/080861.html
Signed-off-by: Jia He
Suggested-by: Jerin Jacob
---
config/common_armv8a_linuxapp | 2 +
lib/librte_ring/Makefile | 3 +-
lib/librte_ring/rte_ring.h | 14 ++-
lib/librte_ring/rte_ring_
for the code as follows:
if (condition)
rte_smp_rmb();
else
rte_smp_wmb();
Without this patch, compiler will report this error:
error: 'else' without a previous 'if'
Fixes: 84733fd0d75e ("eal/arm64: fix memory barrier definition")
Signed-off-by: Jia
Hi Bruce
On 11/8/2017 8:15 PM, Bruce Richardson Wrote:
On Wed, Nov 08, 2017 at 09:54:37AM +, Jia He wrote:
We watched a rte panic of mbuf_autotest in our qualcomm arm64 server
due to a possible race condition.
To fix this race, there are 2 options as suggested by Jerin: 1. use
Hi Bruce
On 11/8/2017 6:28 PM, Bruce Richardson Wrote:
On Wed, Nov 08, 2017 at 06:17:10AM +, Jia He wrote:
for the code as follows:
if (condition)
rte_smp_rmb();
else
rte_smp_wmb();
Without this patch, compiler will report this error:
error: 'else' without a pr
On 11/9/2017 9:22 AM, Jia He Wrote:
Hi Bruce
On 11/8/2017 6:28 PM, Bruce Richardson Wrote:
On Wed, Nov 08, 2017 at 06:17:10AM +, Jia He wrote:
for the code as follows:
if (condition)
rte_smp_rmb();
else
rte_smp_wmb();
Without this patch, compiler will report this error:
error
Hi Jianbo
On 11/9/2017 11:21 AM, Jianbo Liu Wrote:
The 11/09/2017 11:14, Jia He wrote:
On 11/9/2017 9:22 AM, Jia He Wrote:
Hi Bruce
On 11/8/2017 6:28 PM, Bruce Richardson Wrote:
On Wed, Nov 08, 2017 at 06:17:10AM +, Jia He wrote:
for the code as follows:
if (condition
ithout architectures specific concerns.
Signed-off-by: Jia He
Signed-off-by: jie2@hxt-semitech.com
Signed-off-by: bing.z...@hxt-semitech.com
---
lib/librte_ring/rte_ring.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h
i
due to the milestone concerns, this is the 1st one
V4: split into small patches
V3: arch specific implementation for enqueue/dequeue barrier
V2: let users choose whether using load_acquire/store_release
V1: rte_smp_rmb() between 2 loads
Jia He (4):
eal/arm64: remove the braces {} for dmb() and dsb
On 11/9/2017 5:38 PM, Ananyev, Konstantin Wrote:
-Original Message-
From: Jianbo Liu [mailto:jianbo@arm.com]
Sent: Thursday, November 9, 2017 4:56 AM
To: Jia He
Cc: Richardson, Bruce ;
jerin.ja...@caviumnetworks.com; dev@dpdk.org; olivier.m...@6wind.com;
Ananyev, Konstantin
From: Jia He
We watched a rte panic of mbuf_autotest in our qualcomm arm64 server
(Amberwing) due to a possible race condition. To fix this race condition,
rmb() is needed to add between the 2 loads.
Already fuctionally tested on the machines as follows:
- on X86
- on arm64
---
Changelog
V6
his patch, the old cons.head will be recaculated after failure of
rte_atomic32_cmpset
There is no such issue on X86, because X86 is strong memory order model.
But rte_smp_rmb() doesn't have impact on runtime performance on X86, so
keep the same code without architectures specific concerns.
From: Jia He
To support C11 memory model barrier, 2 options are suggested by Jerin:
1. use rte_smp_rmb
2. use load_acquire/store_release
CONFIG_RTE_RING_USE_C11_MEM_MODEL is provided, and by default it is "y"
only on arm64 so far.
The reason why providing 2 options is due to the p
From: Jia He
move the common part of rte_ring.h into rte_ring_generic.h
move the memory barrier part into update_tail()
no functional changes here
Signed-off-by: Jia He
Suggested-by: Jerin Jacob
Suggested-by: Ananyev, Konstantin
---
lib/librte_eventdev/rte_event_ring.h | 6 +-
lib
for the code as follows:
if (condition)
rte_smp_rmb();
else
rte_smp_wmb();
Without this patch, compiler will report this error:
error: 'else' without a previous 'if'
Fixes: 84733fd0d75e ("eal/arm64: fix memory barrier definition")
Signed-off-by: Jia
chives/dev/2017-October/080861.html
Signed-off-by: Jia He
Suggested-by: Jerin Jacob
---
config/common_armv8a_linuxapp | 2 +
lib/librte_ring/Makefile | 3 +-
lib/librte_ring/rte_ring.h | 14 ++-
lib/librte_ring/rte_ring_c11_mem.h | 186 +++
r any suggestions
Cheers,
Jia
On 11/8/2017 11:11 PM, Jia He Wrote:
Hi Bruce
On 11/8/2017 8:15 PM, Bruce Richardson Wrote:
On Wed, Nov 08, 2017 at 09:54:37AM +0000, Jia He wrote:
We watched a rte panic of mbuf_autotest in our qualcomm arm64 server
due to a possible race condition.
To fix this race,
milestone concerns, this is the 2st
one. Also fix checkpatch.pl warnings
V4: split into small patches
V3: arch specific implementation for enqueue/dequeue barrier
V2: let users choose whether using load_acquire/store_release
V1: rte_smp_rmb() between 2 loads
Jia He (3):
eal/arm64: remove
for the code as follows:
if (condition)
rte_smp_rmb();
else
rte_smp_wmb();
Without this patch, compiler will report this error:
error: 'else' without a previous 'if'
Fixes: 84733fd0d75e ("eal/arm: fix memory barrier definition")
Cc: sta...@dpdk.org
S
move the common part of rte_ring.h into rte_ring_generic.h.
move the memory barrier part into update_tail().
no functional changes here.
Signed-off-by: Jia He
Suggested-by: Jerin Jacob
Suggested-by: Ananyev, Konstantin
---
lib/librte_eventdev/rte_event_ring.h | 6 +-
lib/librte_ring
chives/dev/2017-October/080861.html
Signed-off-by: Jia He
Suggested-by: Jerin Jacob
---
config/common_armv8a_linuxapp | 2 +
lib/librte_ring/Makefile | 3 +-
lib/librte_ring/rte_ring.h | 14 ++-
lib/librte_ring/rte_ring_c11_mem.h | 186 +++
for the code as follows:
if (condition)
rte_smp_rmb();
else
rte_smp_wmb();
Without this patch, compiler will report this error:
error: 'else' without a previous 'if'
Fixes: 84733fd0d75e ("eal/arm64: fix memory barrier definition")
Cc: sta...@dpdk.or
te_smp_rmb() between 2 loads
Jia He (3):
eal/arm64: remove the braces {} for dmb() and dsb()
ring: introduce new header file to include common functions
ring: introduce new header file to support C11 memory model
config/common_armv8a_linuxapp | 2 +
.../common/includ
chives/dev/2017-October/080861.html
Signed-off-by: Jia He
Suggested-by: Jerin Jacob
Acked-by: Jerin Jacob
---
config/common_armv8a_linuxapp | 2 +
lib/librte_ring/Makefile | 3 +-
lib/librte_ring/rte_ring.h | 14 ++-
lib/librte_ring/rte_ring_
move the common part of rte_ring.h into rte_ring_generic.h.
move the memory barrier part into update_tail().
no functional changes here.
Signed-off-by: Jia He
Suggested-by: Jerin Jacob
Suggested-by: Ananyev Konstantin
Acked-by: Jerin Jacob
---
lib/librte_eventdev/rte_event_ring.h | 6
Hi Jerin
In [1], I met a pmu cycle counter problem (all return value is 0)
occasionally.
And then I submited a patch to kernel maillist, but was rejected by
maintainer at last [2].
He said:
"We only intend for the in-kernel perf infrastructure to access
pmccntr_el0; nothing else should to
ution
cycle counter is not
correct if the kernel version is newer than v4.5-rc1-8-gda4e4f1?
Cheers,
Jia
On 12/11/2017 1:59 PM, Jerin Jacob Wrote:
-Original Message-
Date: Mon, 11 Dec 2017 13:38:25 +0800
From: Jia He
To: Jerin Jacob , "dev@dpdk.org"
Subject: About pmu cycle c
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