On Sat, Jan 16, 2021 at 3:39 PM Ruifeng Wang wrote:
> > Subject: [PATCH 1/3] net/hinic: restore vectorised code
> >
> > Following make support removal, the vectorised code is not built anymore,
> > fix the build flag check.
> >
> > Fixes: 3cc6ecfdfe85 ("build: remove makefiles")
> > Cc: sta...@dpd
> -Original Message-
> From: David Marchand
> Sent: Monday, January 18, 2021 4:18 PM
> To: Ruifeng Wang
> Cc: dev@dpdk.org; ferruh.yi...@intel.com; sta...@dpdk.org; Ziyang Xuan
> ; Xiaoyun Wang
> ; Guoyang Zhou
> ; Ciara Power ;
> tho...@monjalon.net; nd
> Subject: Re: [PATCH 1/3] net/h
On Fri, Jan 15, 2021 at 1:15 PM Anatoly Burakov
wrote:
>
> Currently, we don't check anything that comes in through memory hotplug
> subsystem using the IPC, because we always assume the data is correct.
> This is okay as anyone having access to the IPC socket would also have
> rights to crash the
> -Original Message-
> From: dev On Behalf Of Zhang,Alvin
> Sent: Friday, January 15, 2021 4:34 PM
> To: Guo, Jia ; Xie, WeiX
> Cc: dev@dpdk.org; Zhang, AlvinX
> Subject: [dpdk-dev] [PATCH v2] net/i40e: fix out-of-scope variable
>
> From: Alvin Zhang
>
> Using "key", which points t
Allow error to be returned for VIRTCHNL_OP_SET_RSS_HENA when set
hena = 0. Add warning that PF doesnot support hena = 0 now.
Fixes: 95f2f0e9fc2a6("net/iavf: improve default RSS")
Cc: sta...@dpdk.org
Signed-off-by: Xuan Ding
---
drivers/net/iavf/iavf_ethdev.c | 20 +---
1 file ch
On Sat, Jan 16, 2021 at 10:39 AM Igor Russkikh wrote:
>
> When testing high performance numbers, it is often that CPU performance
> limits the max values device can reach (both in pps and in gbps)
>
> Here instead of recreating each packet separately, we use clones counter
> to resend the same mbu
From: Alvin Zhang
For some types of NIC, jumbo frame is not supported in IOV mode,
so if a VF requests to configure the frame size to not bigger
than RTE_ETHER_MAX_LEN, the kernel driver returns 0, but the DPDK
ixgbe PMD returens -1, this will cause the VF to fail to start
when the PF driven by D
Acked-by: Jeff Guo
> -Original Message-
> From: Zhang,Alvin
> Sent: Monday, January 18, 2021 4:35 PM
> To: Guo, Jia ; Xie, WeiX ; Wang,
> Haiyue
> Cc: dev@dpdk.org; Zhang, AlvinX ;
> sta...@dpdk.org
> Subject: [PATCH v6] net/ixgbe: fix configuration of max frame size
>
> From: Alvin Zh
Since DCF always configure the outer VLAN offloads for the target AVF,
so rename the related variables to align with this design.
Also, the DCF needs to trace the AVF reset status to re-apply the VLAN
offload setting, refactor the reset event handling to support this.
Change the VF representor AP
Allow error to be returned for VIRTCHNL_OP_SET_RSS_HENA when set
hena = 0. Add warning that PF does not support hena = 0 now.
Fixes: 95f2f0e9fc2a6("net/iavf: improve default RSS")
Cc: sta...@dpdk.org
Signed-off-by: Xuan Ding
---
v2:
* Modify the commit log to avoid a spelling error.
---
driver
From: Alvin Zhang
Since the patch '1848b117' has set the value of key in 'struct
rte_flow_action_rss' to NULL, the PMD cannot get the RSS key now.
This patch sets offset and size of the key pointer as the first
parameter of the token 'key' and copies the start address of the
'HEX' data to the lo
On 1/6/2021 10:05 AM, Ivan Malov wrote:
A particular FW version is aware of some set of match fields.
Depending on FW configuration and match specification type, a
known field may not necessarily be allowed to have a non-zero
mask. FW communicates such restrictions via field capabilities
MCDI. Ne
Hi Ankur,
> -Original Message-
> From: Ankur Dwivedi
> Sent: Friday, January 8, 2021 2:11 PM
> To: dev@dpdk.org
> Cc: sta...@dpdk.org; Gujjar, Abhinandan S ;
> akhil.go...@nxp.com; ano...@marvell.com; Ankur Dwivedi
>
> Subject: [PATCH] test/event_crypto_adapter: set cipher operation in t
On 1/14/2021 4:18 AM, Zhang, Qi Z wrote:
-Original Message-
From: Guo, Jia
Sent: Wednesday, January 13, 2021 10:05 PM
To: Zhang, Qi Z ; Wu, Jingjing ;
Yang, Qiming ; Wang, Haiyue
Cc: dev@dpdk.org; Guo, Jia ; Su, Simei
Subject: [dpdk-dev v3 0/3] enable UDP ecpri configure in dcf
Ena
add basic PCIe ethdev probe and remove.
Signed-off-by: Nalla Pradeep
---
drivers/common/octeontx2/otx2_common.h| 5 +-
drivers/net/octeontx_ep/meson.build | 13 +
drivers/net/octeontx_ep/otx_ep_common.h | 14 +
drivers/net/octeontx_ep/otx_ep_ethdev.c | 62 +
Functions to setup device, basic IQ and OQ registers are added.
Signed-off-by: Nalla Pradeep
---
drivers/net/octeontx_ep/meson.build | 2 +
drivers/net/octeontx_ep/otx2_ep_vf.c| 138 +
drivers/net/octeontx_ep/otx2_ep_vf.h| 11 ++
drivers/net/octeontx_ep/otx_ep_
Add basic init and uninit function which includes
initializing fields of ethdev private structure.
Signed-off-by: Nalla Pradeep
---
drivers/net/octeontx_ep/otx_ep_common.h | 19 +-
drivers/net/octeontx_ep/otx_ep_ethdev.c | 88 +++--
2 files changed, 101 insertions(+), 6 d
Receive queue setup involves allocating memory for the queue,
initializing data structure representing the queue and filling queue
with receive buffers of rx descriptor count.
Receive queues are referred as droq. Hardware fills the receive buffers
in queue with the packet. It can use same receive
Add device information get and device configure operations.
Signed-off-by: Nalla Pradeep
---
drivers/net/octeontx_ep/otx_ep_common.h | 16 +
drivers/net/octeontx_ep/otx_ep_ethdev.c | 89 -
drivers/net/octeontx_ep/otx_ep_rxtx.h | 10 +++
3 files changed, 112 insertio
Configuring hardware registers with command queue(iq) and droq(oq)
parameters.
Signed-off-by: Nalla Pradeep
---
drivers/net/octeontx_ep/otx2_ep_vf.c| 124
drivers/net/octeontx_ep/otx_ep_common.h | 65 +
drivers/net/octeontx_ep/otx_ep_vf.c | 124 +
Transmit queue setup involves allocating memory for the command queue
considering tx descriptor count and initializing data structure
representing the queue. Transmit queue release function frees the
command queue.
Signed-off-by: Nalla Pradeep
---
drivers/net/octeontx_ep/otx_ep_common.h | 89 ++
Adding bare minimum PMD library and doc build infrastructure
and claim the maintainership for octeontx end point PMD.
Signed-off-by: Nalla Pradeep
---
MAINTAINERS | 9 +++
doc/guides/nics/features/octeontx_ep.ini | 8 ++
doc/guides/nics/index.rst
Function to deliver packets from DROQ to application is added. It also
fills DROQ with receive buffers timely such that device can fill them
with incoming packets.
Signed-off-by: Nalla Pradeep
---
drivers/net/octeontx_ep/otx_ep_common.h | 3 +
drivers/net/octeontx_ep/otx_ep_ethdev.c | 3 +
d
1. Packet transmit function for both otx and otx2 are added.
2. Flushing transmit(command) queue when pending commands are more than
maximum allowed value (currently 16).
3. Scatter gather support if the packet spans multiple buffers.
Signed-off-by: Nalla Pradeep
---
drivers/net/octeontx_ep/o
Dev start and stop operations are added. To accomplish this internal
functions to enable or disable io queues are incorporated.
Signed-off-by: Nalla Pradeep
---
drivers/net/octeontx_ep/otx2_ep_vf.c| 107
drivers/net/octeontx_ep/otx_ep_common.h | 11 ++
drivers/net/octeo
18/01/2021 05:01, Zhang, Qi Z:
> From: Thomas Monjalon
> > 12/01/2021 12:47, Qi Zhang:
> > > + * This API is for the first case and typically it will only be
> > > + implemented
> > > + * on a PF driver or a VF driver which have privilege right to
> > > + configure for
> >
> > What is a privilege
On 1/15/2021 11:03 AM, Jiawen Wu wrote:
Add txgbe PMD new features in release notes,
update user guide in txgbe.rst for flow API and traffic manager.
Signed-off-by: Jiawen Wu
Thanks for the update.
Reviewed-by: Ferruh Yigit
Applied to dpdk-next-net/main, thanks.
Hi,
The 'speed_capa' will be reported in rte_eth_dev_info_get API. How
should users use the field?
1) The driver reports only the capabilities supported by the NIC, and
users only obtain the capabilities.
Maybe, there is a case that a rate bit in 'speed_capa' is not supported
by the current
On 1/15/2021 10:44 AM, oulijun wrote:
Hi Steve
This is a very good job! But I have some question and suggestions.
Please check it.
在 2021/1/14 17:45, Steve Yang 写道:
Ethdev is using default Ethernet overhead to decide if provided
'max_rx_pkt_len' value is bigger than max (non jumbo) MTU value,
a
From: Liron Himi
pf-func is 16bit but the current reserved location
used in tx action is 8bits. moved it to bits 63-48.
Fixes: 32e6aaa97 ("net/octeontx2: support flow parse actions")
Cc: sta...@dpdk.org
Signed-off-by: Liron Himi
Reviewed-by: Kiran Kumar Kokkilagadda
---
drivers/net/octeontx2
On Fri, Jan 15, 2021 at 06:40:56PM +, Ferruh Yigit wrote:
> On 12/21/2020 2:04 PM, Bruce Richardson wrote:
> > On Mon, Dec 21, 2020 at 12:19:17PM +, Hemant Agrawal wrote:
> > > Hi,
> > > I am trying to cross compile DPDK for arm64 on a ubuntu
> > > machine, which has a zli
To support more representor type, this patch introduces representor type
enum. The enum is subject to extend for new types upcoming.
Signed-off-by: Xueming Li
Acked-by: Viacheslav Ovsiienko
---
drivers/net/bnxt/bnxt_ethdev.c| 7 +++
drivers/net/enic/enic_ethdev.c| 7 ++
To support extended representor syntax, this patch extends the
representor list parsing to support for representor port range in
devargs, examples:
representor=[1,2,3] - single list
representor=[1,3-5,7,9-11] - list with singles and ranges
Signed-off-by: Xueming Li
Acked-by: Viache
With Kernel bonding, multiple underlying PFs are bonded, VFs come
from different PF, need to identify representor of VFs unambiguously by
adding PF index.
This patch introduces optional 'pf' section to representor devargs
syntax, examples:
representor=pf0vf0 - single VF representor
r
This patch updates kvargs parser to support lists on top of range, allow
multiple lists or range:
k1=a[1,2]b[3-5]
Signed-off-by: Xueming Li
Acked-by: Viacheslav Ovsiienko
---
app/test/test_kvargs.c | 46 +--
lib/librte_kvargs/rte_kvargs.c | 101 +++
SubFunction [1] is a portion of the PCI device, a SF netdev has its own
dedicated queues(txq, rxq). A SF netdev supports E-Switch representation
offload similar to existing PF and VF representors. A SF shares PCI
level resources with other SFs and/or with its parent PCI function.
>From SmartNIC pe
The NIC can have multiple PCIe links and can be attached to multiple
hosts, for example the same single NIC can be shared for multiple server
units in the rack. On each PCIe link NIC can provide multiple PFs and
VFs/SFs based on these ones. The full representor identifier consists of
three indices
Old DPDK version or some drivers that don't support SubFunction
representor. For application to adapt different DPDK version
automatically, or to be used for different NICs, this patch introduces
new eth device capability of supporting SubFunction representor device.
Signed-off-by: Xueming Li
Ack
To prepare for more representor types, this patch adds compatible VF
representor devargs syntax:
vf#: new VF port representor/s, examples:
representor=vf2 - single representor
representor=vf[1,3,5]- single list
representor=vf[0-3] - single range
representor=vf[0,1,4-7] - lis
The NIC can have multiple PCIe links and can be attached to the multiple
hosts, for example the same single NIC can be shared for multiple server
units in the rack. On each PCIe link NIC can provide multiple PFs and
VFs/SFs based on these ones. To provide the unambiguous identification
of the PCIe
SubFunction is a portion of the PCI device, created on demand, a SF
netdev has its own dedicated queues(txq, rxq). A SF netdev supports
eswitch representation offload similar to existing PF and VF
representors.
To support SF representor, this patch introduces new devargs syntax,
examples:
represe
On 1/18/2021 10:27 AM, oulijun wrote:
Hi,
The 'speed_capa' will be reported in rte_eth_dev_info_get API. How should users
use the field?
1) The driver reports only the capabilities supported by the NIC, and users only
obtain the capabilities.
Maybe, there is a case that a rate bit in 'speed
SubFunction [1] is a portion of the PCI device, a SF netdev has its own
dedicated queues(txq, rxq). A SF netdev supports E-Switch representation
offload similar to existing PF and VF representors. A SF shares PCI
level resources with other SFs and/or with its parent PCI function.
This patch set in
To probe representor on 2nd PF of kernel bonding device, had to specify
PF1 BDF in devarg:
,representor=0
When closing bonding device, all representors had to be closed together
and this implies all representors have to use primary PF of bonding
device. So after probing representor port on 2nd PF
In case of kernel bonding device, counter was read from first bonding PF
member.
This patch reads all member PFs and sums to get bond xstats.
Signed-off-by: Xueming Li
Acked-by: Viacheslav Ovsiienko
---
drivers/net/mlx5/linux/mlx5_ethdev_os.c | 127 +++-
1 file changed, 102
With kernel bonding, representors on second PF are being probed by
devargs:
,representor=pf1vf
No need to save primary PF port ID and lookup when probing sibling
ports, revert patch [1]
[1]:
commit e6818853c022 ("net/mlx5: set representor to first PF in bonding
mode")
Signed-off-by: Xuemi
Since kernel bonding interface doesn't provide counter summary of member
ports, PMD has to aggregate couters from of member ports.
This patch collect bonding member information and save to shared context
data.
Signed-off-by: Xueming Li
Acked-by: Viacheslav Ovsiienko
---
drivers/net/mlx5/mlx5.h
With kernel bonding, there was an error when setting VF MAC address
through representor. The Netlink api requires ifindex of owner PF, not
bonding device ifindex.
Uses owner PF ifindex to modify VF default MAC in case of bonding
device.
Fixes: c21e5facf7d2 ("net/mlx5: use bond index for netdev op
This patch adds support for SF representor. Similar to VF representor,
switch port name of SF representor in phys_port_name sysfs key is
"pfsf".
Device representor argumnt is "representors=sf[list]", list member could
be mix of instance and range. Example:
representors=sf[0,2,4,8-12,-1]
To prob
To probe representors from different kernel bonding PFs, had to specify
2 separate devargs like this:
-a 03:00.0,representor=pf0vf[0-3] -a 03:00.0,representor=pf1vf[0-3]
This patch supports range or list of PF section in devargs, so the
alternative short devargs of above is:
-a 03:00.0,rep
Since kernel bonding netdev doesn't provide statistics counter that
reflects all member ports, PMD has to manually summarize counters from
each member ports.
As a preparation, this patch collects bonding member port information
and saves to shared context data.
Signed-off-by: Xueming Li
Acked-by
This patch updates representor name parsing for SF.
In sysfs, representor name stored under "phys_port_name" sysfs key,
similar to VF representor, switch port name of SF representor is
"pfsf".
For netlink message, net SF type is supported.
Examples:
pf0sf1
pf0sf[0-3]
Signed-off-by: Xueming Li
Hi Abhinandan,
>-Original Message-
>From: Gujjar, Abhinandan S
>Sent: Monday, January 18, 2021 2:42 PM
>To: Ankur Dwivedi ; dev@dpdk.org
>Cc: sta...@dpdk.org; akhil.go...@nxp.com; Anoob Joseph
>
>Subject: [EXT] RE: [PATCH] test/event_crypto_adapter: set cipher operation in
>transform
>
>E
Fixes some spelling errors in app logs and help text.
Fixes: 7da018731c56 ("app/crypto-perf: add help option")
Fixes: f8be1786b1b8 ("app/crypto-perf: introduce performance test application")
Cc: pablo.de.lara.gua...@intel.com
Cc: slawomirx.mrozow...@intel.com
Cc: sta...@dpdk.org
Signed-off-by: Ci
On 18-Jan-21 8:26 AM, David Marchand wrote:
On Fri, Jan 15, 2021 at 1:15 PM Anatoly Burakov
wrote:
Currently, we don't check anything that comes in through memory hotplug
subsystem using the IPC, because we always assume the data is correct.
This is okay as anyone having access to the IPC sock
@Stephen Hemminger
Xiaoyun proposed a solution which may match your idea, but there are some
concerns:
1. a global variable for original terminal setting has to be defined.
2. in each app which uses cmdline, a function has to be registered with
atexit() in prompt() to restore original ter
Since DCF always configure the outer VLAN offloads for the target AVF,
so rename the related variables to align with this design.
Also, the DCF needs to trace the AVF reset status to re-apply the VLAN
offload setting, refactor the reset event handling to support this.
Change the VF representor AP
On 1/18/2021 7:04 AM, Steve Yang wrote:
The jumbo frame used the 'RTE_ETHER_MAX_LEN' as boundary condition, this
fix will change the boundary condition with 'RTE_ETHER_MTU' and overhead.
When the MTU(1500) set, the frame type of rx packet will be different
if used different overhead, it will cau
On 1/18/2021 10:51 AM, Bruce Richardson wrote:
On Fri, Jan 15, 2021 at 06:40:56PM +, Ferruh Yigit wrote:
On 12/21/2020 2:04 PM, Bruce Richardson wrote:
On Mon, Dec 21, 2020 at 12:19:17PM +, Hemant Agrawal wrote:
Hi,
I am trying to cross compile DPDK for arm64 on a ubu
On 1/18/2021 11:58 AM, Ferruh Yigit wrote:
On 1/18/2021 10:51 AM, Bruce Richardson wrote:
On Fri, Jan 15, 2021 at 06:40:56PM +, Ferruh Yigit wrote:
On 12/21/2020 2:04 PM, Bruce Richardson wrote:
On Mon, Dec 21, 2020 at 12:19:17PM +, Hemant Agrawal wrote:
Hi,
I am try
Hi Ankur,
> -Original Message-
> From: Ankur Dwivedi
> Sent: Monday, January 18, 2021 5:04 PM
> To: Gujjar, Abhinandan S ; dev@dpdk.org
> Cc: sta...@dpdk.org; akhil.go...@nxp.com; Anoob Joseph
>
> Subject: RE: [PATCH] test/event_crypto_adapter: set cipher operation in
> transform
>
> Hi
On 1/18/2021 12:05 PM, Ferruh Yigit wrote:
On 1/18/2021 11:58 AM, Ferruh Yigit wrote:
On 1/18/2021 10:51 AM, Bruce Richardson wrote:
On Fri, Jan 15, 2021 at 06:40:56PM +, Ferruh Yigit wrote:
On 12/21/2020 2:04 PM, Bruce Richardson wrote:
On Mon, Dec 21, 2020 at 12:19:17PM +, Hemant Ag
Hi Anatoly,
On 14/1/2021 2:46 PM, Anatoly Burakov wrote:
From: Liang Ma
Add a simple on/off switch that will enable saving power when no
packets are arriving. It is based on counting the number of empty
polls and, when the number reaches a certain threshold, entering an
architecture-defined op
Hi Anatoly,
On 14/1/2021 2:46 PM, Anatoly Burakov wrote:
From: Liang Ma
Add PMD power management feature support to l3fwd-power sample app.
Signed-off-by: Liang Ma
Signed-off-by: Anatoly Burakov
---
Notes:
v12:
- Allow selecting PMD power management scheme from command-line
On Mon, Jan 18, 2021 at 11:58:40AM +, Ferruh Yigit wrote:
> On 1/18/2021 10:51 AM, Bruce Richardson wrote:
> > On Fri, Jan 15, 2021 at 06:40:56PM +, Ferruh Yigit wrote:
> > > On 12/21/2020 2:04 PM, Bruce Richardson wrote:
> > > > On Mon, Dec 21, 2020 at 12:19:17PM +, Hemant Agrawal wrot
Stephen Hemminger writes:
> On Sun, 17 Jan 2021 18:57:56 +0100
> Thomas Monjalon wrote:
>
>> 14/01/2021 17:58, Stephen Hemminger:
>> > The ticketlock test is fast and should be run all the time.
>>
>> I think it was not added because it includes a perf test.
>> Cc'ing more people for comments
On Mon, Jan 18, 2021 at 12:16:04PM +, Ferruh Yigit wrote:
> On 1/18/2021 12:05 PM, Ferruh Yigit wrote:
> > On 1/18/2021 11:58 AM, Ferruh Yigit wrote:
> > > On 1/18/2021 10:51 AM, Bruce Richardson wrote:
> > > > On Fri, Jan 15, 2021 at 06:40:56PM +, Ferruh Yigit wrote:
> > > > > On 12/21/202
15/01/2021 14:26, Juraj Linkeš:
> A few options that disabled drivers in the old makefiles were improperly
> ported to the meson build system. Fix this by adding a to the list of
"by adding a" what?
> disabled drivers, similarly how the command line option works and remove
> unneeded driver optio
15/01/2021 14:26, Juraj Linkeš:
> Add Arm SoC configuration to Arm meson.build and add a meson option to
> enable those options for native builds. This is preferable to
> specifying a cross file when doing aarch64 -> aarch64 builds, since the
> cross file specifies the toolchain as well.
>
> Signe
This patch should squashed into commit ea6ecf3f to fix
the build error on windows.
Fixes: ea6ecf3f21b0 ("net/i40e: add AVX512 vector path")
Signed-off-by: Leyi Rong
---
drivers/net/i40e/i40e_rxtx_vec_avx512.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/i40e/i
15/01/2021 14:26, Juraj Linkeš:
> Fix the implementer and part number of DPAA and ARMADA SoCs.
> The current values of 16 cores and 1 NUMA node don't cover all SoCs from
> the Arm implementer, e.g. Taishan 2280 has 64 cores and 4 NUMA nodes.
> Increase these to 64 and 4 to widen the coverage.
> Add
> -Original Message-
> From: Odi Assli
> Sent: Sunday, January 17, 2021 7:26 PM
> To: Zhang, Qi Z ; Rong, Leyi ; Lu,
> Wenzhuo ; Yigit, Ferruh ;
> Richardson, Bruce ; Xing, Beilei
> ; Kadam, Pallavi ; Menon,
> Ranjit
> Cc: dev@dpdk.org; Tal Shnaiderman ; NBU-Contact-
> Thomas Monjalon ;
Reviewed-by: Liron Himi
-Original Message-
From: Thomas Monjalon
Sent: Monday, 18 January 2021 15:45
To: Juraj Linkeš
Cc: bruce.richard...@intel.com; ruifeng.w...@arm.com;
honnappa.nagaraha...@arm.com; phil.y...@arm.com; vcchu...@amazon.com;
dharmik.thak...@arm.com; jerinjac...@gmail
> >When querying the link status via telemetry interface, we don't want the
> >client to have to wait for multiple seconds for a reply. Therefore use
> >"rte_eth_link_get_nowait()" rather than "rte_eth_link_get()" in the telemetry
> >callback.
> >
> >Cc: sta...@dpdk.org
> >Fixes: c190daedb9b1 ("eth
On 1/18/2021 1:58 PM, Rong, Leyi wrote:
-Original Message-
From: Odi Assli
Sent: Sunday, January 17, 2021 7:26 PM
To: Zhang, Qi Z ; Rong, Leyi ; Lu,
Wenzhuo ; Yigit, Ferruh ;
Richardson, Bruce ; Xing, Beilei
; Kadam, Pallavi ; Menon,
Ranjit
Cc: dev@dpdk.org; Tal Shnaiderman ; NBU-Cont
On 1/17/2021 10:21 AM, Shiri Kuzin wrote:
The Geneve tunneling protocol is designed to allow the
user to specify some data context on the packet.
The GENEVE TLV (Type-Length-Variable) Option
is the mean intended to present the user data.
In order to support GENEVE TLV Option the new rte_flow
ite
On 1/17/2021 10:21 AM, Shiri Kuzin wrote:
The Geneve tunneling protocol is designed to allow the user to specify
some data context on the packet.
The GENEVE TLV (Type-Length-Variable) Option is the mean intended to
present the user data.
In order to support GENEVE TLV Option the new rte_flow ite
Meson can use cmake as a fallback for detecting packages, and this can
lead to picking up 64-libs for 32-bit builds. To work around this, force
the use of pkg-config only for detecting libcrypto, zlib, jansson and
other package dependencies.
CC: sta...@dpdk.org
Signed-off-by: Bruce Richardson
--
On 1/17/2021 10:21 AM, Shiri Kuzin wrote:
The Geneve tunneling protocol is designed to allow the user to specify
some data context on the packet.
The GENEVE TLV (Type-Length-Variable) Option is the mean intended to
present the user data.
In order to support GENEVE TLV Option the new rte_flow ite
On 1/15/2021 1:40 PM, David Marchand wrote:
Some fixes following make support removal.
The first patch is a real fix.
The other two are cleanups so I did not mark them for backport.
Series applied to dpdk-next-net/main, thanks.
On 1/18/2021 2:02 PM, Thomas Monjalon wrote:
When querying the link status via telemetry interface, we don't want the
client to have to wait for multiple seconds for a reply. Therefore use
"rte_eth_link_get_nowait()" rather than "rte_eth_link_get()" in the telemetry
callback.
Cc: sta...@dpdk.org
Hi Declan, Akhil
We are going to implement mlx5 crypto PMD to support AES-XTS de\encrypt
operations.
The algorithm defines block size >= 16Bytes (it is called also data-unit)which
should be known for encryption\decryptions.
I didn't find this parameterin the cypher xform.
How do you sugge
> Subject: Re: [PATCH v3 0/3] AVX512 vPMD on i40e
>
> External email: Use caution opening links or attachments
>
>
> On 1/18/2021 1:58 PM, Rong, Leyi wrote:
> >
> >> -Original Message-
> >> From: Odi Assli
> >> Sent: Sunday, January 17, 2021 7:26 PM
> >> To: Zhang, Qi Z ; Rong, Leyi
> >
Hi Abhinandan,
>-Original Message-
>From: Gujjar, Abhinandan S
>Sent: Monday, January 18, 2021 5:41 PM
>To: Ankur Dwivedi ; dev@dpdk.org
>Cc: sta...@dpdk.org; akhil.go...@nxp.com; Anoob Joseph
>
>Subject: [EXT] RE: [PATCH] test/event_crypto_adapter: set cipher operation in
>transform
>
>E
>-Original Message-
>From: dev On Behalf Of Juraj Linkeš
>Sent: Friday, January 15, 2021 6:56 PM
>To: bruce.richard...@intel.com; ruifeng.w...@arm.com;
>honnappa.nagaraha...@arm.com; phil.y...@arm.com;
>vcchu...@amazon.com; dharmik.thak...@arm.com;
>jerinjac...@gmail.com; hemant.agra...@
On 1/7/2021 2:01 PM, Hyong Youb Kim wrote:
Latest VIC adapters support 64B CQ (completion queue) entries as well
as 16B entries available on all VIC models. 64B entries can greatly
reduce cache contention (CPU stall cycles) between DMA writes (Rx
packet descriptors) and polling CPU. The effect is
> -Original Message-
> From: dev On Behalf Of Matan Azrad
> Sent: Wednesday, January 13, 2021 18:18
> To: dev@dpdk.org
> Cc: NBU-Contact-Thomas Monjalon ; Ashish Gupta
> ; Fiona Trahe ;
> akhil.go...@nxp.com
> Subject: [dpdk-dev] [PATCH v2 01/10] common/mlx5: add DevX attributes for
> comp
This patch fixes memory leak in parsing error handling.
Fixes: 338327d731e6 ("devargs: add function to parse device layers")
Cc: gaetan.ri...@6wind.com
Cc: sta...@dpdk.org
Signed-off-by: Xueming Li
---
lib/librte_eal/common/eal_common_devargs.c | 8 +++-
1 file changed, 7 insertions(+), 1 d
To use Global Device Syntax as devarg, name is required for device
management.
This patch adds global device syntax name resolving by using same
strategy as function rte_eth_iterator_init(), parses from "addr" bus
parameter for PCI bus, from "name" bus parameter for vdev bus.
Example:
-a bus=pci,
In current design, legacy parser rte_devargs_parse() saved scratch
buffer to devargs.args while new parser rte_devargs_layers_parse() saved
to devargs.data. Code using devargs had to know the difference and
cleaned up memory accordingly - error prone.
This patch unifies data the dedicate scratch b
Adds a new function to get value of a specific key from kvargs list.
Signed-off-by: Xueming Li
---
lib/librte_kvargs/rte_kvargs.c | 20
lib/librte_kvargs/rte_kvargs.h | 14 ++
lib/librte_kvargs/version.map | 1 +
3 files changed, 35 insertions(+)
diff --git a/
When parsing a device argument, try to parse new global device syntax
firstly, fallback to legacy syntax parsing on error.
Example of new global device syntax:
-a bus=pci,addr=82:00.0/class=eth/driver=mlx5,dv_flow_en=1
Signed-off-by: Xueming Li
---
lib/librte_eal/common/eal_common_devargs.c |
The new Global Device Syntax [1] is used to identify a device with full
bus, class and driver description, example:
-a bus=pci,addr=82:00.0/class=eth/driver=mlx5,...
This patchset enables global device syntax with backward compatibility
by:
- unify devargs memory cleanup
- parse name from bus par
On 1/12/2021 5:28 AM, asoma...@amd.com wrote:
From: Amaranath Somalapuram
Adding API for get_module_eeprom and get_module_info.
Signed-off-by: Amaranath Somalapuram
---
doc/guides/nics/features/axgbe.ini | 1 +
drivers/net/axgbe/axgbe_ethdev.c | 2 +
drivers/net/axgbe/axgbe_phy.h
On 1/7/2021 8:42 PM, George Prekas wrote:
Strict-aliasing rules are violated by cast to uint16_t* in flowgen.c and
the calculated IP checksum is wrong. Use attribute __may_alias__ to fix
the problem.
Signed-off-by: George Prekas
Fixes: e9e23a617eb8 ("app/testpmd: add flowgen forwarding en
On Thu, Jan 14, 2021 at 3:46 PM Anatoly Burakov
wrote:
>
> This patchset proposes a simple API for Ethernet drivers to cause the
> CPU to enter a power-optimized state while waiting for packets to
> arrive. There are multiple proposed mechanisms to achieve said power
> savings: simple frequency sc
This patch supports new device global device syntax, resolve class type
from "class" section if the devarg is global device syntax:
bus=,k=v,,,/class=,k=v,,,/driver=,k=v
To reuse class name of global device syntax, this patch also changes
internal class name introduced by commit [1] to algin w
New Global device syntax [1] is used to identify a device with full bus,
class and driver description, for example:
-a bus=pci,id=82:00.0/class=eth/driver=mlx5,dv_flow_en=1
This patchset enables global syntax in mlx5 PMD.
Depends-on: series-14815 ("eal: support global device syntax")
History:
V
This patch support new global device syntax like:
bus=pci,addr=BB:DD.F/class=eth/driver=mlx5,devargs,..
In driver parameters check, ignores "driver" key which is part of new
global device syntax instead of reporting error.
Signed-off-by: Xueming Li
---
drivers/net/mlx5/mlx5.c | 6 +-
Hi Matan,
Block size is specified in the capability structure and is expected to be same
for a particular algorithm.
And for AES-XTS it is 16 bytes only if I am not wrong.
As per my understanding, data unit is different from block size.
Data unit is the input data which may or may not be multipl
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