Hi Stephen,
Agreed that the current code does not directly support hotplug.
Now I am looking for a hint regarding how best the DPDK application can find
out that the PCI device on which it was doing the I/O has been removed from
underneath. In that case the application can call the ethdev stop
Hi,
I am a beginner with dpdk and trying to follow the instructions in
http://www.dpdk.org/doc/quick-start
I am seeing the following error when doing make with 1.5.0r2 or 1.5.1r1
== Build lib/librte_meter
== Build lib/librte_sched
CC rte_sched.o
In file included from
/home/surya/dpdk/dpdk-1.
Changing the CPU type emulation to some model that supports SSSE3 solved
it (e.g. core2duo) should do the trick. I faced the same problem
sometime ago.
best
marc
On 29/11/13 11:39, Surya Nimmagadda wrote:
> Hi,
>
> I am a beginner with dpdk and trying to follow the instructions in
> http://www
Hmm, that's strange. I don't know how to interpret my observations then.
I have access to two platforms, one is based on Intel(R) Xeon(R) CPU
E3-1230 V2 @ 3.30GHz and another on Intel(R) Xeon(R) CPU E3-1270 v3 @
3.50GHz. Both running ubuntu-12.04 server. I see repeating errors on NIC
initialisa
29/11/2013 14:53, Dmitry Vyal :
> On 11/28/2013 03:01 PM, Richardson, Bruce wrote:
> >> It's probably due to a frequency scaling.
> >> The timer based is initialized when DPDK initialize and the CPU can
> >> change
> >> its frequency, breaking next timers.
> >>
> >> The fix is to control the CPU f
Hi Surya,
SSE3 instructions are not enabled by default.
To enable, you can either tell gcc your CPU architecture (-march=) as
suggested
by Marc, or enable just the specific SSE version that's supported by your
CPU (e.g.,
make TOOLCHAIN_CFLAGS="-msse4")
See http://gcc.gnu.org/onlinedocs/gcc/i386-
29/11/2013 13:25, Thomas Monjalon :
> 29/11/2013 14:53, Dmitry Vyal :
> > On 11/28/2013 03:01 PM, Richardson, Bruce wrote:
> > > [BR] Frequency changes should not affect timers for modern Intel CPUs.
> > > Please see the " Intel(r) 64 and IA-32 Architectures Software
> > > Developer's
> > > Manual"
Thomas29/11/2013 13:25, Monjalon :
> 29/11/2013 14:53, Dmitry Vyal :
> > On 11/28/2013 03:01 PM, Richardson, Bruce wrote:
> > > [BR] Frequency changes should not affect timers for modern Intel CPUs.
> >
> > The error frequency greatly reduces if I patch
> > loop limit as I described earlier or if
Hi Ariel, some comments inlined below. Regards, Cristian
-Original Message-
From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Ariel Rodriguez
Sent: Thursday, November 28, 2013 8:53 PM
To: dev at dpdk.org
Subject: [dpdk-dev] 4 Traffic classes per Pipe limitation
Hi, im working
Thanks for the answer, your explanation was perfect. Unfortunally
, the client requirements are those, we need at traffic control level
around 64 traffic metering controlers (traffic classes) at subscriber level.
Each subscriber have a global plan rate (each pipe have the same
to
On Fri, 29 Nov 2013 17:50:34 -0200
Ariel Rodriguez wrote:
> Thanks for the answer, your explanation was perfect. Unfortunally
> , the client requirements are those, we need at traffic control level
> around 64 traffic metering controlers (traffic classes) at subscriber level.
I think yo
Ok thats give the reason i need, yes i could change the number of bits
of ,for example , pipe size which is 20 bytes but we need around a million
of pipe (the telecom has a million of concurent subscribers). Thank you so
much, i have to think about this, for the moment i believe we will use th
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