[dpdk-dev] Sporadic errors while initializing NICs in example applications, dpdk-1.5.0r1

[Thomas Monjalon]

29/11/2013 13:25, Thomas Monjalon :
> 29/11/2013 14:53, Dmitry Vyal :
> > On 11/28/2013 03:01 PM, Richardson, Bruce wrote:
> > > [BR] Frequency changes should not affect timers for modern Intel CPUs.
> > > Please see the " Intel(r) 64 and IA-32 Architectures Software
> > > Developer's
> > > Manual" Volume 3
> > > (http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-> 
> > > > > i
> > > a-32-architectures-software-developer-system-programming-manual-325384.p
> > > df
> > > ) , Section 17.13 for more details on this.
> > 
> > Hmm, that's strange. I don't know how to interpret my observations then.
> > I have access to two platforms, one is based on Intel(R) Xeon(R) CPU
> > E3-1230 V2 @ 3.30GHz and another on Intel(R) Xeon(R) CPU E3-1270 v3 @
> > 3.50GHz. Both running ubuntu-12.04 server. I see repeating errors on NIC
> > initialisation phase. The error frequency greatly reduces if I patch
> > loop limit as I described earlier or if I call rte_power_init and
> > rte_power_freq_max as Thomas suggested.
> > 
> > But the only way to get rid of them completely is to set performance
> > governor.
> 
> Please check that your hardware do not support invariant TSC.
> It would explain why you need to fix frequency.
> 
> I attach a simple code to test CPU feature "Invariant TSC".

It seems that the file is stripped on the mailing-list.
Code inlined:

#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <stdint.h>


int main()
{
    uint32_t a = 0x80000000;
    uint32_t b, d;

    __asm__("cpuid;"
            :"=a"(b)
            :"0"(a));

    if (b >= 0x80000007) {

        a = 0x80000007;
        __asm__("cpuid;"
                :"=a"(b), "=d"(d)
                :"0"(a));

        if (d & (1<<8)) {
            printf("Invariant TSC is supported\n");
        } else{
            printf("Invariant TSC is NOT supported\n");
        }
    } else {
        printf("No support for Advanced Power Management Information in 
CPUID\n");
    }
    return 0;
}