Hi,
The testpmd maintainers should also take a look.
> -Original Message-
> From: Alexander Kozyrev
> Sent: Tuesday, August 19, 2025 10:45 PM
> To: dev@dpdk.org
> Cc: sta...@dpdk.org; Raslan Darawsheh ; Bing Zhao
> ; Ori Kam
> Subject: [PATCH] app/testpmd: use
Hi,
@Stephen Hemminger, we don't know other NICs behavior. If all NICs behave the
same, maybe the limitation can be considered to move to the common part.
> -Original Message-
> From: Dariusz Sosnowski
> Sent: Friday, July 18, 2025 7:52 PM
> To: Slava Ovsiienko ; Bing
he
memory and MR are allocated successfully before creating a SQ / CQ.
So the error is not critical and a warning message is enough, the
saved length can be used to create the queue.
Fixes: d94177339289 ("net/mlx5: use consecutive memory for Tx queue creation")
Signed-off-by: Bing
mlx5_txq_release() before continue will recover the
reference count to the initial state and solve the leak.
Fixes: 6f356d3840e6 ("net/mlx5: pass DevX object info in Tx queue start")
Signed-off-by: Bing Zhao
Acked-by: Viacheslav Ovsiienko
---
drivers/net/mlx5/mlx5_trigger.c | 6
. reorganize the code with different commits order.
v4:
1. fix building failure on Windows and OSes with different compilers
2. update the rst
3. addressing comments and fix bugs
v5:
1. solve one size_t coverity warning
---
Bing Zhao (5):
net/mlx5: add new devarg for Tx queue consecutive memory
/ CQ objects, if it is in consecutive mode,
the umem and MR should not be released and the global resources
should only be released when stopping the device.
Signed-off-by: Bing Zhao
---
drivers/common/mlx5/mlx5_common_devx.c | 160 +
drivers/common/mlx5
If the unique umem and MR method is enabled, before starting Tx
queues in device start stage, the memory will be pre-allocated
and the MR will be registered for the Tx queues' usage later.
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5.h | 4 ++
drivers/net/mlx5/mlx5_trigger.c
trunks.
In the testing, such assignment will help to improve the performance
a little bit. All the doorbells will be grouped and padded at the end
of the umem area.
The umem object and offsets information are passed to the Devx
creation function for the further usage.
Signed-off-by: Bing Zhao
When the alignment is non-zero, it means that the single umem and MR
allocation for all Tx queues will be used.
In this commit, the total length of SQs and associated CQs will be
calculated and saved.
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5.h | 4 +++
drivers/net/mlx5/mlx5_tx.h
for more details.
Signed-off-by: Bing Zhao
---
doc/guides/nics/mlx5.rst | 25 +
drivers/net/mlx5/mlx5.c | 36
drivers/net/mlx5/mlx5.h | 7 ---
3 files changed, 65 insertions(+), 3 deletions(-)
diff --git a/doc/guides/nics/mlx5.r
trunks.
In the testing, such assignment will help to improve the performance
a little bit. All the doorbells will be grouped and padded at the end
of the umem area.
The umem object and offsets information are passed to the Devx
creation function for the further usage.
Signed-off-by: Bing Zhao
/ CQ objects, if it is in consecutive mode,
the umem and MR should not be released and the global resources
should only be released when stopping the device.
Signed-off-by: Bing Zhao
---
drivers/common/mlx5/mlx5_common_devx.c | 160 +
drivers/common/mlx5
If the unique umem and MR method is enabled, before starting Tx
queues in device start stage, the memory will be pre-allocated
and the MR will be registered for the Tx queues' usage later.
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5.h | 4 ++
drivers/net/mlx5/mlx5_trigger.c
When the alignment is non-zero, it means that the single umem and MR
allocation for all Tx queues will be used.
In this commit, the total length of SQs and associated CQs will be
calculated and saved.
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5.h | 4 +++
drivers/net/mlx5/mlx5_tx.h
for more details.
Signed-off-by: Bing Zhao
---
doc/guides/nics/mlx5.rst | 25 +
drivers/net/mlx5/mlx5.c | 36
drivers/net/mlx5/mlx5.h | 7 ---
3 files changed, 65 insertions(+), 3 deletions(-)
diff --git a/doc/guides/nics/mlx5.r
. reorganize the code with different commits order.
v4:
1. fix building failure on Windows and OSes with different compilers
2. update the rst
3. addressing comments and fix bugs
---
Bing Zhao (5):
net/mlx5: add new devarg for Tx queue consecutive memory
net/mlx5: calculate the memory length for
trunks.
In the testing, such assignment will help to improve the performance
a little bit. All the doorbells will be grouped and padded at the end
of the umem area.
The umem object and offsets information are passed to the Devx
creation function for the further usage.
Signed-off-by: Bing Zhao
/ CQ objects, if it is in consecutive mode,
the umem and MR should not be released and the global resources
should only be released when stopping the device.
Signed-off-by: Bing Zhao
---
drivers/common/mlx5/mlx5_common_devx.c | 160 +
drivers/common/mlx5
If the unique umem and MR method is enabled, before starting Tx
queues in device start stage, the memory will be pre-allocated
and the MR will be registered for the Tx queues' usage later.
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5.h | 4 ++
drivers/net/mlx5/mlx5_trigger.c
When setting to 0, the legacy way of per queue umem allocation will
be selected in the following commit.
If the value is smaller than the system page size, the starting
address alignment will be rounded up to the page size.
The value is a logarithm value based to 2.
Signed-off-by: Bing Zhao
---
When the alignment is non-zero, it means that the single umem and MR
allocation for all Tx queues will be used.
In this commit, the total length of SQs and associated CQs will be
calculated and saved.
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5.h | 4 +++
drivers/net/mlx5/mlx5_tx.h
. reorganize the code with different commits order.
---
Bing Zhao (5):
net/mlx5: add new devarg for Tx queue consecutive memory
net/mlx5: calculate the memory length for all Tx queues
net/mlx5: allocate and release unique resources for Tx queues
net/mlx5: pass the information in Tx queue start
and that is incorrect.
Adjusting the WQE size will solve the wrong calculation when the
calculated WQE size is less than 64B.
Fixes: 38b4b397a57d ("net/mlx5: add Tx configuration and setup")
Cc: viachesl...@nvidia.com
Cc: sta...@dpdk.org
Signed-off-by: Bing Zhao
Acked-by: Viacheslav
. WDYT?
From: Stephen Hemminger
Sent: Tuesday, June 24, 2025 8:02 PM
To: Bing Zhao
Cc: Slava Ovsiienko ; Matan Azrad ;
dev ; NBU-Contact-Thomas Monjalon (EXTERNAL)
; Dariusz Sosnowski ; Suanming Mou
; Raslan Darawsheh
Subject: Re: [PATCH v2 2/3] net/mlx5: add new devarg for Tx queue consecutive
This patchset will move all the mlx5 Tx queues memory to a
consecutive memory area. All the WQEBBs will be allocated based
on the offset of this memory area.
Bing Zhao (2):
net/mlx5: add new devarg for Tx queue consecutive memory
net/mlx5: use consecutive memory for all Tx queues
drivers
With this commit, a new device argument is introduced to control
the memory allocation for Tx queues.
By default, 'txq_consec_mem' is 1 to let all the Tx queues use a
consecutive memory area and a single MR.
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5.c | 14 ++
d
will make the Tx performance
more stable.
Signed-off-by: Bing Zhao
---
drivers/common/mlx5/mlx5_common.h | 2 +
drivers/common/mlx5/mlx5_common_devx.c | 77 +-
drivers/common/mlx5/mlx5_common_devx.h | 2 +-
drivers/common/mlx5/mlx5_devx_cmds.h | 5 ++
drivers
This patchset will move all the mlx5 Tx queues memory to a
consecutive memory area. All the WQEBBs will be allocated based
on the offset of this memory area.
---
v2:
1. add a new fix for legacy code of WQE calculation
2. fix the style
---
Bing Zhao (3):
net/mlx5: fix the WQE size
incorrect.
Fixes: 38b4b397a57d ("net/mlx5: add Tx configuration and setup")
Cc: viachesl...@mellanox.com
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5_txq.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/
With this commit, a new device argument is introduced to control
the memory allocation for Tx queues.
By default, 'txq_consec_mem' is 1 to let all the Tx queues use a
consecutive memory area and a single MR.
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5.c | 14 ++
d
will make the Tx performance
more stable.
Signed-off-by: Bing Zhao
---
drivers/common/mlx5/mlx5_common.h | 2 +
drivers/common/mlx5/mlx5_common_devx.c | 77 +-
drivers/common/mlx5/mlx5_common_devx.h | 2 +-
drivers/common/mlx5/mlx5_devx_cmds.h | 5 ++
drivers
und.
> -*/
> + /* The list of configurations to engage the workaround.
> + */
> break;
> default:
> /*
> -* The configuration is not found in the "white list".
> +* The configuration is not found in the list.
> * We should not engage the VLAN workaround.
> */
> return NULL;
> --
> 2.34.1
Acked-by: Bing Zhao
Hi,
> -Original Message-
> From: Dariusz Sosnowski
> Sent: Saturday, April 26, 2025 3:49 AM
> To: Slava Ovsiienko ; Bing Zhao
> ; Ori Kam ; Suanming Mou
> ; Matan Azrad
> Cc: dev@dpdk.org; sta...@dpdk.org
> Subject: [PATCH] net/mlx5: fix VLAN stripping on hairpi
this. Adding the NULL pointer check will help to get rid of such
warning.
Fixes: 5194299d6ef5 ("examples/ntb: support more functions")
Cc: xiaoyun...@intel.com
Signed-off-by: Bing Zhao
---
examples/ntb/ntb_fwd.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/ex
Hi,
> -Original Message-
> From: Maayan Kashani
> Sent: Sunday, April 27, 2025 7:28 PM
> To: dev@dpdk.org
> Cc: Maayan Kashani ; Dariusz Sosnowski
> ; Raslan Darawsheh ;
> sta...@dpdk.org; Alex Vesker ; Slava Ovsiienko
> ; Bing Zhao ; Ori Kam
> ; Suanming Mou
Hi Ming & Stephen,
> -Original Message-
> From: Yang Ming
> Sent: Wednesday, March 12, 2025 10:33 AM
> To: Stephen Hemminger ; Bing Zhao
>
> Cc: Dariusz Sosnowski ; Slava Ovsiienko
> ; Ori Kam ; Suanming Mou
> ; Matan Azrad ; dev@dpdk.org
> Subject: Re:
Hi Ming,
> -Original Message-
> From: Yang Ming
> Sent: Friday, December 13, 2024 5:25 PM
> To: Dariusz Sosnowski ; Slava Ovsiienko
> ; Bing Zhao ; Ori Kam
> ; Suanming Mou ; Matan Azrad
>
> Cc: dev@dpdk.org; Yang Ming
> Subject: [PATCH 2/2] net/
> -Original Message-
> From: Suanming Mou
> Sent: Wednesday, February 26, 2025 10:01 PM
> To: Dariusz Sosnowski ; Slava Ovsiienko
> ; Bing Zhao ; Ori Kam
> ; Matan Azrad
> Cc: dev@dpdk.org; Raslan Darawsheh ; Alex Vesker
>
> Subject: [PATCH v2 1/3] net/ml
Thanks a lot, Dariusz.
> -Original Message-
> From: Dariusz Sosnowski
> Sent: Thursday, February 27, 2025 12:04 AM
> To: Dariusz Sosnowski ; Slava Ovsiienko
> ; Bing Zhao ; Ori Kam
> ; Suanming Mou ; Matan Azrad
>
> Cc: dev@dpdk.org; Raslan Darawsheh
> Subje
Hi
> -Original Message-
> From: Suanming Mou
> Sent: Wednesday, February 26, 2025 9:43 PM
> To: Bing Zhao ; Dariusz Sosnowski
> ; Slava Ovsiienko ; Ori Kam
> ; Matan Azrad
> Cc: dev@dpdk.org; Raslan Darawsheh
> Subject: RE: [PATCH 3/3]
> -Original Message-
> From: Suanming Mou
> Sent: Tuesday, February 25, 2025 8:45 AM
> To: Dariusz Sosnowski ; Slava Ovsiienko
> ; Bing Zhao ; Ori Kam
> ; Matan Azrad
> Cc: dev@dpdk.org; Raslan Darawsheh
> Subject: [PATCH 3/3] net/mlx5: allow FDB RSS
>
Hi
> -Original Message-
> From: Suanming Mou
> Sent: Tuesday, February 25, 2025 8:45 AM
> To: Dariusz Sosnowski ; Slava Ovsiienko
> ; Bing Zhao ; Ori Kam
> ; Matan Azrad
> Cc: dev@dpdk.org; Raslan Darawsheh
> Subject: [PATCH 2/3] net/mlx5: add jump FDB Rx flag
Hi Suanming,
PSB
> -Original Message-
> From: Suanming Mou
> Sent: Tuesday, February 25, 2025 8:45 AM
> To: Dariusz Sosnowski ; Slava Ovsiienko
> ; Bing Zhao ; Ori Kam
> ; Matan Azrad
> Cc: dev@dpdk.org; Raslan Darawsheh ; Alex Vesker
>
> Subject: [PATCH
Support eCPRI item matching over L2 (ETHER / VLAN) in HWS, both for
template API and backward compatibility API.
Signed-off-by: Bing Zhao
Acked-by: Dariusz Sosnowski
---
v2: fix the checkpatch warning of unneeded else
v3: fix single line if condition code style warning
---
drivers/net/mlx5/hws
Support eCPRI item matching over L2 (ETHER / VLAN) in HWS, both for
template API and backward compatibility API.
Signed-off-by: Bing Zhao
Acked-by: Dariusz Sosnowski
---
v2: fix the checkpatch warning of unneeded else
---
drivers/net/mlx5/hws/mlx5dr_definer.c | 86
Support eCPRI item matching over L2 (ETHER / VLAN) in HWS, both for
template API and backward compatibility API.
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/hws/mlx5dr_definer.c | 86 +++
drivers/net/mlx5/mlx5_flow.h | 3 +
drivers/net/mlx5/mlx5_flow_hw.c
("net/mlx5: abstract flow action and enable reconfigure")
Cc: mkash...@nvidia.com
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5_flow.c| 11 +--
drivers/net/mlx5/mlx5_flow.h| 3 +++
drivers/net/mlx5/mlx5_flow_hw.c | 19 +++
3 files changed, 23 inserti
d be freed when the actions
construction is done.
Fixes: ff4064d5b1fe ("net/mlx5: support bulk actions in non-template flow")
Cc: mkash...@nvidia.com
Signed-off-by: Bing Zhao
Acked-by: Dariusz Sosnowski
---
v2: update the commit log
---
drivers/net/mlx5
x5: fix Rx queue control management")
Cc: sta...@dpdk.org
Signed-off-by: Bing Zhao
Acked-by: Dariusz Sosnowski
---
drivers/net/mlx5/mlx5_rx.h | 2 +-
drivers/net/mlx5/mlx5_rxq.c | 12 ++--
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_rx.
d when the actions
construction is done.
Fixes: ff4064d5b1fe ("net/mlx5: support bulk actions in non-template flow")
Cc: mkash...@nvidia.com
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5_flow_hw.c | 63 -
1 file changed, 39 insertions(+), 24 deleti
k.org
Signed-off-by: Bing Zhao
Acked-by: Dariusz Sosnowski
---
drivers/net/mlx5/mlx5_flow.h| 8
drivers/net/mlx5/mlx5_flow_hw.c | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 693e07218d..7028
ed.
Fixes: 3a2f674b6aa8 ("net/mlx5: add queue and RSS HW steering action")
Cc: sta...@dpdk.org
Signed-off-by: Bing Zhao
Acked-by: Dariusz Sosnowski
---
drivers/net/mlx5/mlx5.h | 1 +
drivers/net/mlx5/mlx5_flow.c | 3 +++
drivers/net/mlx5/mlx5_rxq.c | 8 +---
3 files changed
Thanks.
> -Original Message-
> From: Suanming Mou
> Sent: Wednesday, November 6, 2024 5:34 PM
> To: Dariusz Sosnowski ; Slava Ovsiienko
> ; Bing Zhao ; Ori Kam
> ; Matan Azrad
> Cc: dev@dpdk.org; sta...@dpdk.org
> Subject: [PATCH v2] doc: update match with compar
Suanming Mou
> Cc: Dariusz Sosnowski ; Slava Ovsiienko
> ; Bing Zhao ; Ori Kam
> ; Matan Azrad ; dev@dpdk.org;
> sta...@dpdk.org
> Subject: Re: [PATCH] doc: update match with compare result item limitation
>
> External email: Use caution opening links or attachments
>
&g
The ` repr_matching_en ` flag is enabled (by default) can be added.
> -Original Message-
> From: Suanming Mou
> Sent: Tuesday, November 5, 2024 9:48 AM
> To: Dariusz Sosnowski ; Slava Ovsiienko
> ; Bing Zhao ; Ori Kam
> ; Matan Azrad
> Cc: dev@dpdk.org; sta...@dpdk.
issue.
Fixes: f957ac996435 ("net/mlx5: workaround list management of Rx queue control")
Fixes: bcc220cb57d7 ("net/mlx5: fix shared Rx queue list management")
CC: sta...@dpdk.org
Signed-off-by: Bing Zhao
Acked-by: Viacheslav Ovsiienko
Acked-by: Dariusz Sosnowski
---
dri
- goto exit;
> - }
> } else {
> /*
> * The existence of several matching entries (nd > 1)
> means
> --
Acked-by: Bing Zhao
Thanks
> 2.18.1
The 'eswitch_owner_vhca_id_valid' only depends on the
'merged_eswitch' capability. And it should be set for all
vport actions.
Fixes: ac8415cfe760 ("net/mlx5/hws: set E-Switch owner VHC ID valid")
Cc: ere...@nvidia.com
Signed-off-by: Bing Zhao
Reviewed-by: Alex Ves
uot;, the LIST_REMOVE
will be called again and cause some UFA issue. If the memory is no
longer mapped, there will be a SIGSEGV.
Adding a flag in the Rx queue private structure to remove the
"rxq_ctrl" from the list only on the port/queue that allocated it.
Fixes: bcc220cb57d7 ("net/m
uot;, the LIST_REMOVE
will be called again and cause some UFA issue. If the memory is no
longer mapped, there will be a SIGSEGV.
Adding a flag in the Rx queue private structure to remove the
"rxq_ctrl" from the list only on the port/queue that allocated it.
Fixes: bcc220cb57d7 ("net/m
, decap, modify header and
matcher resource release under flow destroy cause all uses list/hlist
with return value 0/1.
Fixes: ff4064d5b1fe ("net/mlx5: support bulk actions in non-template flow")
Signed-off-by: Maayan Kashani
Acked-by: Dariusz Sosnowski
Signed-off-by: Bing Zhao
---
d
layers. In the meanwhile, unlike
in template API, the group information is also needed for the mask
translation.
Fixes: 27d171b88031 ("net/mlx5: abstract flow action and enable reconfigure")
Signed-off-by: Bing Zhao
Acked-by: Dariusz Sosnowski
---
drivers/net/mlx5/mlx5_flow_dv.c | 1
: b2845d51c748 ("net/mlx5: support FDB in non-template flow")
Signed-off-by: Maayan Kashani
Signed-off-by: Bing Zhao
Acked-by: Dariusz Sosnowski
---
drivers/net/mlx5/mlx5_flow_hw.c | 20 +++-
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/driver
he polling
of associative CQ will continue until a new CQE is generated.
Fixes: 87026d2e6601 ("net/mlx5/hws: support backward-compatible API")
Signed-off-by: Bing Zhao
Reviewed-by: Yevgeny Kliteynik
Acked-by: Dariusz Sosnowski
---
drivers/net/mlx5/hws/mlx5dr_bwc.c | 4 +++-
A set for cumulative fixes of non-template API support.
Bing Zhao (4):
net/mlx5/hws: fix state detection of queue full in polling
net/mlx5: fix releasing order of compatible matcher
net/mlx5: fix matcher mask translation
net/mlx5: fix log error on non-template rule destroy
drivers/net
Hi Patrick,
It seems to be so. The patch is only for mlx5 slow path configuration. There is
no reason that such change will impact the BRCM NIC performance.
Thanks.
BR. Bing
> -Original Message-
> From: Patrick Robb
> Sent: Thursday, July 18, 2024 4:58 AM
> To: Bing Zhao
fy RQT")
Cc: ma...@nvidia.com
Signed-off-by: Bing Zhao
Acked-by: Viacheslav Ovsiienko
---
drivers/common/mlx5/mlx5_devx_cmds.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c
b/drivers/common/mlx5/mlx5_devx_cmds.c
index 8e12ac50de..9710dcedd3 100644
PLINK will always try to be probed with any format.
Fixes: 2e569a370395 ("net/mlx5: add VF LAG mode bonding device recognition")
Signed-off-by: Bing Zhao
Acked-by: Viacheslav Ovsiienko
---
drivers/net/mlx5/linux/mlx5_os.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --gi
ome counters are missed. The "xstats_o_idx"
should be used instead of the iteration to check if the statistics
is an IB device counter.
In the meanwhile, adding another field to record the start index of
the IB counters to reduce the redundancy iterations.
Fixes: a687c3e658c2 ("net/m
ct-Thomas Monjalon (EXTERNAL)
> ; Suanming Mou ; Dariusz
> Sosnowski ; Bing Zhao ; Ori Kam
> ; Matan Azrad
> Cc: dev@dpdk.org; sta...@dpdk.org
> Subject: [PATCH 8/8] net/mlx5/hws: fix NA64 copy TOS field instead of TTL
>
> From: Erez Shitrit
>
> We don't have enough r
IC Rx rule.
Regarding the NIC Tx, only the metadata is relevant and it will be
copied in NIC Tx from REG_A into some REG_C_x. The current HWS
implementation already has already supported in the default copy
rule or the default SQ miss rule in the NIC Tx root table.
Signed-off-by: Bing Zhao
Ack
Hi,
> -Original Message-
> From: Mahmoud Maatuq
> Sent: Wednesday, July 3, 2024 4:15 AM
> To: Dariusz Sosnowski ; Slava Ovsiienko
> ; Bing Zhao ; Ori Kam
> ; Suanming Mou ; Matan Azrad
> ; Maayan Kashani
> Cc: dev@dpdk.org; Mahmoud Maatuq
> Subject: [PATC
IC Rx rule.
Regarding the NIC Tx, only the metadata is relevant and it will be
copied in NIC Tx from REG_A into some REG_C_x. The current HWS
implementation already has already supported in the default copy
rule or the default SQ miss rule in the NIC Tx root table.
Signed-off-by: Bing Zhao
Ack
From: Rongwei Liu
When devargs "allow_duplicate_pattern=0" is specified, PMD won't
allow duplicated flows to be inserted and return EEXIST as rte_errno.
The queue/RSS split table is shared globally by all representors and
PMD didn't prepend port information into it, so all the following ports
tr
. In the meanwhile, since the
action handles are already destroyed, it makes no sense to hold the
indirect action software resources anymore.
Fixes: f7352c176bbf ("app/testpmd: fix use of indirect action after port close")
Cc: dmitry.kozl...@gmail.com
Cc: sta...@dpdk.org
Signed-off-by:
Hi Ferruh,
> -Original Message-
> From: Ferruh Yigit
> Sent: Tuesday, March 19, 2024 10:21 PM
> To: Bing Zhao ; dmitry.kozl...@gmail.com;
> dev@dpdk.org
> Cc: aman.deep.si...@intel.com; yuying.zh...@intel.com; Matan Azrad
> ; sta...@dpdk.org; Dariusz Sosnowski
>
closed again.
Fixes: f7352c176bbf ("app/testpmd: fix use of indirect action after port close")
Cc: dmitry.kozl...@gmail.com
Cc: sta...@dpdk.org
Signed-off-by: Bing Zhao
Reviewed-by: Dariusz Sosnowski
---
app/test-pmd/config.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletion
. This would cause
the counter set resources to be exhausted after starting and stopping
the ports repeatedly.
Fixes: 65b3cd0dc39b ("net/mlx5: create global drop action")
Cc: suanmi...@nvidia.com
Cc: sta...@dpdk.org
Signed-off-by: Bing Zhao
Acked-by: Suanming Mou
---
drivers/net/mlx5/
t;net/mlx5: use aging by counter when counter exists")
Cc: michae...@nvidia.com
Cc: sta...@dpdk.org
Signed-off-by: Bing Zhao
Acked-by: Ori Kam
---
drivers/net/mlx5/mlx5_flow.c| 1 +
drivers/net/mlx5/mlx5_flow_dv.c | 3 +--
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/d
From: Eli Britstein
The following log is printed in WARNING severity:
mlx5_net: port 1 ioctl(SIOCETHTOOL, ETHTOOL_GPAUSEPARAM) failed:
Operation not supported
Reduce the severity to DEBUG to prevent this log from flooding
when there are hundreds of ports probed without supporting this
flow
d69 ("net/mlx5: improve xstats of bonding port")
Cc: xuemi...@nvidia.com
Cc: sta...@dpdk.org
Signed-off-by: Bing Zhao
Acked-by: Viacheslav Ovsiienko
---
drivers/net/mlx5/linux/mlx5_ethdev_os.c | 249 +++---
drivers/net/mlx5/mlx5.h | 15
application should not try to
match these TAGs after the rule that contains NAT64 action.
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5_flow.h| 1 +
drivers/net/mlx5/mlx5_flow_hw.c | 51 +
2 files changed, 52 insertions(+)
diff --git a/drivers/net/mlx5
The action will handle the IPv4 and IPv6 headers translation. It will
add / remove IPv6 address prefix by default.
To use the user specific address, another rule to modify the
addresses of the IP header is needed.
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5_flow_hw.c | 20
The NAT64 DR actions can be shared among the tables. All these
actions can be created during configuring the flow queues and saved
for the future usage.
Even the actions can be shared now, inside per each flow rule, the
actual hardware resources are unique.
Signed-off-by: Bing Zhao
---
doc
-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5.c | 9 +
drivers/net/mlx5/mlx5.h | 2 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index f2ca0ae4c2..cc7cd6adf5 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -1644,6
From: Erez Shitrit
Add support of new action mlx5dr_action_create_nat64.
The new action allows to modify IP packets from version to version, IPV6
to IPV4 and vice versa.
Signed-off-by: Erez Shitrit
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/hws/mlx5dr.h| 29 ++
drivers/net/mlx5
v3:
1. code style and typo.
Update in v2:
1. separate from the RTE and testpmd common part.
2. reorder the commits.
3. bug fix, code polishing and document update.
Bing Zhao (4):
net/mlx5: fetch the available registers for NAT64
net/mlx5: create NAT64 actions during configuration
flow registers in shared
context")
Cc: getel...@nvidia.com
Cc: sta...@dpdk.org
Signed-off-by: Bing Zhao
Acked-by: Suanming Mou
---
drivers/net/mlx5/mlx5.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index 881c42a97a..
allocation and flow rule creation on the
representor port.
Fixes: 0f0ae73a3287 ("net/mlx5: add parameter for LACP packets control")
Fixes: 49dffadf4b0c ("net/mlx5: fix LACP redirection in Rx domain")
Cc: sta...@dpdk.org
Signed-off-by: Bing Zhao
Acked-by: Suanming Mou
-
From: Hamdan Igbaria
Set the correct VLAN inner_type value, till today the
once the VLAN inner_type field was set, an incorrect
value was taken instead of the inner_type field.
Fixes: c55c2bf35333 ("net/mlx5/hws: add definer layer")
Cc: sta...@dpdk.org
Signed-off-by: Hamdan Igbaria
Reviewed-by
From: Hamdan Igbaria
If a VLAN item was passed with null mask, the item handler would
return immediately and thus won't set default values for non relax
mode.
Also change the non relax default set to single-tagged (CVLAN).
Fixes: c55c2bf35333 ("net/mlx5/hws: add definer layer")
Cc: sta...@dpdk.o
From: Hamdan Igbaria
If a VLAN item was passed with null mask, the item handler would
return immediately and thus won't set default values for non relax
mode.
Also change the non relax default set to single-tagged (CVLAN).
Fixes: c55c2bf35333 ("net/mlx5/hws: add definer layer")
Cc: sta...@dpdk.o
valid pointers
would cause a crash.
With this commit, the flag of the per port aging initialization will
be checked. This would help to get rid of the invalid accessing.
Fixes: 04a4de756e14 ("net/mlx5: support flow age action with HWS")
Cc: michae...@nvidia.com
Cc: sta...@dpdk.org
Sign
The action will handle the IPv4 and IPv6 headers translation. It will
add / remove IPv6 address prefix by default.
To use the user specific address, another rule to modify the
addresses of the IP header is needed.
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5_flow_hw.c | 20
application should not try to
match these TAGs after the rule that contains NAT64 action.
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5_flow.h| 1 +
drivers/net/mlx5/mlx5_flow_hw.c | 51 +
2 files changed, 52 insertions(+)
diff --git a/drivers/net/mlx5
The NAT64 DR actions can be shared among the tables. All these
actions can be created during configuring the flow queues and saved
for the future usage.
Even the actions can be shared now, inside per each flow rule, the
actual hardware resources are unique.
Signed-off-by: Bing Zhao
---
doc
-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5.c | 9 +
drivers/net/mlx5/mlx5.h | 2 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index 881c42a97a..9c3b9946e3 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -1644,6
From: Erez Shitrit
Add support of new action mlx5dr_action_create_nat64.
The new action allows to modify IP packets from version to version, IPV6
to IPV4 and vice versa.
Signed-off-by: Erez Shitrit
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/hws/mlx5dr.h| 29 ++
drivers/net/mlx5
This patch set contains the mlx5 PMD implementation for NAT64.
Update in v3:
1. code style and typo.
Update in v2:
1. separate from the RTE and testpmd common part.
2. reorder the commits.
3. bug fix, code polishing and document update.
Bing Zhao (4):
net/mlx5: fetch the available
application should not try to
match these TAGs after the rule that contains NAT64 action.
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5_flow.h| 1 +
drivers/net/mlx5/mlx5_flow_hw.c | 51 +
2 files changed, 52 insertions(+)
diff --git a/drivers/net/mlx5
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