Support eCPRI item matching over L2 (ETHER / VLAN) in HWS, both for
template API and backward compatibility API.
Signed-off-by: Bing Zhao <bi...@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnow...@nvidia.com>
---
v2: fix the checkpatch warning of unneeded else
v3: fix single line if condition code style warning
---
drivers/net/mlx5/hws/mlx5dr_definer.c | 86 +++++++++++++++++++++++++++
drivers/net/mlx5/mlx5_flow.h | 3 +
drivers/net/mlx5/mlx5_flow_hw.c | 59 ++++++++++++++++++
3 files changed, 148 insertions(+)
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c
b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 837e0c47bd..25087022c1 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -583,6 +583,35 @@ mlx5dr_definer_ipv6_routing_ext_set(struct
mlx5dr_definer_fc *fc,
DR_SET(tag, val, fc->byte_off, 0, fc->bit_mask);
}
+static void
+mlx5dr_definer_ecpri_common_set(struct mlx5dr_definer_fc *fc,
+ const void *item,
+ uint8_t *tag)
+{
+ const struct rte_flow_item_ecpri *ec = item;
+ uint32_t val;
+
+ val = ec->hdr.common.u32;
+
+ DR_SET_BE32(tag, val, fc->byte_off, 0, fc->bit_mask);
+}
+
+static void
+mlx5dr_definer_ecpri_body_set(struct mlx5dr_definer_fc *fc,
+ const void *item,
+ uint8_t *tag)
+{
+ const struct rte_flow_item_ecpri *ec = item;
+ uint32_t val, idx;
+
+
+ idx = fc->fname - MLX5DR_DEFINER_FNAME_FLEX_PARSER_0;
+ /* The 1st DW is used for common field, indeed, there are only 2 DWs. */
+ val = ec->hdr.dummy[idx - 1];
+
+ DR_SET_BE32(tag, val, fc->byte_off, 0, fc->bit_mask);
+}
+
static void
mlx5dr_definer_flex_parser_set(struct mlx5dr_definer_fc *fc,
const void *item,
@@ -2555,6 +2584,59 @@ mlx5dr_definer_conv_item_random(struct
mlx5dr_definer_conv_data *cd,
return 0;
}
+static uint32_t
+mlx5dr_definer_get_ecpri_parser_byte_off_from_ctx(void *dr_ctx, uint32_t
*byte_off)
+{
+ uint32_t base_off = MLX5_BYTE_OFF(definer_hl,
flex_parser.flex_parser_0);
+ struct mlx5_ecpri_parser_profile *ecp;
+ uint32_t i;
+
+ ecp = flow_hw_get_ecpri_parser_profile(dr_ctx);
+ if (!ecp)
+ return UINT32_MAX;
+ for (i = 0; i < ecp->num; i++)
+ byte_off[i] = base_off - ecp->ids[i] * sizeof(uint32_t);
+ return i;
+}
+
+static int
+mlx5dr_definer_conv_item_ecpri(struct mlx5dr_definer_conv_data *cd,
+ struct rte_flow_item *item,
+ int item_idx)
+{
+ const struct rte_flow_item_ecpri *m;
+ uint32_t i, mask, byte_off[8] = {0};
+ struct mlx5dr_definer_fc *fc;
+ uint32_t num_dws;
+
+ num_dws = mlx5dr_definer_get_ecpri_parser_byte_off_from_ctx(cd->ctx,
byte_off);
+ if (num_dws == UINT32_MAX) {
+ DR_LOG(ERR, "failed to get eCPRI samples %d", -rte_errno);
+ return rte_errno;
+ }
+
+ m = item->mask;
+ if (!m)
+ return 0;
+
+ for (i = 0; i < num_dws; i++) {
+ mask = i == 0 ? m->hdr.common.u32 : m->hdr.dummy[i - 1];
+ if (!mask)
+ continue;
+ mask = htobe32(mask);
+ fc = mlx5dr_definer_get_flex_parser_fc(cd, byte_off[i]);
+ if (!fc)
+ return rte_errno;
+
+ fc->item_idx = item_idx;
+ fc->tag_set = i == 0 ? &mlx5dr_definer_ecpri_common_set :
+ &mlx5dr_definer_ecpri_body_set;
+ fc->tag_mask_set = &mlx5dr_definer_ones_set;
+ fc->bit_mask = mask;
+ }
+ return 0;
+}
+
static int
mlx5dr_definer_conv_item_geneve(struct mlx5dr_definer_conv_data *cd,
struct rte_flow_item *item,
@@ -3314,6 +3396,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context
*ctx,
MLX5_FLOW_ITEM_OUTER_FLEX;
}
break;
+ case RTE_FLOW_ITEM_TYPE_ECPRI:
+ ret = mlx5dr_definer_conv_item_ecpri(&cd, items, i);
+ item_flags |= MLX5_FLOW_LAYER_ECPRI;
+ break;
case RTE_FLOW_ITEM_TYPE_MPLS:
ret = mlx5dr_definer_conv_item_mpls(&cd, items, i);
item_flags |= MLX5_FLOW_LAYER_MPLS;
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 445c9cdb4b..e5245edd46 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -1812,6 +1812,7 @@ flow_hw_get_reg_id_from_ctx(void *dr_ctx, enum
rte_flow_item_type type,
#endif
+
/*
* Define list of valid combinations of RX Hash fields
* (see enum ibv_rx_hash_fields).
@@ -3704,5 +3705,7 @@ mlx5_flow_nta_update_copy_table(struct rte_eth_dev *dev,
uint64_t action_flags,
struct rte_flow_error *error);
+struct mlx5_ecpri_parser_profile *flow_hw_get_ecpri_parser_profile(void
*dr_ctx);
+
#endif
#endif /* RTE_PMD_MLX5_FLOW_H_ */
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index e72b87d70f..48b1b5f95e 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -5096,6 +5096,16 @@ flow_hw_table_create(struct rte_eth_dev *dev,
NULL, "pattern template domain does
not match table");
return NULL;
}
+ if (item_templates[i]->item_flags & MLX5_FLOW_LAYER_ECPRI &&
+ !mlx5_flex_parser_ecpri_exist(dev))
+ if (mlx5_flex_parser_ecpri_alloc(dev)) {
+ rte_flow_error_set(error, EIO,
+
RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "failed to create Flex
parser "
+ "profile for ECPRI");
+ goto error;
+ }
}
for (i = 0; i < nb_action_templates; i++) {
const struct rte_flow_actions_template *at =
action_templates[i];
@@ -8389,6 +8399,16 @@ const struct rte_flow_item_ipv6 hws_nic_ipv6_mask = {
.has_frag_ext = 1,
};
+const struct rte_flow_item_ecpri hws_nic_ecpri_mask = {
+ .hdr = {
+ .common = {
+ .u32 = RTE_BE32(0xffffffff),
+ },
+ .dummy[0] = 0xffffffff,
+ },
+};
+
+
static int
flow_hw_validate_item_ptype(const struct rte_flow_item *item,
struct rte_flow_error *error)
@@ -8831,6 +8851,14 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,
* template and item spec in flow rule.
*/
break;
+ case RTE_FLOW_ITEM_TYPE_ECPRI:
+ ret = mlx5_flow_validate_item_ecpri(dev, item,
*item_flags, last_item,
+
RTE_ETHER_TYPE_ECPRI,
+
&hws_nic_ecpri_mask, error);
+ if (ret < 0)
+ return ret;
+ *item_flags |= MLX5_FLOW_LAYER_ECPRI;
+ break;
case RTE_FLOW_ITEM_TYPE_IB_BTH:
case RTE_FLOW_ITEM_TYPE_VOID:
case RTE_FLOW_ITEM_TYPE_END:
@@ -13859,6 +13887,15 @@ flow_hw_create_flow(struct rte_eth_dev *dev, enum
mlx5_flow_type type,
if (ret)
goto error;
+ if (item_flags & MLX5_FLOW_LAYER_ECPRI &&
!mlx5_flex_parser_ecpri_exist(dev))
+ if (mlx5_flex_parser_ecpri_alloc(dev)) {
+ rte_flow_error_set(error, EIO,
+ RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "failed to create Flex parser "
+ "profile for ECPRI");
+ goto error;
+ }
ret = flow_hw_register_matcher(dev, attr, items, external, *flow,
&matcher, error);
if (ret)
goto error;
@@ -16341,6 +16378,7 @@ mlx5_flow_hw_ctrl_flow_dmac(struct rte_eth_dev *dev,
addr, 0);
}
+
int
mlx5_flow_hw_ctrl_flow_dmac_destroy(struct rte_eth_dev *dev,
const struct rte_ether_addr *addr)
@@ -16422,6 +16460,27 @@ mlx5_flow_hw_ctrl_flow_dmac_vlan_destroy(struct
rte_eth_dev *dev,
return 0;
}
+struct mlx5_ecpri_parser_profile *
+flow_hw_get_ecpri_parser_profile(void *dr_ctx)
+{
+ uint16_t port_id;
+ bool found = false;
+ struct mlx5_priv *priv;
+
+ MLX5_ETH_FOREACH_DEV(port_id, NULL) {
+ priv = rte_eth_devices[port_id].data->dev_private;
+ if (priv->dr_ctx == dr_ctx) {
+ found = true;
+ break;
+ }
+ }
+ if (found)
+ return &priv->sh->ecpri_parser;
+ rte_errno = ENODEV;
+ return NULL;
+}
+
+
static __rte_always_inline uint32_t
mlx5_reformat_domain_to_tbl_type(const struct rte_flow_indir_action_conf
*domain)
{
--
2.34.1
