In both SWS and HWS mode, default ingress RSS flows are always
created via the driver on the root table. In the current driver,
the first created flow rules will be matched firstly when:
1. >= 2 rules can be matched on the root table.
2. the rules have the same priority.
All MC / BC flow rules would have the same priority and discard
the input priority from the user space in the driver. All rules have
a fixed priority 32 when the Ethernet destination MAC is a MC or BC
address.
In SWS non-template API, all the device rules are added into the list
and applied in a reverse order.
This patch syncs default flow rule creation order between SWS and HWS.
The order should be:
1. IPv4(6) + TCP/UDP, if required.
2. IPv4(6) only, if required.
3. None IP traffic.
Fixes: 9fa7c1cddb85 ("net/mlx5: create control flow rules with HWS")
Cc: dsosnow...@nvidia.com
Cc: sta...@dpdk.org
Signed-off-by: Bing Zhao <bi...@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnow...@nvidia.com>
---
drivers/net/mlx5/mlx5_flow.h | 8 ++++----
drivers/net/mlx5/mlx5_flow_hw.c | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 693e07218d..702878c1d8 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -2941,13 +2941,13 @@ enum mlx5_flow_ctrl_rx_eth_pattern_type {
/* All types of RSS actions used in control flow rules. */
enum mlx5_flow_ctrl_rx_expanded_rss_type {
- MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_NON_IP = 0,
- MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4,
+ MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP = 0,
+ MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP,
MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP,
MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP,
MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6,
- MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP,
- MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP,
+ MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4,
+ MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_NON_IP,
MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX,
};
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 2a9ef71cd8..a75bcd5c67 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -16157,7 +16157,7 @@ mlx5_flow_hw_ctrl_flows(struct rte_eth_dev *dev,
uint32_t flags)
struct mlx5_priv *priv = dev->data->dev_private;
struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
unsigned int i;
- unsigned int j;
+ int j;
int ret = 0;
RTE_SET_USED(priv);
--
2.34.1
