@@ -4619,6 +4619,12 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
// Buffer is a void**.
Address Buf = EmitPointerWithAlignment(E->getArg(0));
+if (getTarget().getTriple().getArch() == llvm::Triple::systemz) {
+ // Call L
@@ -6292,6 +6534,10 @@ SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
return lowerGET_ROUNDING(Op, DAG);
case ISD::READCYCLECOUNTER:
return lowerREADCYCLECOUNTER(Op, DAG);
+ case ISD::EH_SJLJ_SETJMP:
+ case ISD::EH_SJLJ_LONGJMP:
+return Op;
--
@@ -940,7 +947,242 @@ bool SystemZTargetLowering::isFPImmLegal(const APFloat
&Imm, EVT VT,
return SystemZVectorConstantInfo(Imm).isVectorConstantLegal(Subtarget);
}
-/// Returns true if stack probing through inline assembly is requested.
+
+MachineBasicBlock *
+SystemZTarge
@@ -751,6 +751,13 @@ SystemZTargetLowering::SystemZTargetLowering(const
TargetMachine &TM,
setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
+ // We're not using SJLJ for exception handling, b
@@ -940,7 +947,242 @@ bool SystemZTargetLowering::isFPImmLegal(const APFloat
&Imm, EVT VT,
return SystemZVectorConstantInfo(Imm).isVectorConstantLegal(Subtarget);
}
-/// Returns true if stack probing through inline assembly is requested.
+
+MachineBasicBlock *
+SystemZTarge
@@ -6108,6 +6160,133 @@ static SDValue lowerAddrSpaceCast(SDValue Op,
SelectionDAG &DAG) {
return Op;
}
+SDValue SystemZTargetLowering::LowerFP_EXTEND(SDValue Op,
+ SelectionDAG &DAG) const {
+ bool IsStrict = Op->isStrictFPOpco
@@ -6108,6 +6160,133 @@ static SDValue lowerAddrSpaceCast(SDValue Op,
SelectionDAG &DAG) {
return Op;
}
+SDValue SystemZTargetLowering::LowerFP_EXTEND(SDValue Op,
+ SelectionDAG &DAG) const {
+ bool IsStrict = Op->isStrictFPOpco
@@ -185,6 +185,8 @@ bool SystemZABIInfo::isFPArgumentType(QualType Ty) const {
if (const BuiltinType *BT = Ty->getAs())
switch (BT->getKind()) {
+case BuiltinType::Half: // __fp16
uweigand wrote:
Then I think we shouldn't have this either.
http
https://github.com/uweigand edited
https://github.com/llvm/llvm-project/pull/109164
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@@ -91,11 +91,28 @@ class LLVM_LIBRARY_VISIBILITY SystemZTargetInfo : public
TargetInfo {
"-v128:64-a:8:16-n32:64");
}
MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 128;
+
+// True if the backend supports operations on the half LLVM IR type.
@@ -723,6 +729,7 @@ class SystemZTargetLowering : public TargetLowering {
SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
+
uweigand wrote:
This shouldn't be here.
https:
@@ -940,7 +947,242 @@ bool SystemZTargetLowering::isFPImmLegal(const APFloat
&Imm, EVT VT,
return SystemZVectorConstantInfo(Imm).isVectorConstantLegal(Subtarget);
}
-/// Returns true if stack probing through inline assembly is requested.
+
+MachineBasicBlock *
+SystemZTarge
@@ -513,11 +514,26 @@ SystemZTargetLowering::SystemZTargetLowering(const
TargetMachine &TM,
}
// Handle floating-point types.
+ // Promote all f16 operations to float, with some exceptions below.
+ for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
+setOperati
uweigand wrote:
> Improved handling to utilize vector instructions when present.
Thanks!
>New VR16 regclass, but v8f16 _not_ legal. It might make sense to have it as a
>legal type and e.g. do VL;VST when moving vectors in memory, and also set all
>vector ops to "Expand". Not sure how trivial
@@ -1883,6 +1931,10 @@ void SystemZInstrInfo::getLoadStoreOpcodes(const
TargetRegisterClass *RC,
} else if (RC == &SystemZ::FP128BitRegClass) {
LoadOpcode = SystemZ::LX;
StoreOpcode = SystemZ::STX;
+ } else if (RC == &SystemZ::FP16BitRegClass ||
+ RC ==
@@ -47,8 +49,11 @@ def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>;
def LXR : UnaryRRE<"lxr", 0xB365, null_frag, FP128, FP128>;
// For z13 we prefer LDR over LER to avoid partial register dependencies.
-let isCodeGenOnly = 1 in
- def LDR32 : UnaryRR<"ldr", 0x28, nul
@@ -4619,6 +4619,31 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
// Buffer is a void**.
Address Buf = EmitPointerWithAlignment(E->getArg(0));
+if (getTarget().getTriple().getArch() == llvm::Triple::systemz) {
+ // Call L
https://github.com/uweigand commented:
This now looks good to me (see one inline comment). The only part missing is
the doc change as discussed above - can you add this to the PR here? Then it
should be good to go. Thanks!
https://github.com/llvm/llvm-project/pull/116642
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@@ -1,4 +1,4 @@
-//===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation
-===//
+//===-- systemzisellowering.cpp - systemz dag lowering implementation
-===//
uweigand wrote:
This seems to be some accidental change? Please remove.
https:
https://github.com/uweigand commented:
One last comment, then it looks good to go for me. Thanks!
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@@ -374,10 +374,11 @@ overall functioning of this intrinsic is compatible with
the GCC
to interoperate.
The single parameter is a pointer to a five word buffer in which the calling
-context is saved. The front end places the frame pointer in the first word, and
-the target im
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uweigand wrote:
The s390x failure is just an unstable test that occasionally fails - that
woudn't be a reason to revert. Cannot say about the arm64-windows failure.
https://github.com/llvm/llvm-project/pull/118734
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@@ -2563,9 +2563,15 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
if ((i < ResultRegIsFlagReg.size()) && ResultRegIsFlagReg[i]) {
// Target must guarantee the Value `Tmp` here is lowered to a boolean
// value.
- llvm::Constant *Two = llvm::Consta
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uweigand wrote:
@redstar looks like this disables an optimization on z/OS with mixed pointer
widths. Please have a look whether this is relevant.
https://github.com/llvm/llvm-project/pull/119365
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https://github.com/uweigand commented:
Thanks for fixing those issues. Just a couple of further comments inline.
https://github.com/llvm/llvm-project/pull/119257
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@@ -374,10 +374,11 @@ overall functioning of this intrinsic is compatible with
the GCC
to interoperate.
The single parameter is a pointer to a five word buffer in which the calling
-context is saved. The front end places the frame pointer in the first word, and
-the target im
@@ -0,0 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; Test longjmp load from jmp_buf.
+; Frame pointer from Slot 1.
+; Jump address from Slot 2.
+; Backchain Value from Slot 3.
+; Stack Pointer from Slot 4.
+; Lit
https://github.com/uweigand approved this pull request.
LGTM, let's try to merge again.
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uweigand wrote:
The s390x failures are unrelated.
https://github.com/llvm/llvm-project/pull/111918
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https://github.com/uweigand approved this pull request.
LGTM now. Thanks for your contribution!
https://github.com/llvm/llvm-project/pull/116642
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Author: Ulrich Weigand
Date: 2024-12-07T00:55:54+01:00
New Revision: 8787bc72a61aa43a6e937647b6797ddb2ff287d2
URL:
https://github.com/llvm/llvm-project/commit/8787bc72a61aa43a6e937647b6797ddb2ff287d2
DIFF:
https://github.com/llvm/llvm-project/commit/8787bc72a61aa43a6e937647b6797ddb2ff287d2.diff
uweigand wrote:
Hi @anoopkg6 , I had to revert this again as it was causing a number of issues:
- An unused variable warning fixed here:
https://github.com/llvm/llvm-project/commit/3c47e63723b1aa9e76f30fc8d1acef9caf4ea783
- The fuchsia build bot failure - I'm not completely sure what causes thi
@@ -6292,6 +6534,10 @@ SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
return lowerGET_ROUNDING(Op, DAG);
case ISD::READCYCLECOUNTER:
return lowerREADCYCLECOUNTER(Op, DAG);
+ case ISD::EH_SJLJ_SETJMP:
+ case ISD::EH_SJLJ_LONGJMP:
+return Op;
--
@@ -0,0 +1,255 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; Simulate register pressure around setjmp call for integer arguments.
+; Test assembly of funtion call foo in func() in setjmp if and else part.
+; extern foo
@@ -0,0 +1,25 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
uweigand wrote:
I don't think we need a -backchain version of the test case here - what's
tested here is completely identical as far as the fro
@@ -940,6 +945,240 @@ bool SystemZTargetLowering::isFPImmLegal(const APFloat
&Imm, EVT VT,
return SystemZVectorConstantInfo(Imm).isVectorConstantLegal(Subtarget);
}
+MachineBasicBlock *
+SystemZTargetLowering::emitEHSjLjSetJmp(MachineInstr &MI,
+
@@ -4619,6 +4619,31 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
// Buffer is a void**.
Address Buf = EmitPointerWithAlignment(E->getArg(0));
+if (getTarget().getTriple().getArch() == llvm::Triple::systemz) {
+ // Call L
@@ -0,0 +1,123 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
uweigand wrote:
Here I think it would be good to add one more test, to verify that the *frame
pointer* is saved if it is live - this is curren
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https://github.com/uweigand commented:
I think we're getting close now - but I still have a few comments below.
Thanks!
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uweigand wrote:
> I see a lot of target specific pre-processing in clear_cache.c that either
> disables this to a no-op, or does something target specific. The test itself
> this is disabled for some targets. Seems reasonable to leave this as
> unsupported and disable the test (for now?). Also
@@ -119,6 +119,12 @@ class LLVM_LIBRARY_VISIBILITY SystemZTargetInfo : public
TargetInfo {
TargetInfo::ConstraintInfo &info) const override;
std::string convertConstraint(const char *&Constraint) const override {
+if (llvm::StringRef(Constra
@@ -119,6 +119,12 @@ class LLVM_LIBRARY_VISIBILITY SystemZTargetInfo : public
TargetInfo {
TargetInfo::ConstraintInfo &info) const override;
std::string convertConstraint(const char *&Constraint) const override {
+if (llvm::StringRef(Constra
@@ -12112,18 +12138,36 @@ void
SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
const APInt &SmallValue = Small.Low->getValue();
const APInt &BigValue = Big.Low->getValue();
+ // Incoming IR is switch table.Identify SRL/IPM/CC sequence fo
@@ -2837,8 +2837,34 @@ void SelectionDAGBuilder::visitBr(const BranchInst &I) {
Opcode = Instruction::And;
else if (match(BOp, m_LogicalOr(m_Value(BOp0), m_Value(BOp1
Opcode = Instruction::Or;
-
-if (Opcode &&
+auto &TLI = DAG.getTargetLoweringInfo()
@@ -2621,9 +2621,25 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
if ((i < ResultRegIsFlagReg.size()) && ResultRegIsFlagReg[i]) {
// Target must guarantee the Value `Tmp` here is lowered to a boolean
// value.
- llvm::Constant *Two = llvm::Consta
@@ -35,100 +35,96 @@ using namespace llvm;
#include "SystemZGenRegisterInfo.inc"
const unsigned SystemZMC::GR32Regs[16] = {
- SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L,
- SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L,
- SystemZ::R8L, SystemZ::R9L, Syst
@@ -541,11 +543,26 @@ SystemZTargetLowering::SystemZTargetLowering(const
TargetMachine &TM,
}
// Handle floating-point types.
+ // Promote all f16 operations to float, with some exceptions below.
+ for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
+setOperati
@@ -65,6 +65,7 @@ void __clear_cache(void *start, void *end) {
#elif defined(_WIN32) && (defined(__arm__) || defined(__aarch64__))
FlushInstructionCache(GetCurrentProcess(), start, end - start);
#elif defined(__arm__) && !defined(__APPLE__)
+#elif defined(__s390__)
--
@@ -6769,11 +6898,20 @@ SystemZTargetLowering::LowerOperationWrapper(SDNode *N,
break;
}
case ISD::BITCAST: {
+SDLoc DL(N);
SDValue Src = N->getOperand(0);
-if (N->getValueType(0) == MVT::i128 && Src.getValueType() == MVT::f128 &&
-!useSoftFloat())
@@ -179,20 +179,31 @@ bool SystemZABIInfo::isVectorArgumentType(QualType Ty)
const {
getContext().getTypeSize(Ty) <= 128);
}
-bool SystemZABIInfo::isFPArgumentType(QualType Ty) const {
+// The Size argument will in case of af an overaligned single element struct
+//
@@ -6464,6 +6522,70 @@ static SDValue lowerAddrSpaceCast(SDValue Op,
SelectionDAG &DAG) {
return Op;
}
+SDValue SystemZTargetLowering::lowerFP_EXTEND(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDValue In = Op.getOperand(Op->isSt
@@ -6769,11 +6898,20 @@ SystemZTargetLowering::LowerOperationWrapper(SDNode *N,
break;
}
case ISD::BITCAST: {
+SDLoc DL(N);
SDValue Src = N->getOperand(0);
-if (N->getValueType(0) == MVT::i128 && Src.getValueType() == MVT::f128 &&
-!useSoftFloat())
@@ -229,7 +229,7 @@ class TargetInfo : public TransferrableTargetInfo,
bool NoAsmVariants; // True if {|} are normal characters.
bool HasLegalHalfType; // True if the backend supports operations on the half
// LLVM IR type.
- bool HalfArgsAndRetur
Author: Ulrich Weigand
Date: 2025-02-14T00:10:37+01:00
New Revision: adacbf68ebeaeaf9d07a5beaff163da9ca0534a9
URL:
https://github.com/llvm/llvm-project/commit/adacbf68ebeaeaf9d07a5beaff163da9ca0534a9
DIFF:
https://github.com/llvm/llvm-project/commit/adacbf68ebeaeaf9d07a5beaff163da9ca0534a9.diff
@@ -115,10 +115,19 @@ class LLVM_LIBRARY_VISIBILITY SystemZTargetInfo : public
TargetInfo {
return RegName == "r15";
}
+ // CC has interval [0, 4).
+ unsigned getFlagOutputCCUpperBound() const override { return 4; }
bool validateAsmConstraint(const char *&Name,
@@ -8132,7 +8722,9 @@ SDValue SystemZTargetLowering::combineBR_CCMASK(
SDValue Chain = N->getOperand(0);
SDValue CCReg = N->getOperand(4);
- if (combineCCMask(CCReg, CCValidVal, CCMaskVal))
+ // combineCCIPMMask tries to combine srl/ipm sequence for flag output
operand.
@@ -2837,8 +2837,37 @@ void SelectionDAGBuilder::visitBr(const BranchInst &I) {
Opcode = Instruction::And;
else if (match(BOp, m_LogicalOr(m_Value(BOp0), m_Value(BOp1
Opcode = Instruction::Or;
-
-if (Opcode &&
+auto &TLI = DAG.getTargetLoweringInfo()
@@ -1689,6 +1696,35 @@ Register
SystemZTargetLowering::getExceptionSelectorRegister(
return Subtarget.isTargetXPLINK64() ? SystemZ::R2D : SystemZ::R7D;
}
+// Lower @cc targets via setcc.
+SDValue SystemZTargetLowering::LowerAsmOutputForConstraint(
+SDValue &Chain, SDVal
@@ -115,10 +115,19 @@ class LLVM_LIBRARY_VISIBILITY SystemZTargetInfo : public
TargetInfo {
return RegName == "r15";
}
+ // CC has interval [0, 4).
+ unsigned getFlagOutputCCUpperBound() const override { return 4; }
bool validateAsmConstraint(const char *&Name,
@@ -3830,6 +3876,14 @@ SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
ISD::CondCode CC = cast(Op.getOperand(4))->get();
SDLoc DL(Op);
+ // SELECT_CC involving f16 will not have the cmp-ops promoted by the
+ // legalizer, as it will be handled according to the
@@ -6470,6 +6540,84 @@ static SDValue lowerAddrSpaceCast(SDValue Op,
SelectionDAG &DAG) {
return Op;
}
+SDValue SystemZTargetLowering::lowerFP_EXTEND(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDValue In = Op.getOperand(Op->isSt
@@ -179,20 +179,31 @@ bool SystemZABIInfo::isVectorArgumentType(QualType Ty)
const {
getContext().getTypeSize(Ty) <= 128);
}
-bool SystemZABIInfo::isFPArgumentType(QualType Ty) const {
+// The Size argument will in case of af an overaligned single element struct
+//
@@ -6769,11 +6898,20 @@ SystemZTargetLowering::LowerOperationWrapper(SDNode *N,
break;
}
case ISD::BITCAST: {
+SDLoc DL(N);
SDValue Src = N->getOperand(0);
-if (N->getValueType(0) == MVT::i128 && Src.getValueType() == MVT::f128 &&
-!useSoftFloat())
https://github.com/uweigand approved this pull request.
LGTM, thanks!
https://github.com/llvm/llvm-project/pull/129170
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uweigand wrote:
> I'd like if this could also make it into a clang 19 release if possible.
I don't think there will be any further clang 19 releases. It should be
backported into clang 20, however.
https://github.com/llvm/llvm-project/pull/129170
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@@ -0,0 +1,27 @@
+//===-- lib/extendhfdf2.c - half -> single conversion -*- C
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
uweigand wrote:
> * However, if I removed the check for COMPILER_RT_HAS_FLOAT16 in the source
> files, it builds. Not sure why/if that is needed there (there is no check for
> it in e.g. extendhfdf2.c), or how it could be set.
This is set if the host compiler used to build compiler-rt supports
uweigand wrote:
> For the missing libfunctions, I see these files in compiler-rt/lib/builtins:
>
> ```
> compiler-rt/lib/builtins/extendhfsf2.c
> compiler-rt/lib/builtins/extendhftf2.c
> compiler-rt/lib/builtins/extendhfxf2.c
> ```
>
> For double, I get undefined reference to `__extendhfdf2' fr
uweigand wrote:
In the SystemZ tests, the variables involved have been deliberated marked
`volatile` to prevent this type of optimization (the tests are supposed to
verify the basic operation of the intrinsics). Does this new transformation
respect `volatile`?
https://github.com/llvm/llvm-pr
uweigand wrote:
/cherry-pick
https://github.com/llvm/llvm-project/commit/ddaa5b3bfb2980f79c6f277608ad33a6efe8d554
https://github.com/llvm/llvm-project/pull/129170
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uweigand wrote:
I think that compiler-rt should provide all six conversion routines (f16<->f32,
f16<->f64, f16<->f128), simply because libgcc has them and GCC-generated code
will use them, and compiler-rt is supposed to be usable as drop-in replacement.
Also, I think LLVM should ideally genera
uweigand wrote:
To clarify about soft-float - we do support `-msoft-float` as a compiler
option, but there is no actual soft-float library provided anywhere; never has
been. The compiler option is still useful in particular for the case of the
Linux kernel: kernel code does not actually have
uweigand wrote:
> So this should already work. If it doesn't, you'll have to debug the build
> process here (e.g. look at preprocessed output to see what's actually going
> on here).
Ah, sorry, now I see what's going on. In this line you added to the cmake
logic:
```
set(s390x_SOURCES ${GENE
@@ -2750,7 +2759,7 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
std::vector ArgElemTypes;
std::vector Args;
llvm::BitVector ResultTypeRequiresCast;
- llvm::BitVector ResultRegIsFlagReg;
+ std::vector ResultRegIsFlagReg;
uweigand wrote:
Agai
@@ -12118,12 +12117,13 @@ void
SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
SDValue CondLHS = getValue(Cond);
EVT VT = CondLHS.getValueType();
SDLoc DL = getCurSDLoc();
+SDValue Cond;
SDValue Or = DAG.getNode(
@@ -2601,7 +2601,7 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
const llvm::ArrayRef ResultRegDests,
const llvm::ArrayRef ResultRegQualTys,
const llvm::BitVector &ResultTypeRequiresCast,
- const llvm::BitVector
@@ -2621,9 +2621,18 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
if ((i < ResultRegIsFlagReg.size()) && ResultRegIsFlagReg[i]) {
// Target must guarantee the Value `Tmp` here is lowered to a boolean
// value.
- llvm::Constant *Two = llvm::Consta
@@ -1228,6 +1238,7 @@ class TargetInfo : public TransferrableTargetInfo,
std::string &/*SuggestedModifier*/) const {
return true;
}
+
uweigand wrote:
This shouldn't be here.
https://github.com/llvm/llvm-project/pull/125970
_
@@ -756,7 +768,11 @@ class SystemZTargetLowering : public TargetLowering {
SDValue combineINT_TO_FP(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
+ std
@@ -8030,7 +8077,431 @@ SDValue SystemZTargetLowering::combineBSWAP(
return SDValue();
}
+// Combine IPM sequence for flag output operands.
+static bool combineSRL_IPM_CCMask(SDValue &CCReg, int &CCValid, int &CCMask) {
+ // Convert CCVal to CCMask and update it along with
@@ -24,6 +24,7 @@
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsS390.h"
+#include "llvm/IR/PatternMatch.h"
uweigand wrote:
Is this really still necessary?
https://github.com/llvm/llvm-project/pull/125970
__
@@ -8113,10 +8583,151 @@ static bool combineCCMask(SDValue &CCReg, int
&CCValid, int &CCMask) {
CCReg = IPM->getOperand(0);
return true;
}
-
uweigand wrote:
These shouldn't be here.
https://github.com/llvm/llvm-project/pull/125970
_
@@ -8113,10 +8583,151 @@ static bool combineCCMask(SDValue &CCReg, int
&CCValid, int &CCMask) {
CCReg = IPM->getOperand(0);
return true;
}
-
return false;
}
+std::optional
+SystemZTargetLowering::combineSELECT_CC_CCIPMMask(SDNode *N,
+
@@ -8030,7 +8077,431 @@ SDValue SystemZTargetLowering::combineBSWAP(
return SDValue();
}
+// Combine IPM sequence for flag output operands.
+static bool combineSRL_IPM_CCMask(SDValue &CCReg, int &CCValid, int &CCMask) {
+ // Convert CCVal to CCMask and update it along with
@@ -2757,6 +2797,21 @@ static unsigned CCMaskForCondCode(ISD::CondCode CC) {
#undef CONV
}
+static unsigned CCMaskForSystemZCCVal(unsigned CC) {
uweigand wrote:
I don't think this is needed, this is simply `1 << (3 - CC)` or something. You
have similar code
@@ -98,6 +98,15 @@ bool SystemZTargetInfo::validateAsmConstraint(
case 'T': // Likewise, plus an index
Info.setAllowsMemory();
return true;
+ case '@':
+// CC condition changes.
+if (StringRef(Name) == "@cc") {
+ Name += 2;
+ Info.setAllowsRegister(
@@ -1188,6 +1190,14 @@ class TargetInfo : public TransferrableTargetInfo,
TiedOperand = N;
// Don't copy Name or constraint string.
}
+
+// CC range can be set by target. SystemZ sets it to 4. It is 2 by default.
uweigand wrote:
Comment is
@@ -8030,7 +8077,431 @@ SDValue SystemZTargetLowering::combineBSWAP(
return SDValue();
}
+// Combine IPM sequence for flag output operands.
+static bool combineSRL_IPM_CCMask(SDValue &CCReg, int &CCValid, int &CCMask) {
+ // Convert CCVal to CCMask and update it along with
uweigand wrote:
> > I see that the LowerOperationWrapper still emits i128 operations. (E.g. you
> > expand a f16->i128 into a f16->f32 and f32->i128) But that routine is
> > called because of the illegal input type i128, so I understand it must not
> > leave any operations with the illegal typ
uweigand wrote:
> Moved the comment "Promoting the result to i64...so use the default
> expansion" that was present in SystemZISelLowering.cpp into this method, but
> don't quite understand it fully. Is this talking about promoting to signed
> i64?
This is about whether we can (and should) im
https://github.com/uweigand approved this pull request.
You might want to re-test after the recent merge of the z17 patch. Otherwise,
this now looks all good to me, a few further enhancement we discussed can be
done as follow-on. Thanks!
https://github.com/llvm/llvm-project/pull/109164
@@ -2,6 +2,16 @@
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; Test f316->i32.
uweigand wrote:
Comment typo.
https://github.com/llvm/llvm-project/pull/109164
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