[clang] [compiler-rt] [llvm] [SystemZ] Add support for half (fp16) (PR #109164)

[Ulrich Weigand via cfe-commits]

================
@@ -6769,11 +6898,20 @@ SystemZTargetLowering::LowerOperationWrapper(SDNode *N,
     break;
   }
   case ISD::BITCAST: {
+    SDLoc DL(N);
     SDValue Src = N->getOperand(0);
-    if (N->getValueType(0) == MVT::i128 && Src.getValueType() == MVT::f128 &&
-        !useSoftFloat()) {
-      SDLoc DL(N);
+    EVT SrcVT = Src.getValueType();
+    EVT ResVT = N->getValueType(0);
+    if (ResVT == MVT::i128 && SrcVT == MVT::f128 && !useSoftFloat())
       Results.push_back(expandBitCastF128ToI128(DAG, Src, DL));
+    else if (SrcVT == MVT::i16 && ResVT == MVT::f16) {
+      SDValue In32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Src);
+      Results.push_back(
+          SDValue(DAG.getMachineNode(SystemZ::LEFR_16, DL, MVT::f16, In32), 
0));
----------------
uweigand wrote:

This unconditionally uses vector instructions.  What if we don't have those?  
Do we need a full BITCAST for all cases?

https://github.com/llvm/llvm-project/pull/109164
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