================
@@ -541,11 +543,26 @@ SystemZTargetLowering::SystemZTargetLowering(const
TargetMachine &TM,
}
// Handle floating-point types.
+ // Promote all f16 operations to float, with some exceptions below.
+ for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
+ setOperationAction(Opc, MVT::f16, Promote);
+ setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
+ for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
+ setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
+ setTruncStoreAction(VT, MVT::f16, Expand);
+ }
+ for (auto Op : {ISD::LOAD, ISD::ATOMIC_LOAD, ISD::STORE, ISD::ATOMIC_STORE})
+ setOperationAction(Op, MVT::f16, Subtarget.hasVector() ? Legal : Custom);
+ setOperationAction(ISD::FP_ROUND, MVT::f16, LibCall);
+ setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, LibCall);
+ if (Subtarget.hasVector()) // f16 <-> i16 bitcasts.
+ setOperationAction(ISD::BITCAST, MVT::i16, Custom);
----------------
uweigand wrote:
Not sure about the whole `BITCAST` story here. `f16` should now be legal
always, whether we have vector support or not (either in VR16 or FP16). That
seems to imply that we'll have to have a `BITCAST` implementation in both cases
too - does it not?
https://github.com/llvm/llvm-project/pull/109164
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