https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/84877
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https://github.com/llvm/llvm-project/pull/84877
>From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 12 Mar 2024 14:28:09 +0800
Subject: [PATCH 1/7] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
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wangpc-pp wrote:
I don't know why spr added so many reviewers... sorry for bothering.
https://github.com/llvm/llvm-project/pull/84877
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https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/90373
Since C++14 has been released for about nine years and most standard
libraries have implemented sized deallocation functions, it's time to
make this feature default again.
This is another try of https://reviews
wangpc-pp wrote:
@dyung Can you help me to comfirm whether the Windows builder is passing now? I
don't have such environment. Thanks in advance!
https://github.com/llvm/llvm-project/pull/90373
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ht
wangpc-pp wrote:
> > > @dyung Can you help me to comfirm whether the Windows builder is passing
> > > now? I don't have such environment. Thanks in advance!
> >
> >
> > Sure, I'll try it on our internal builder and see if it passes and let you
> > know the result.
>
> I can confirm that this
=?utf-8?b?6YOd5bq36L6+?=
Message-ID:
In-Reply-To:
wangpc-pp wrote:
I'd like to see the support of KunMingHu, but please hold this PR and wait for
the finalization of KunMingHu's architecture.
https://github.com/llvm/llvm-project/pull/90392
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https://github.com/wangpc-pp commented:
Do we still need this?
```
def Experimental
: SubtargetFeature<"experimental", "HasExperimental",
"true", "Experimental intrinsics">;
```
https://github.com/llvm/llvm-project/pull/106359
https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/106359
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@@ -664,5 +664,9 @@ def FRM: RISCVReg<0, "frm">;
// Shadow Stack register
def SSP: RISCVReg<0, "ssp">;
-// Dummy VCIX state register
+// Dummy VCIX state register and its register class
def VCIX_STATE : RISCVReg<0, "vcix_state">;
+def : RISCVRegisterClass<[XLenVT], 32
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https://github.com/llvm/llvm-project/pull/97925
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@@ -290,8 +290,24 @@ std::string riscv::getRISCVArch(const llvm::opt::ArgList
&Args,
// 2. Get march (isa string) based on `-mcpu=`
if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
StringRef CPU = A->getValue();
-if (CPU == "native")
+if (CPU == "nat
https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/94352
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wangpc-pp wrote:
Is it a NFC?
https://github.com/llvm/llvm-project/pull/92682
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https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/92644
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wangpc-pp wrote:
I think it's a good rewrite. Added more RISCV guys.
https://github.com/llvm/llvm-project/pull/92682
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https://github.com/wangpc-pp approved this pull request.
LGTM. Thanks!
https://github.com/llvm/llvm-project/pull/91556
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@@ -1554,13 +1554,13 @@
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
// Experimental extensions
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zaamo0p2 -E -dM %s \
+// RUN: %clang --target=riscv32 \
wangpc-pp wrote:
@@ -112,10 +112,10 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZVFBFMIN %s
; RUN: llc -mtriple=ri
https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/92682
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https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/90373
>From fd015302585fc8149811868636cb0da5c422cf7a Mon Sep 17 00:00:00 2001
From: Pengcheng Wang
Date: Fri, 26 Apr 2024 16:59:12 +0800
Subject: [PATCH] [clang] Enable sized deallocation by default in C++14 onwards
wangpc-pp wrote:
Please review this PR as all noticable issues have been fixed I think.
https://github.com/llvm/llvm-project/pull/90373
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https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/90373
>From a18f57e23c0d4fd23647eb2ef610352e402b45f6 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang
Date: Fri, 26 Apr 2024 16:59:12 +0800
Subject: [PATCH] [clang] Enable sized deallocation by default in C++14 onwards
https://github.com/wangpc-pp closed
https://github.com/llvm/llvm-project/pull/90373
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wangpc-pp wrote:
> This one is broken https://lab.llvm.org/buildbot/#/builders/168/builds/20461
The broken case is:
```cpp
void test_allocate_deallocate() {
std::pmr::memory_resource& r1 = *std::pmr::new_delete_resource();
globalMemCounter.reset();
void* ret = r1.allocate(50);
assert(r
wangpc-pp wrote:
> > Based on my rough understanding, this is expected?
>
> What do you mean?
>
> Isn't this test needs to be updated or disabled?
I think this ASAN failure is not caused by this PR because these memorys are
allocated/deallocated by `memory_resource` directly, **there is nothi
wangpc-pp wrote:
Thanks @vitalybuka! After some investigations, I think this PR just uncovered
the existed ASAN problem.
```cpp
#if !defined(__cpp_sized_deallocation) || __cpp_sized_deallocation < 201309L
# define _LIBCPP_HAS_NO_LANGUAGE_SIZED_DEALLOCATION
#endif
#if !defined(_LIBCPP_BUILDING_
wangpc-pp wrote:
Thanks @vitalybuka for fixing the remain issues.
It has been about 2 days since this PR was merged and there is no other issue,
I think we finally make sized deallocation default this time! Cheers!
https://github.com/llvm/llvm-project/pull/90373
@@ -106,6 +106,7 @@ Changes to the RISC-V Backend
* `.balign N, 0`, `.p2align N, 0`, `.align N, 0` in code sections will now fill
the required alignment space with a sequence of `0x0` bytes (the requested
fill value) rather than NOPs.
+* Added Syntacore SCR4 CPUs: ``-mcpu=s
https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/101321
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https://github.com/wangpc-pp approved this pull request.
https://github.com/llvm/llvm-project/pull/98855
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https://github.com/wangpc-pp commented:
I don't think this will be better. We may keep these names so that these code
can be self-explanatory.
https://github.com/llvm/llvm-project/pull/101643
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htt
https://github.com/wangpc-pp approved this pull request.
Make sense to me.
(Do we have a way to test these generated builtins?)
https://github.com/llvm/llvm-project/pull/101646
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@@ -1371,7 +1371,6 @@ def NoConditionalMoveFusion :
Predicate<"!Subtarget->hasConditionalMoveFusion()
def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
"SiFive 7-Series processors">;
-
wangpc-pp wr
@@ -304,6 +304,16 @@
// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs"
// MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d"
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p470 | FileCheck
-check-prefix=MCPU-SIFIVE-P470 %s
+// MCPU-SIFIVE-P470: "-target-cpu" "sifive-
https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/102022
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@@ -45,6 +154,13 @@ defvar SiFiveP400FloatArith = SiFiveP400FEXQ0;
defvar SiFiveP400F2I = SiFiveP400FEXQ0;
def SiFiveP400FloatDiv: ProcResource<1>;
+// Vector pipeline
+def SiFiveP400VEXQ0: ProcResource<1>;
wangpc-pp wrote:
`EXQ0` means `exe
@@ -45,6 +154,13 @@ defvar SiFiveP400FloatArith = SiFiveP400FEXQ0;
defvar SiFiveP400F2I = SiFiveP400FEXQ0;
def SiFiveP400FloatDiv: ProcResource<1>;
+// Vector pipeline
+def SiFiveP400VEXQ0: ProcResource<1>;
wangpc-pp wrote:
So there is 1 vec
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/103709
>From 0330ffdcd0ff0230ef8ba7fac5eff5874ba2e544 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Wed, 14 Aug 2024 15:14:36 +0800
Subject: [PATCH 1/2] [RISCV][MC] Support experimental extensions Zvbc32e and
https://github.com/wangpc-pp closed
https://github.com/llvm/llvm-project/pull/103709
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https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/104736
Add a macro to simplify some codes.
>From d45743a893a44dbb5da75d3dbe40dfbd34c14e71 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Mon, 19 Aug 2024 12:07:00 +0800
Subject: [PATCH] [RISCV] Simplify resers
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/104736
>From d45743a893a44dbb5da75d3dbe40dfbd34c14e71 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Mon, 19 Aug 2024 12:07:00 +0800
Subject: [PATCH 1/2] [RISCV] Simplify reserse fixed regs
Add a macro to simpl
https://github.com/wangpc-pp closed
https://github.com/llvm/llvm-project/pull/104736
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@@ -1571,7 +1571,9 @@ StringRef sys::getHostCPUName() {
#if defined(__linux__)
std::unique_ptr P = getProcCpuinfoContent();
StringRef Content = P ? P->getBuffer() : "";
- return detail::getHostCPUNameForRISCV(Content);
+ StringRef Name = detail::getHostCPUNameForRISCV(Con
wangpc-pp wrote:
> I have no idea about why it corrupts StringMap. Sad :(
>
> ![image](https://private-user-images.githubusercontent.com/15650457/341986439-fd427068-6ca0-4ecb-a340-48c51e5629a6.png?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb2
https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/96465
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https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/96465
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@@ -365,24 +365,30 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
// RV32-ZFHMIN: "-target-feature" "+zfhmin"
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso -### %s \
+// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/96465
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@@ -83,8 +83,14 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
// and other features (ex. mirco architecture feature) from mcpu
if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
StringRef CPU = A->getValue();
-if (CPU == "nat
wangpc-pp wrote:
> Why don’t any of our lit tests that use every intrinsic catch it?
We don't see any error, is it because your downstream added some intrinsics?
https://github.com/llvm/llvm-project/pull/111481
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https://github.com/wangpc-pp approved this pull request.
Make sense to me. It was wrong since when?
https://github.com/llvm/llvm-project/pull/111476
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https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/111466
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https://github.com/wangpc-pp approved this pull request.
LGTM.
I like this change and adding support of paired registers is on my todo list as
well.
https://github.com/llvm/llvm-project/pull/112561
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@@ -276,6 +276,14 @@ foreach i = 0...15 in {
foreach i = 0...63 in
def : SysReg<"pmpaddr"#i, !add(0x3B0, i)>;
+//===--===//
+// Machine Non-Maskable Interrupt Handling
+//===-
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/111668
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@@ -66,6 +66,8 @@ def riscv_sret_glue : SDNode<"RISCVISD::SRET_GLUE", SDTNone,
[SDNPHasChain, SDNPOptInGlue]>;
def riscv_mret_glue : SDNode<"RISCVISD::MRET_GLUE", SDTNone,
[SDNPHasChain, SDNPOptInGlue]>;
+def riscv_mnret
@@ -276,6 +276,14 @@ foreach i = 0...15 in {
foreach i = 0...63 in
def : SysReg<"pmpaddr"#i, !add(0x3B0, i)>;
+//===--===//
+// Machine Non-Maskable Interrupt Handling
+//===-
https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/111481
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@@ -2224,6 +2231,17 @@ bool RISCVTargetLowering::isExtractSubvectorCheap(EVT
ResVT, EVT SrcVT,
return Index == 0 || Index == ResElts;
}
+EVT RISCVTargetLowering::getAsmOperandValueType(const DataLayout &DL, Type *Ty,
+bool All
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/112983
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https://github.com/wangpc-pp commented:
Thanks! I just had a detailed look. Given that you have explained almost all
the code detailedly, I think this PR looks great to me!
Just some overall comments:
1. I personally like your proposal of adding new constraints, but we still need
the agreement
https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/113618
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@@ -26,5 +26,5 @@ entry:
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
declare @llvm.masked.gather.nxv4i32.nxv4p0(, i32 immarg, , ) #1
-attributes #0 = {
"target-features"="+64bit,+d,+f,+relax,+v,+xsifivecdiscarddlone,+zicsr,+zve32f,+zve32x,+zve
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/113618
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https://github.com/wangpc-pp approved this pull request.
LGTM.
(And it's time to mask RV[A|B|M]23 as non-experimental now?)
https://github.com/llvm/llvm-project/pull/113619
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https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/113619
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https://github.com/wangpc-pp approved this pull request.
Cheers! LGTM!
https://github.com/llvm/llvm-project/pull/113918
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https://github.com/wangpc-pp approved this pull request.
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https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/113758
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https://github.com/wangpc-pp commented:
Please update ReleaseNotes.
https://github.com/llvm/llvm-project/pull/113758
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https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/113826
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https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/113820
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https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/113823
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https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/115100
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@@ -104,6 +104,62 @@
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-max |
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-MAX %s
// MTUNE-SYNTACORE-SCR1-MAX: "-tune-cpu" "syntacore-scr1-max"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=tt-ascalo
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/115100
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@@ -21351,6 +21372,17 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
unsigned NumParts, MVT PartVT, std::optional CC) const {
bool IsABIRegCopy = CC.has_value();
EVT ValueVT = Val.getValueType();
+
+ if (ValueVT == (Subtarget.is64Bit() ? MVT::i128 : MVT::i64
https://github.com/wangpc-pp approved this pull request.
Cheers! It seems using `untyped` saves some lines as well!
LGTM with nits.
https://github.com/llvm/llvm-project/pull/112983
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@@ -74,7 +74,10 @@ def sub_gpr_odd : SubRegIndex<32, 32> {
}
} // Namespace = "RISCV"
-// Integer registers
+//===--===//
wangpc-pp wrote:
Please land these comment/style changes first.
htt
@@ -486,3 +486,15 @@ bool RISCVTargetInfo::validateCpuSupports(StringRef
Feature) const {
bool RISCVTargetInfo::isValidFeatureName(StringRef Name) const {
return llvm::RISCVISAInfo::isSupportedExtensionFeature(Name);
}
+
+bool RISCVTargetInfo::validateGlobalRegisterVariable(
https://github.com/wangpc-pp approved this pull request.
https://github.com/llvm/llvm-project/pull/109889
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https://github.com/wangpc-pp approved this pull request.
https://github.com/llvm/llvm-project/pull/109390
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@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/117356
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https://github.com/wangpc-pp closed
https://github.com/llvm/llvm-project/pull/116231
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https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/116231
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https://github.com/wangpc-pp commented:
Add ReleaseNote to Clang?
https://github.com/llvm/llvm-project/pull/116597
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https://github.com/wangpc-pp approved this pull request.
LGTM. Nice cleanup.
https://github.com/llvm/llvm-project/pull/121024
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https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/120936
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https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/96283
>From 4b597ebf69de59d62e5587a27cedf2b12e831763 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 21 Jun 2024 16:09:13 +0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=
wangpc-pp wrote:
Ping for comments. :-)
https://github.com/llvm/llvm-project/pull/96283
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https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/96283
>From 4b597ebf69de59d62e5587a27cedf2b12e831763 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 21 Jun 2024 16:09:13 +0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
@@ -0,0 +1,494 @@
+//===-- RISCVSchedGenericOOO.td - Generic O3 Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/120712
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@@ -0,0 +1,494 @@
+//===-- RISCVSchedGenericOOO.td - Generic O3 Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -623,13 +623,37 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
}
}
+ auto checkVsetvl = [&](unsigned SEWOffset,
+unsigned LMULOffset) -> bool {
+const FunctionDecl *FD = SemaRef.getCurFunctionDecl();
+
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/126064
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