[clang] [llvm] [RISCV] Remove experimental from Zacas. (PR #83195)

topperc wrote: > LGTM. > > Will it be in LLVM 18? Or we need more time to examine its robustness? The bar for LLVM 18 is pretty high at this point. I doubt this qualifies. https://github.com/llvm/llvm-project/pull/83195 ___ cfe-commits mailing list c

[clang] [llvm] [RISCV] Remove experimental from Zacas. (PR #83195)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/83195 >From 8ed68475b43008d9c7baff7f275026cc7ada5993 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 27 Feb 2024 14:01:52 -0800 Subject: [PATCH 1/2] [RISCV] Remove experimental from Zacas. Document that we don'

[clang] [llvm] [RISCV] Remove experimental from Zacas. (PR #83195)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/83195 >From 8ed68475b43008d9c7baff7f275026cc7ada5993 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 27 Feb 2024 14:01:52 -0800 Subject: [PATCH 1/3] [RISCV] Remove experimental from Zacas. Document that we don'

[clang] [llvm] [RISCV] Remove experimental from Zacas. (PR #83195)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/83195 >From 8ed68475b43008d9c7baff7f275026cc7ada5993 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 27 Feb 2024 14:01:52 -0800 Subject: [PATCH 1/4] [RISCV] Remove experimental from Zacas. Document that we don'

[clang] [llvm] [RISCV] Remove experimental from Zacas. (PR #83195)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/83195 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [lld] [llvm] [X86] Use generic CPU tuning when tune-cpu is empty (PR #83631)

topperc wrote: > This is a turbulent change to both upstream and downstream tests without any > profit as far as I can tell. > > I did a similar change for 64-bit a few years ago: > https://reviews.llvm.org/D129647 > > In comparison, this patch is not to solve a specific problem. It should no

[clang] [llvm] [RISCV] Add support of Sscofpmf (PR #83831)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/83831 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/83896 These were in LLVM 17 but removed from LLVM 18 due to an incorrect extension name being used. This restores them with new extension names that match SiFive's downstream compiler. The extension name has been use

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/83896 >From 9434f834c4d48559aeec94403c927f48b15763e3 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 4 Mar 2024 11:24:34 -0800 Subject: [PATCH 1/2] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instru

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/83896 >From 9434f834c4d48559aeec94403c927f48b15763e3 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 4 Mar 2024 11:24:34 -0800 Subject: [PATCH 1/3] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instru

[clang] 7dc7fc0 - Recommit "[RISCV] Relax march string order constraint (#78120)"

Author: Piyou Chen Date: 2024-01-30T10:24:14-08:00 New Revision: 7dc7fc08430b824ca16d3b22542ba73bc4d17881 URL: https://github.com/llvm/llvm-project/commit/7dc7fc08430b824ca16d3b22542ba73bc4d17881 DIFF: https://github.com/llvm/llvm-project/commit/7dc7fc08430b824ca16d3b22542ba73bc4d17881.diff LO

[clang] [llvm] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)

@@ -145,6 +145,7 @@ // CHECK-NOT: __riscv_zacas {{.*$}} // CHECK-NOT: __riscv_zalrsc {{.*$}} // CHECK-NOT: __riscv_zcmop {{.*$}} +// CHECK-NOT: __riscv_zalasr {{.*$}} topperc wrote: this list is roughly in alphabetical order, can you alphabetize zalasr above

[clang] [llvm] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)

@@ -0,0 +1,70 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zalasr -riscv-no-aliases -show-encoding \ topperc wrote: It's not very obvious from the test names, but I think the convention for the `-valid.s` tests is usually that the `rv32` test cont

[clang] [llvm] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/79911 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][Clang] Added builtin support for experimental Zimop extension (PR #79971)

@@ -89,5 +89,13 @@ TARGET_BUILTIN(__builtin_riscv_sm3p1, "UiUi", "nc", "zksh") TARGET_BUILTIN(__builtin_riscv_ntl_load, "v.", "t", "zihintntl") TARGET_BUILTIN(__builtin_riscv_ntl_store, "v.", "t", "zihintntl") +// Zimop extension +TARGET_BUILTIN(__builtin_riscv_mopr_32, "UiUiU

[clang] [llvm] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)

@@ -106,9 +112,15 @@ static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB, CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; })) return; + const RISCVInstrInfo *TII = STI.getInstrInfo(); + if (!STI.hasForcedSWShadowStack() && +

[llvm] [clang] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)

@@ -51,9 +51,15 @@ static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB, CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; })) return; + const RISCVInstrInfo *TII = STI.getInstrInfo(); + if (!STI.hasForcedSWShadowStack() && +

[clang] [Clang][RISCV] Add assumptions to vsetvli/vsetvlimax (PR #79975)

topperc wrote: I'm concerned that llvm.assume is handled differently than a branch to unreachable in the middle end. Have you tested that these assumes have the intended effect? https://github.com/llvm/llvm-project/pull/79975 ___ cfe-commits mailing

[llvm] [clang] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

topperc wrote: Ping https://github.com/llvm/llvm-project/pull/79399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

@@ -764,6 +771,62 @@ def FeatureStdExtSmepmp : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", "'Smepmp' (Enhanced Physical Memory Protection)", []>; +def FeatureStdExtSsccptr +: SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true", +

[llvm] [clang] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

@@ -764,6 +771,62 @@ def FeatureStdExtSmepmp : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", "'Smepmp' (Enhanced Physical Memory Protection)", []>; +def FeatureStdExtSsccptr +: SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true", +

[llvm] [clang] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

@@ -764,6 +771,62 @@ def FeatureStdExtSmepmp : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", "'Smepmp' (Enhanced Physical Memory Protection)", []>; +def FeatureStdExtSsccptr +: SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true", +

[clang] [llvm] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/79399 >From 1d29443b30f6d6db2dbba0f78e8347ea126321e7 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 24 Jan 2024 18:39:07 -0800 Subject: [PATCH 1/7] [RISCV] Add many of the S extensions mentioned in the profile

[clang] [llvm] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/79399 >From 1d29443b30f6d6db2dbba0f78e8347ea126321e7 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 24 Jan 2024 18:39:07 -0800 Subject: [PATCH 1/8] [RISCV] Add many of the S extensions mentioned in the profile

[clang] [llvm] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/79399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add support for RISC-V Pointer Masking (PR #79929)

@@ -797,6 +797,40 @@ def FeatureStdExtSvpbmt : SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true", "'Svpbmt' (Page-Based Memory Types)">; +// Pointer Masking extensions + +// A supervisor-level extension that provides pointer masking for the next

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/76548 >From 3dfa00b0dab1820d1d8692ea91e98b29c9f8b627 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 28 Dec 2023 16:49:03 -0800 Subject: [PATCH 1/2] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predica

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/76548 >From 3dfa00b0dab1820d1d8692ea91e98b29c9f8b627 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 28 Dec 2023 16:49:03 -0800 Subject: [PATCH 1/3] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predica

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

topperc wrote: > Generalising this code makes sense, 16 should never have been hardcoded here. > > Is it possible to add a test for the case where the predicate type is not > ``? I rebased, which picked up more tests that are affected for RISC-V. This also pointed out that I missed very simil

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

@@ -2136,14 +2136,16 @@ Value *ScalarExprEmitter::VisitCastExpr(CastExpr *CE) { // bitcast. if (const auto *FixedSrc = dyn_cast(SrcTy)) { if (const auto *ScalableDst = dyn_cast(DstTy)) { -// If we are casting a fixed i8 vector to a scalable 16 x i1 predic

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

@@ -70,13 +70,17 @@ fixed_float64m1_t call_float64_ff(fixed_float64m1_t op1, fixed_float64m1_t op2) // CHECK-LABEL: @call_bool1_ff( // CHECK-NEXT: entry: -// CHECK-NEXT:[[SAVED_VALUE4:%.*]] = alloca , align 8 -// CHECK-NEXT:[[RETVAL_COERCE:%.*]] = alloca , align 8 -/

[clang] [Headers][X86] Editorial fixes to ia32intrin.h descriptions (PR #80490)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/80490 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add support for RISC-V Pointer Masking (PR #79929)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/79929 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][clang] Add Zvfbfwma C intrinsics support (PR #79615)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/79615 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add support for RISC-V Pointer Masking (PR #79929)

topperc wrote: Looks like we missed updating llvm/test/MC/RISCV/attribute-arch.s https://github.com/llvm/llvm-project/pull/79929 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add Ssqosid support to -march. (PR #80747)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/80747 None >From a92d11432df57ad7172d80157e794ebec63b3410 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 5 Feb 2024 13:46:32 -0800 Subject: [PATCH] [RISCV] Add Ssqosid support to -march. --- clang/test/Prepr

[clang] [llvm] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)

topperc wrote: Will https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/417 be implemented in a separate patch? https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bi

[clang] [RISCV] Add -march string as Module metadata in IR. (PR #80760)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/80760 In an LTO build, we don't set the ELF attributes to indicate what extensions were compiled with. The target CPU/Attrs in RISCVTargetMachine do not get set for an LTO build. Each function gets a target-cpu/featur

[clang] [RISCV] Add -march string as Module metadata in IR. (PR #80760)

topperc wrote: > I'm surprised only 1 test file needed the metadata updated as a result of > this change. Maybe other tests are better about using regexes to hide the numbers? https://github.com/llvm/llvm-project/pull/80760 ___ cfe-commits mailing li

[llvm] [clang] [RISCV] Add Ssqosid support to -march. (PR #80747)

@@ -1612,6 +1613,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s // CHECK-SUPM-EXT: __riscv_supm 8000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_ssqosid1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-p

[llvm] [clang] [RISCV][MC] Add experimental support of Zaamo and Zalrsc (PR #78970)

@@ -168,6 +168,18 @@ def FeatureStdExtZa64rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs", "true", def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs", "true", "'Za128rs' (Reservation Set Size of at Most 128

[clang] [llvm] [RISCV][MC] Add experimental support of Zaamo and Zalrsc (PR #78970)

@@ -168,6 +168,18 @@ def FeatureStdExtZa64rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs", "true", def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs", "true", "'Za128rs' (Reservation Set Size of at Most 128

[llvm] [clang] [RISCV][MC] Add experimental support of Zaamo and Zalrsc (PR #78970)

@@ -176,6 +188,18 @@ def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">, "'Zacas' (Atomic Compare-And-Swap Instructions)">; def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">; +def FeatureStdExtZalrsc +: SubtargetFeatu

[llvm] [clang] [clang-tools-extra] [X86] Use RORX over SHR imm (PR #77964)

@@ -4212,6 +4213,96 @@ MachineSDNode *X86DAGToDAGISel::emitPCMPESTR(unsigned ROpc, unsigned MOpc, return CNode; } +// When the consumer of a right shift (arithmetic or logical) wouldn't notice +// the difference if the instruction was a rotate right instead (because the +//

[llvm] [clang] [RISCV][MC] Add experimental support of Zaamo and Zalrsc (PR #78970)

@@ -1307,6 +1309,13 @@ // CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}} // Experimental extensions +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zaamo0p1 -x c -E -dM %s \ topperc wrote: It's not working. It failed the a

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

@@ -2000,6 +2000,14 @@ bool RISCVTargetLowering::shouldSinkOperands( if (!I->getType()->isVectorTy() || !Subtarget.hasVInstructions()) return false; + // Don't sink splat operands if the target prefers it. Some targets requires topperc wrote: These sho

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/79015 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -416,8 +416,10 @@ class RVVIntrinsic { RVVTypePtr getOutputType() const { return OutputType; } const RVVTypes &getInputTypes() const { return InputTypes; } llvm::StringRef getBuiltinName() const { return BuiltinName; } - llvm::StringRef getName() const { return Name;

[llvm] [clang] [RISCV] Relax march string order constraint (PR #78120)

@@ -695,6 +696,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) { return std::move(ISAInfo); } +static Error splitExtsByUnderscore(StringRef Exts, + std::vector &SplitExts) { + SmallVector Split; + if (Exts.empty()) +retu

[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)

@@ -695,6 +696,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) { return std::move(ISAInfo); } +static Error splitExtsByUnderscore(StringRef Exts, + std::vector &SplitExts) { + SmallVector Split; + if (Exts.empty()) +retu

[clang-tools-extra] [llvm] [clang] [compiler-rt] [flang] [RISCV][MC] Add experimental support of Zaamo and Zalrsc (PR #78970)

@@ -170,7 +170,7 @@ xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction # Instruction not in the base ISA div a4, ra, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'M' (Integer Multiplication and Division){{$}} -amomaxu.w s5, s4,

[clang] [Docs] Mention RISC-V in the introductory paragraph in ShadowCallStack.rst. (PR #79241)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/79241 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/79399 This is a good portion of the extensions mentioned in the RVA23 profile here https://github.com/riscv/riscv-profiles/blob/main/rva23-profile.adoc I don't believe these add any new CSRs. Sstc does add new CSRs, b

[llvm] [compiler-rt] [flang] [clang] [clang-tools-extra] [RISCV][MC] Add experimental support of Zaamo and Zalrsc (PR #78970)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/78970 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Support __riscv_v_fixed_vlen for vbool types. (PR #76551)

topperc wrote: ping https://github.com/llvm/llvm-project/pull/76551 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/79399 >From f913962bfe113d2cd6be82d8fc6df479891a7a71 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 24 Jan 2024 18:39:07 -0800 Subject: [PATCH 1/2] [RISCV] Add many of the S extensions mentioned in the profile

[clang] [llvm] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/79399 >From f913962bfe113d2cd6be82d8fc6df479891a7a71 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 24 Jan 2024 18:39:07 -0800 Subject: [PATCH 1/3] [RISCV] Add many of the S extensions mentioned in the profile

[clang] [llvm] [RISCV][SiFive] Reduce intrinsics of SiFive VCIX extension (PR #79407)

@@ -10,7 +10,8 @@ // CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT:call void @llvm.riscv.sf.vc.x.se.e64m1.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT:[[CONV:%.*]] = trunc i64 [[RS1

[clang] [llvm] [RISCV][SiFive] Reduce intrinsics of SiFive VCIX extension (PR #79407)

@@ -817,6 +817,66 @@ bool RISCVDAGToDAGISel::tryIndexedLoad(SDNode *Node) { return true; } +void RISCVDAGToDAGISel::selectSF_VC_X_SE(SDNode *Node) { + if (!Subtarget->hasVInstructions()) +return; + + assert(Node->getOpcode() == ISD::INTRINSIC_VOID && "Unexpected opcode

[llvm] [clang] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

@@ -269,6 +286,142 @@ // CHECK-M-EXT: __riscv_mul 1 // CHECK-M-EXT: __riscv_muldiv 1 +// RUN: %clang --target=riscv32-unknown-linux-gnu \ topperc wrote: Should I just reformat this file? https://github.com/llvm/llvm-project/pull/79399 ___

[clang] [RISCV] Reformat riscv-target-features.c. NFC (PR #79409)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/79409 Indent line continuations by 2 spaces. Drop -x c >From 32dcc4d617811a42285958637274c4fb995742c4 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 24 Jan 2024 22:33:37 -0800 Subject: [PATCH] [RISCV] Reformat

[llvm] [clang] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/79399 >From f913962bfe113d2cd6be82d8fc6df479891a7a71 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 24 Jan 2024 18:39:07 -0800 Subject: [PATCH 1/4] [RISCV] Add many of the S extensions mentioned in the profile

[llvm] [clang] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/79399 >From f913962bfe113d2cd6be82d8fc6df479891a7a71 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 24 Jan 2024 18:39:07 -0800 Subject: [PATCH 1/5] [RISCV] Add many of the S extensions mentioned in the profile

[clang] [RISCV] Reformat riscv-target-features.c. NFC (PR #79409)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/79409 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][SiFive] Reduce intrinsics of SiFive VCIX extension (PR #79407)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/79407 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang-tools-extra] [llvm] [clang] [RISCV] Relax march string order constraint (PR #78120)

@@ -793,153 +887,69 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, Minor = Version->Minor; } -ISAInfo->addExtension(StringRef(&Baseline, 1), {Major, Minor}); +// Postpone AddExtension until end of this function +SeenEx

[clang] [llvm] [clang-tools-extra] [RISCV] Relax march string order constraint (PR #78120)

@@ -793,153 +887,69 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, Minor = Version->Minor; } -ISAInfo->addExtension(StringRef(&Baseline, 1), {Major, Minor}); +// Postpone AddExtension until end of this function +SeenEx

[llvm] [clang-tools-extra] [clang] [RISCV] Relax march string order constraint (PR #78120)

@@ -793,153 +887,69 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, Minor = Version->Minor; } -ISAInfo->addExtension(StringRef(&Baseline, 1), {Major, Minor}); +// Postpone AddExtension until end of this function +SeenEx

[clang] [RISCV] Support __riscv_v_fixed_vlen for vbool types. (PR #76551)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/76551 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add missing dependency check for Zvkb (PR #79467)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/79467 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] 51b25ba - Revert "[RISCV] Support __riscv_v_fixed_vlen for vbool types. (#76551)"

Author: Craig Topper Date: 2024-01-25T09:38:11-08:00 New Revision: 51b25bad5e53d5be07b5162e4cebcb7d49a422e7 URL: https://github.com/llvm/llvm-project/commit/51b25bad5e53d5be07b5162e4cebcb7d49a422e7 DIFF: https://github.com/llvm/llvm-project/commit/51b25bad5e53d5be07b5162e4cebcb7d49a422e7.diff

[clang] [RISCV] Support __riscv_v_fixed_vlen for vbool types. (PR #76551)

topperc wrote: > Breaks tests: http://45.33.8.238/linux/129101/step_7.txt Reverted at 51b25bad5e53d5be07b5162e4cebcb7d49a422e7 https://github.com/llvm/llvm-project/pull/76551 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.o

[clang] c92ad41 - Recommit "[RISCV] Support __riscv_v_fixed_vlen for vbool types. (#76551)"

Author: Craig Topper Date: 2024-01-25T10:20:29-08:00 New Revision: c92ad411f2f94d8521cd18abcb37285f9a390ecb URL: https://github.com/llvm/llvm-project/commit/c92ad411f2f94d8521cd18abcb37285f9a390ecb DIFF: https://github.com/llvm/llvm-project/commit/c92ad411f2f94d8521cd18abcb37285f9a390ecb.diff

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -464,7 +466,8 @@ void RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR, bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult &LR, IdentifierInfo *II,

[llvm] [clang] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #69685)

@@ -20506,6 +20506,15 @@ unsigned RISCVTargetLowering::getCustomCtpopCost(EVT VT, return isCtpopFast(VT) ? 0 : 1; } +bool RISCVTargetLowering::shouldInsertFencesForAtomic( +const Instruction *I) const { + if (Subtarget.hasStdExtZalasr()) { +return false; + } else

[clang] [llvm] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #69685)

@@ -228,6 +228,9 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zacas`` LLVM implements the `1.0-rc1 draft specification `_. +``experimental-zalasr`` + LLVM imp

[llvm] [clang] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #69685)

@@ -0,0 +1,98 @@ +//===-- RISCVInstrInfoZalasr.td - RISC-V 'Zalasr' instructions ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Ident

[llvm] [clang] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #69685)

@@ -797,6 +797,13 @@ def FeatureStdExtSvpbmt : SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true", "'Svpbmt' (Page-Based Memory Types)">; +def FeatureStdExtZalasr +: SubtargetFeature<"experimental-zalasr", "HasStdExtZalasr", "true", +

[llvm] [clang] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #69685)

@@ -1120,6 +1121,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s // CHECK-SMEPMP-EXT: __riscv_smepmp 100{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zalasr1p0 -x c -E -dM %s \ topperc

[clang] [llvm] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #69685)

@@ -105,22 +105,63 @@ defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">, // Pseudo-instructions and codegen patterns //===--===// +// An atomic load operation that does not need either acquire or r

[llvm] [clang] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #69685)

@@ -105,22 +105,63 @@ defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">, // Pseudo-instructions and codegen patterns //===--===// +// An atomic load operation that does not need either acquire or r

[clang] [llvm] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #69685)

@@ -105,22 +105,63 @@ defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">, // Pseudo-instructions and codegen patterns //===--===// +// An atomic load operation that does not need either acquire or r

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/77487 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Relax march string order constraint (PR #78120)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/78120 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] eeddfec - [Docs] Fix documentation build.

Author: Craig Topper Date: 2024-01-25T19:20:49-08:00 New Revision: eeddfec8c9dc91e3d723a3d8ec3fb108972e031d URL: https://github.com/llvm/llvm-project/commit/eeddfec8c9dc91e3d723a3d8ec3fb108972e031d DIFF: https://github.com/llvm/llvm-project/commit/eeddfec8c9dc91e3d723a3d8ec3fb108972e031d.diff

[clang] [Clang][RISCV][RVV Intrinsic] Fix codegen redundant intrinsic names (PR #77889)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/77889 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Forward --no-relax option to linker for RISC-V (PR #76432)

topperc wrote: Do you need someone to commit this? https://github.com/llvm/llvm-project/pull/76432 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Forward --no-relax option to linker for RISC-V (PR #76432)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/76432 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Relax march string order constraint (PR #78120)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/78120 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)

@@ -0,0 +1,66 @@ +//===-- RISCVInstrInfoZalasr.td - RISC-V 'Zalasr' instructions ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Ident

[clang] [llvm] [clang-tools-extra] [RISCV][ISel] Add ISel support for experimental Zimop extension (PR #77089)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/77089 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)

@@ -0,0 +1,66 @@ +//===-- RISCVInstrInfoZalasr.td - RISC-V 'Zalasr' instructions ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Ident

[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/79618 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][clang] Add Zvfbfwma C intrinsics support (PR #79615)

@@ -1730,12 +1730,26 @@ let ManualCodegen = [{ defm vfwnmacc : RVVFloatingWidenTerBuiltinSetRoundingMode; defm vfwmsac : RVVFloatingWidenTerBuiltinSetRoundingMode; defm vfwnmsac : RVVFloatingWidenTerBuiltinSetRoundingMode; + +// Vector BF16 widening multiply-ac

[clang] [llvm] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)

@@ -0,0 +1,66 @@ +//===-- RISCVInstrInfoZalasr.td - RISC-V 'Zalasr' instructions ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Ident

[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)

@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in { def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">; def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">; } + +// Zvfbfmin - Vector convert BF16 to FP32 +let Log2LMUL = [-

[llvm] [clang] riscv vector cc (PR #77560)

@@ -5400,6 +5400,16 @@ for clang builtin functions. }]; } +def RISCVVectorCCDocs : Documentation { + let Category = DocCatCallingConvs; + let Content = [{ +The ``riscv_vector_cc`` attribute can be applied to a function. It preserves 15 +registers namely, v1-v7 and v24-v31 as

[llvm] [clang] riscv vector cc (PR #77560)

@@ -24,6 +24,19 @@ def CSR_ILP32D_LP64D : CalleeSavedRegs<(add CSR_ILP32_LP64, F8_D, F9_D, (sequence "F%u_D", 18, 27))>; +defvar CSR_V = (add (sequence "V%u", 1, 7), (sequence "V%u", 24, 31), + V2M2, V4M2, V6M2, V24M2, V26M2, V28M

[clang] [llvm] riscv vector cc (PR #77560)

@@ -1416,14 +1560,46 @@ bool RISCVFrameLowering::restoreCalleeSavedRegisters( // first in the epilogue. It increases the opportunity to avoid the // load-to-use data hazard between loading RA and return by RA. // loadRegFromStackSlot can insert multiple instructions. + /

[clang] [llvm] riscv vector cc (PR #77560)

@@ -1416,14 +1560,46 @@ bool RISCVFrameLowering::restoreCalleeSavedRegisters( // first in the epilogue. It increases the opportunity to avoid the // load-to-use data hazard between loading RA and return by RA. // loadRegFromStackSlot can insert multiple instructions. + /

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