================ @@ -1416,14 +1560,46 @@ bool RISCVFrameLowering::restoreCalleeSavedRegisters( // first in the epilogue. It increases the opportunity to avoid the // load-to-use data hazard between loading RA and return by RA. // loadRegFromStackSlot can insert multiple instructions. + // + // + // We first change the restore order for scalar and vector + // callee-saved registers as the layout shown below: + // + // Epilog restore order (original): + // ---------------------------- + // RVV objects + // ---------------------------- + // Callee-saved regs(scalar) + // Callee-saved regs(vector) + // ---------------------------- + // + // Epilog restore order (after): + // ---------------------------- + // RVV objects + // ---------------------------- + // Callee-saved regs(vector) + // Callee-saved regs(scalar) + // ---------------------------- + // + // So that it is able to put all vector registers which need + // to be restored together. The return address will be restored + // first in the scalar regs. It increases the opportunity to avoid the ---------------- topperc wrote:
Part of this paragraph is identical to the paragraph at on line 1562. https://github.com/llvm/llvm-project/pull/77560 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
