[clang] [RISCV] Support __riscv_v_fixed_vlen for vbool types. (PR #76551)

topperc wrote: CC @ita-sc https://github.com/llvm/llvm-project/pull/76551 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Support __riscv_v_fixed_vlen for vbool types. (PR #76551)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/76551 >From 4e651e382ef68ae3f9ff7c9f9059ea1a1bddf892 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 28 Dec 2023 16:14:32 -0800 Subject: [PATCH 1/2] [RISCV] Support __riscv_v_fixed_vlen for vbool types. This ad

[clang] [Clang][RISCV] bfloat uses 'y' instead of 'b' (PR #76575)

topperc wrote: > The 'b' character is specified to use 'b'. Was this sentence supposed to say `bool`? https://github.com/llvm/llvm-project/pull/76575 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listi

[clang] [Clang][RISCV] bfloat uses 'y' instead of 'b' (PR #76575)

https://github.com/topperc commented: LGTM other than the comment about the commit message https://github.com/llvm/llvm-project/pull/76575 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commi

[clang] [Clang][RISCV] bfloat uses 'y' instead of 'b' (PR #76575)

https://github.com/topperc approved this pull request. LGTM other than the comment about the commit message https://github.com/llvm/llvm-project/pull/76575 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/l

[llvm] [clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/66043 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

topperc wrote: What was the last bit of discussion on the phabricator review? I can no longer access it. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/lis

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -0,0 +1,221 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv64 -target-abi lp64e -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV64I-LP64E-FPELIM %s +; RUN: llc -mtriple=riscv64 -target-abi lp64e -ve

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -499,7 +514,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, if (int LibCallRegs = getLibCallID(MF, MFI.getCalleeSavedInfo()) + 1) { // Calculate the size of the frame managed by the libcall. The libcalls are // implemented such that the stack will a

[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -0,0 +1,2556 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -target-abi ilp32e -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=ILP32E-FPELIM %s +; RUN: llc -mtriple=riscv32 -target-abi ilp32e -fram

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -17134,30 +17133,64 @@ static const MCPhysReg ArgVRM4s[] = {RISCV::V8M4, RISCV::V12M4, RISCV::V16M4, RISCV::V20M4}; static const MCPhysReg ArgVRM8s[] = {RISCV::V8M8, RISCV::V16M8}; -ArrayRef RISCV::getArgGPRs() { - static const MCPhysR

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -68,6 +68,11 @@ ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, TargetABI = ABI_Unknown; } + if ((TargetABI == RISCVABI::ABI::ABI_ILP32E || + (TargetABI == ABI_Unknown && IsRVE && !IsRV64)) && + FeatureBits[RISCV::FeatureStdExtD])

[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -285,13 +286,16 @@ StringRef riscv::getRISCVArch(const llvm::opt::ArgList &Args, // 3. Choose a default based on `-mabi=` // // ilp32e -> rv32e + // lp64e -> rv64e // ilp32 | ilp32f | ilp32d -> rv32imafdc // lp64 | lp64f | lp64d -> rv64imafdc if (const Arg *

[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -109,6 +115,11 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const { // beginning with 'x0' for instructions that take register pairs. markSuperRegs(Reserved, RISCV::DUMMY_REG_PAIR_WITH_X0); + // There are only 16 GPRs for RVE. + if (STI.

[clang] [llvm] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)

@@ -57,11 +57,12 @@ compiled application or the operating system. Integrating the runtime into the operating system should be preferred since otherwise all thread creation and destruction would need to be intercepted by the application. -The instrumentation makes use of the p

[clang] [llvm] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)

topperc wrote: How is unwinding handled? The software shadow stack documentation says this > Special unwind information is required on functions that are compiled with > ShadowCallStack and that may be unwound, i.e. functions compiled with > -fexceptions (which is the default in C++). Some unw

[clang] [clang-tools-extra] [llvm] [RISCV] Support Global Dynamic TLSDESC in the RISC-V backend (PR #66915)

@@ -71,6 +71,18 @@ enum Fixups { // Used to generate an R_RISCV_ALIGN relocation, which indicates the linker // should fixup the alignment after linker relaxation. fixup_riscv_align, + // 20-bit fixup corresponding to %tlsdesc_hi(foo) for instructions like + // auipc +

[llvm] [clang] [RISCV] Add B extension (PR #76893)

topperc wrote: > I would suggest set it as 0.1 rather than 1.0, and I gonna to ask Ved to add > version info as well... Then also needs to move behind -menable-experimental-extensions. https://github.com/llvm/llvm-project/pull/76893 ___ cfe-commits m

[clang] [llvm] [RISCV] Add B extension (PR #76893)

topperc wrote: > Thanks! > > > > If someone sets zba_zbb_zbs, should b be inferred? > > > Yes, but it will break `-march=rv64i_zba_zbb_zbs -fno-integrated-as` with versions of the external assembler that don't know about B. We'll infer B and pass it to the assembler -march. https://gith

[clang] 45651c3 - [RISCV] Fix indentation in riscv_sifive_vector.td. NFC

Author: Craig Topper Date: 2024-01-04T11:56:38-08:00 New Revision: 45651c357ae4e39a115bae6a936151b1741abf70 URL: https://github.com/llvm/llvm-project/commit/45651c357ae4e39a115bae6a936151b1741abf70 DIFF: https://github.com/llvm/llvm-project/commit/45651c357ae4e39a115bae6a936151b1741abf70.diff

[clang] [RISCV] Fix collectNonISAExtFeature returning negative extension features (PR #76962)

@@ -237,22 +237,15 @@ ArrayRef RISCVTargetInfo::getTargetBuiltins() const { static std::vector collectNonISAExtFeature(ArrayRef FeaturesNeedOverride, int XLen) { - auto ParseResult = - llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesNeedOverride); - - if (!ParseResult)

[llvm] [clang] [RISCV] Deduplicate RISCVISAInfo::toFeatures/toFeatureVector. NFC (PR #76942)

@@ -466,35 +466,37 @@ bool RISCVISAInfo::compareExtension(const std::string &LHS, return LHS < RHS; } -void RISCVISAInfo::toFeatures( -std::vector &Features, -llvm::function_ref StrAlloc, -bool AddAllExtensions) const { +std::vector RISCVISAInfo::toFeatures(bool

[clang] [llvm] [RISCV] Deduplicate RISCVISAInfo::toFeatures/toFeatureVector. NFC (PR #76942)

@@ -42,9 +42,9 @@ static bool getArchFeatures(const Driver &D, StringRef Arch, return false; } - (*ISAInfo)->toFeatures( - Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); }, - /*AddAllExtensions=*/true); + for (std::string &Str : (*ISAIn

[llvm] [clang] [clang-tools-extra] DAG: Implement promotion for strict_fp_round (PR #74332)

@@ -2621,6 +2642,29 @@ SDValue DAGTypeLegalizer::PromoteFloatRes_FP_ROUND(SDNode *N) { return DAG.getNode(GetPromotionOpcode(VT, NVT), DL, NVT, Round); } +// Explicit operation to reduce precision. Reduce the value to half precision +// and promote it back to the legal typ

[clang] [Clang][Sema] Print more static_assert exprs (PR #74852)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/74852 >From f281d34a51f662c934f158e4770774b0dc3588a2 Mon Sep 17 00:00:00 2001 From: Seth Pellegrino Date: Thu, 7 Dec 2023 08:45:51 -0800 Subject: [PATCH 1/4] [Clang][Sema] Print more static_assert exprs This change in

[clang] [llvm] [clang-tools-extra] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)

@@ -933,6 +933,14 @@ X86 Support - Support ISA of ``AVX10.1``. - ``-march=pantherlake`` and ``-march=clearwaterforest`` are now supported. - Added ABI handling for ``__float128`` to match with GCC. +- Emit warnings for options to enable knl/knm specific ISAs: AVX512PF, AVX512ER

[llvm] [clang] [Clang][RISCV] Move getVScaleRange logic into libLLVMFrontendDriver. NFC (PR #77327)

@@ -2,6 +2,7 @@ set(LLVM_LINK_COMPONENTS Support TargetParser FrontendOpenMP + FrontendDriver topperc wrote: I've very confused by naming of the library. It's called FrontendDriver but is currently important by clang's CodeGen library rather than the d

[llvm] [clang] [Clang][RISCV] Move getVScaleRange logic into libLLVMFrontendDriver. NFC (PR #77327)

https://github.com/topperc deleted https://github.com/llvm/llvm-project/pull/77327 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [Clang][RISCV] Move getVScaleRange logic into libLLVMFrontendDriver. NFC (PR #77327)

@@ -2,6 +2,7 @@ set(LLVM_LINK_COMPONENTS Support TargetParser FrontendOpenMP + FrontendDriver topperc wrote: Ignore the earlier comment I wrote here I misread CodeGenOptions.cpp. This is currently important into the clang Driver library which makes sen

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -380,14 +380,14 @@ void RISCVIntrinsicManagerImpl::InitRVVIntrinsic( OverloadedName += "_" + OverloadedSuffixStr.str(); // clang built-in function name, e.g. __builtin_rvv_vadd. - std::string BuiltinName = "__builtin_rvv_" + std::string(Record.Name); + std::string B

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -463,7 +464,7 @@ void RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR, bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult &LR, IdentifierInfo *II,

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -463,7 +464,7 @@ void RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR, bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult &LR, IdentifierInfo *II,

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -416,8 +416,10 @@ class RVVIntrinsic { RVVTypePtr getOutputType() const { return OutputType; } const RVVTypes &getInputTypes() const { return InputTypes; } llvm::StringRef getBuiltinName() const { return BuiltinName; } - llvm::StringRef getName() const { return Name;

[clang] [Headers][X86] Add more descriptions to ia32intrin.h and immintrin.h (PR #77686)

@@ -361,42 +425,146 @@ _wbinvd(void) { __builtin_ia32_wbinvd(); } +/// Rotates an 8-bit value to the left by the specified number of bits. +///This operation is undefined if the number of bits exceeds the size of +///the value. +/// +/// \headerfile +/// +/// This i

[clang] 016342e - [RISCV] Evaluate ICE operands to builtins using getIntegerConstantExpr.

Author: Craig Topper Date: 2022-06-26T13:51:17-07:00 New Revision: 016342e319fd31e41cf5ed16a6140a8ea2de74dd URL: https://github.com/llvm/llvm-project/commit/016342e319fd31e41cf5ed16a6140a8ea2de74dd DIFF: https://github.com/llvm/llvm-project/commit/016342e319fd31e41cf5ed16a6140a8ea2de74dd.diff

[clang] 17a36c7 - [RISCV] Zero extend immediate for vget/vset builtins to match vector.insert/extract intrinsics.

Author: Craig Topper Date: 2022-06-27T20:26:54-07:00 New Revision: 17a36c7c40e99aa28d4323698f69845d92d96682 URL: https://github.com/llvm/llvm-project/commit/17a36c7c40e99aa28d4323698f69845d92d96682 DIFF: https://github.com/llvm/llvm-project/commit/17a36c7c40e99aa28d4323698f69845d92d96682.diff

[clang] bd30d4b - [Driver] Add f16 support to -mrecip parsing.

Author: Craig Topper Date: 2022-04-28T08:33:52-07:00 New Revision: bd30d4be2354f149fa6cb6d65fd95e6796951529 URL: https://github.com/llvm/llvm-project/commit/bd30d4be2354f149fa6cb6d65fd95e6796951529 DIFF: https://github.com/llvm/llvm-project/commit/bd30d4be2354f149fa6cb6d65fd95e6796951529.diff

[clang] 232c00b - [RISCV] Add extra space into error message about unsupported extension version.

Author: Craig Topper Date: 2022-05-12T12:56:29-07:00 New Revision: 232c00ba5bd1dc6ba69598170f57cba7b20d2635 URL: https://github.com/llvm/llvm-project/commit/232c00ba5bd1dc6ba69598170f57cba7b20d2635 DIFF: https://github.com/llvm/llvm-project/commit/232c00ba5bd1dc6ba69598170f57cba7b20d2635.diff

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

@@ -74,6 +74,21 @@ let TargetPrefix = "riscv" in { } // TargetPrefix = "riscv" +let TargetPrefix = "riscv" in { + // Zicsr + def int_riscv_csrr : +DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], + [IntrNoMem, IntrHasSideEffects, ImmArg>]>;

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

topperc wrote: > Individual implementations will provide different sets of CSR's and need a > way to read/write them. Of course, this can be done with inline asm, but > doing such things with inline asm has its limitations (no error checking, Wouldn't the assembler error check the constant? Di

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

@@ -20,6 +20,12 @@ class RISCVBuiltin : TargetBuiltin { let Attributes = [NoThrow, Const] in { //===--===// +// Zicsr extension. +//===--==

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1, cflush.d.l1, and cease instructions. (PR #83896)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/83896 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

topperc wrote: > I support adding these builtins personally, but I think we need more > discussions on the design. We can achieve the same thing via inline > assemblies, that's true. But, from the compiler side, inline assemblies are > kind of barriers, we can't do a lot of optimizations/reord

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, "string must be lowercase"); } + bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") || + Arch.starts_with("r

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, "string must be lowercase"); } + bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") || + Arch.starts_with("r

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, "string must be lowercase"); } + bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") || + Arch.starts_with("r

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

topperc wrote: Should we use strings like ARM does so we can get register by name? https://github.com/llvm/llvm-project/pull/85091 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/77560 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -244,6 +249,42 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { }; // clang-format on +static const RISCVProfile SupportedProfiles[] = { topperc wrote: `const` -> `constexpr` to be sure the StringLiteral constexpr constructor

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/76357 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [InstCombine] Canonicalize `(sitofp x)` -> `(uitofp x)` if `x >= 0` (PR #82404)

topperc wrote: > > Apart from the correctness issues, we've seen some regressions on various > > benchmarks from LLVM Test Suite after this patch. Specifically, around 3-5% > > regression on x86-64 in various metrics of the > > [Interpolation](https://github.com/llvm/llvm-test-suite/tree/main/

[clang] [llvm] [InstCombine] Canonicalize `(sitofp x)` -> `(uitofp x)` if `x >= 0` (PR #82404)

topperc wrote: > > > Well, I'm not sure how proper that wold be as a reproducer, > > > I extracted the mentioned test to a program: > > > ``` > > > #include > > > > > > #include "third_party/swiftshader/src/Reactor/Coroutine.hpp" > > > #include "third_party/swiftshader/src/Reactor/Reactor.hpp"

[clang] [CLANG] Fix potential integer overflow value in getRVVTypeSize() (PR #86810)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/86810 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [CGBuiltin] Use freeze instruction to create an undef value instead of zero (PR #86967)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/86967 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [CGBuiltin] Use freeze instruction to create an undef value instead of zero (PR #86967)

topperc wrote: I believe this has been tried in the past and reverted. Have we resolved the issues from the past? https://github.com/llvm/llvm-project/pull/86967 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/ma

[clang] [CGBuiltin] Use freeze instruction to create an undef value instead of zero (PR #86967)

https://github.com/topperc reopened https://github.com/llvm/llvm-project/pull/86967 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Disallow target attribute use in multiversioning (PR #85899)

@@ -11853,6 +11853,10 @@ static bool CheckMultiVersionFunction(Sema &S, FunctionDecl *NewFD, if (NewTA && S.getASTContext().getTargetInfo().getTriple().isAArch64()) return false; + // Target attribute on RISCV is not used for multiversioning + if (NewTA && S.getASTCon

[llvm] [clang] [RISCV] Add Ssqosid support to -march. (PR #80747)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/80747 >From a92d11432df57ad7172d80157e794ebec63b3410 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 5 Feb 2024 13:46:32 -0800 Subject: [PATCH 1/2] [RISCV] Add Ssqosid support to -march. --- clang/test/Preproc

[llvm] [clang] [RISCV] Add Ssqosid support to -march. (PR #80747)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/80747 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add canonical ISA string as Module metadata in IR. (PR #80760)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/80760 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add canonical ISA string as Module metadata in IR. (PR #80760)

topperc wrote: > * Just to check my understanding, is the only usecase for this ISA naming > string to produce appropriate ELF attributes? We probably need it to set the `EF_RISCV_RVC` flag too. I just noticed we only set EF_RISCV_RVC based on C, and not Zca. Is that a bug? https://github.com

[clang] [RISCV] Add canonical ISA string as Module metadata in IR. (PR #80760)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/80760 >From 8000459a247317400eda6213a23f32ac89e1ea75 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 5 Feb 2024 14:57:17 -0800 Subject: [PATCH 1/2] [RISCV] Add -march string as Module metadata in IR. In an LTO

[clang] [llvm] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)

https://github.com/topperc approved this pull request. LGTM. We can resolve the question of default behavior later. https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/m

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/76548 >From 3dfa00b0dab1820d1d8692ea91e98b29c9f8b627 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 28 Dec 2023 16:49:03 -0800 Subject: [PATCH 1/4] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predica

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/76548 >From 3dfa00b0dab1820d1d8692ea91e98b29c9f8b627 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 28 Dec 2023 16:49:03 -0800 Subject: [PATCH 1/5] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predica

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

@@ -2136,14 +2136,16 @@ Value *ScalarExprEmitter::VisitCastExpr(CastExpr *CE) { // bitcast. if (const auto *FixedSrc = dyn_cast(SrcTy)) { if (const auto *ScalableDst = dyn_cast(DstTy)) { -// If we are casting a fixed i8 vector to a scalable 16 x i1 predic

[clang] [RISCV] Add canonical ISA string as Module metadata in IR. (PR #80760)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/80760 >From 8000459a247317400eda6213a23f32ac89e1ea75 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 5 Feb 2024 14:57:17 -0800 Subject: [PATCH 1/3] [RISCV] Add -march string as Module metadata in IR. In an LTO

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/76548 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add canonical ISA string as Module metadata in IR. (PR #80760)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/80760 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Improve error message when the extension is not supported (PR #83989)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/83989 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Reorder sema check for RVV type (PR #83553)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/83553 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Reorder sema check for RVV type (PR #83553)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/83553 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)

@@ -74,6 +74,8 @@ unsigned CodeGenTypes::ClangCallConvToLLVMCallConv(CallingConv CC) { case CC_SwiftAsync: return llvm::CallingConv::SwiftTail; case CC_M68kRTD: return llvm::CallingConv::M68k_RTD; case CC_PreserveNone: return llvm::CallingConv::PreserveNone; + case CC_R

[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)

@@ -3439,6 +3439,8 @@ StringRef FunctionType::getNameForCallConv(CallingConv CC) { case CC_PreserveAll: return "preserve_all"; case CC_M68kRTD: return "m68k_rtd"; case CC_PreserveNone: return "preserve_none"; + case CC_RISCVVectorCall: topperc wrote: P

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/83896 >From 9434f834c4d48559aeec94403c927f48b15763e3 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 4 Mar 2024 11:24:34 -0800 Subject: [PATCH 1/4] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instru

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

topperc wrote: > > By the way, is there any plan to support `CFLUSH.I.L1` in the future? > > Flushing the instruction cache doesn't make sense given it can never be > dirty. Invalidating/discarding does, but that's just what fence.i is doing? A cflush.i.l1 did appear in some SiFive manual at s

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -138,6 +150,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { /// initializeProperties(). RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; } + RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; } topperc wrote:

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -0,0 +1,189 @@ +//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -840,6 +886,33 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, "string must be lowercase"); } + bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") || + Arch.starts_with("r

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -0,0 +1,189 @@ +//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -138,6 +150,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { /// initializeProperties(). RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; } + RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; } topperc wrote:

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

topperc wrote: @jrtc27 does this look better now? https://github.com/llvm/llvm-project/pull/83896 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -0,0 +1,189 @@ +//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

topperc wrote: > Hi @topperc, can you add instruction alias for cflush and cdiscard > instructions when the rs1 is X0 to `sf.cflush.d.l1` and `sf.cflush.d.l1` > respectively, as this register is optional according to spec? x0 has special meaning, but the spec never says it is "optional". http

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

topperc wrote: > Also, I think we might need to update the extensions in the > `RISCVProcessors.td` file under SIFIVE_S76 microcontroller? This is a M-mode only extension, and we haven't historically been adding M or S mode extensions to the -mcpu lists. Except for `xiangshan-nanhu` having `S

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

topperc wrote: > > > Hi @topperc, can you add instruction alias for cflush and cdiscard > > > instructions when the rs1 is X0 to `sf.cflush.d.l1` and `sf.cflush.d.l1` > > > respectively, as this register is optional according to spec? > > > > > > x0 has special meaning, but the spec never say

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/83896 >From 9434f834c4d48559aeec94403c927f48b15763e3 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 4 Mar 2024 11:24:34 -0800 Subject: [PATCH 1/5] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instru

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/83896 >From f22a5cd30f77b2043f9c1f7f4482fad87fb79250 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 4 Mar 2024 11:24:34 -0800 Subject: [PATCH 1/5] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instru

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/83896 >From f22a5cd30f77b2043f9c1f7f4482fad87fb79250 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 4 Mar 2024 11:24:34 -0800 Subject: [PATCH 1/6] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instru

[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)

topperc wrote: > I don't know if we need S-mode profile CPUs. I lean towards not supporting them since the S extensions don't do anything in the compiler except preprocessor defines and ELF attributes, but maybe we should put it on the agenda for the sync meeting this week. https://github.com

[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)

@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) { } } - if (T->isRVVSizelessBuiltinType()) -checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext)); + if (T->isRVVSizelessBuiltinType() && isa(CurContext)) { +const FunctionD

[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

topperc wrote: > Thanks for clearing the confusion around whether rs1 would be optional or > not. Can we also add lit tests for the aliases? I already addded tests https://github.com/llvm/llvm-project/pull/83896/commits/f6f43e9f8ffa8b58d63178d28c826d0009de2f3b https://github.com/llvm/llvm-pro

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/83896 >From f22a5cd30f77b2043f9c1f7f4482fad87fb79250 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 4 Mar 2024 11:24:34 -0800 Subject: [PATCH 1/8] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instru

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/83896 >From f22a5cd30f77b2043f9c1f7f4482fad87fb79250 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 4 Mar 2024 11:24:34 -0800 Subject: [PATCH 1/9] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instru

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1, cflush.d.l1, and cease instructions. (PR #83896)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/83896 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1, cflush.d.l1, and cease instructions. (PR #83896)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/83896 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1, cflush.d.l1, and cease instructions. (PR #83896)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/83896 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Remove experimental from Zacas. (PR #83195)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/83195 Document that we don't use the double compare and swap instructions due to ABI concerns. >From 8ed68475b43008d9c7baff7f275026cc7ada5993 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 27 Feb 2024 14:01:5

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