[PATCH] D50043: [RISCV] RISC-V using -fuse-init-array by default

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Thanks, looks good to me. https://reviews.llvm.org/D50043 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman

[PATCH] D50246: [RISCV] Add support for computing sysroot for riscv32-unknown-elf

asb added a comment. Herald added a subscriber: jocewei. Thanks for the patch and sorry for the delay. Once someone else marked it accepted it moves to a separate list in Phabricator - obviously I need to check the 'waiting on authors' list better. As I see it are two changes here: 1. Calculat

[PATCH] D39053: [Bitfield] Add more cases to making the bitfield a separate location

asb added a comment. Just wanted to explicitly say that I'm happy the updated patch reflects the changes to docs and comments I requested. @hfinkel - are you happy for this to land now? https://reviews.llvm.org/D39053 ___ cfe-commits mailing list

[PATCH] D46822: [RISCV] Add driver for riscv32-unknown-elf baremetal target

asb created this revision. asb added reviewers: efriedma, phosek, apazos. Herald added subscribers: mgrang, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, sabuasal, jordy.potman.lists, simoncook, johnrusso, rbar, arichardson, mgorny, emaste. Herald added a reviewer: espindola. This patch a

[PATCH] D46822: [RISCV] Add driver for riscv32-unknown-elf baremetal target

asb added a comment. In https://reviews.llvm.org/D46822#1098764, @efriedma wrote: > Could you include some documentation for how to construct a baremetal > environment like the one this code expects? It's not clear what exactly you > expect to be installed where. Thanks for taking a look Eli

[PATCH] D44888: [RISCV] Default enable linker relaxation and add -mrelax, -mno-relax flags

asb added a comment. I wonder if it would be safer to change this patch so it adds -mrelax and -mno-relax but doesn't compile with linker relaxation by default. That makes it easier to test linker relaxation support, and gives more time for testing before then flipping to -mrelax as the default

[PATCH] D44888: [RISCV] Add -mrelax/-mno-relax flags to enable/disable RISCV linker relaxation

asb added a comment. This is looking good to me, just needs an update to address this request for a test in riscv-features.c that demonstrates the default +relax/-relax setting. Repository: rL LLVM https://reviews.llvm.org/D44888 __

[PATCH] D44888: [RISCV] Add -mrelax/-mno-relax flags to enable/disable RISCV linker relaxation

asb added a comment. In https://reviews.llvm.org/D44888#920, @shiva0217 wrote: > In https://reviews.llvm.org/D44888#1109361, @asb wrote: > > > This is looking good to me, just needs an update to address this > > request for a test in > > riscv

[PATCH] D44888: [RISCV] Add -mrelax/-mno-relax flags to enable/disable RISCV linker relaxation

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Looks good to me, thanks! Repository: rL LLVM https://reviews.llvm.org/D44888 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.l

[PATCH] D50246: [RISCV] Add support for computing sysroot for riscv32-unknown-elf

asb accepted this revision. asb added a comment. Looks good to me, thanks! Repository: rC Clang https://reviews.llvm.org/D50246 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D48412: [RISCV] Add support for interrupt attribute

asb accepted this revision. asb added a comment. Herald added a subscriber: rkruppe. This looks good to me with two caveats - the tests don't seem to check that the "machine" is the default mode when the "interrupt" attribute has no arguments. - Although the conversion from RISCVInterruptAttr::u

[PATCH] D48412: [RISCV] Add support for interrupt attribute

asb accepted this revision. asb added a comment. Looks good to me. https://reviews.llvm.org/D48412 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D50043: [RISCV] RISC-V using -fuse-init-array by default

asb added a comment. Could you add a test for this please? Repository: rC Clang https://reviews.llvm.org/D50043 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D43105: [RISCV] Enable __int128_t and uint128_t through clang flag

asb added a comment. In https://reviews.llvm.org/D43105#1003709, @efriedma wrote: > So you want int128_t for compiler-rt itself, so you can use the soft-float > implementation, but you want to make int128_t opt-in to avoid the possibility > of someone getting a link error trying to link code bu

[PATCH] D43105: [RISCV] Enable __int128_t and uint128_t through clang flag

asb added a comment. Herald added a subscriber: shiva0217. As @efriedma noted in https://reviews.llvm.org/D43106, it would be good to have some test coverage for ABI lowering. I'd suggest updating test/Driver/riscv32-abi.c with something like: #ifdef __SIZEOF_INT128__ // CHECK-FORCEINT128-L

[PATCH] D43105: [RISCV] Enable __int128_t and __uint128_t through clang flag

asb accepted this revision. asb added a comment. I've added two suggestions on further tweaking the tests which I think it would be worth adopting. Looks good to me. Comment at: test/CodeGen/riscv32-abi.c:424-430 + +// RUN: %clang_cc1 -triple riscv32 -fforce-enable-int128 \ +/

[PATCH] D43105: [RISCV] Enable __int128_t and __uint128_t through clang flag

asb added inline comments. Comment at: test/CodeGen/riscv32-abi.c:2-3 // RUN: %clang_cc1 -triple riscv32 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple riscv32 -emit-llvm -fforce-enable-int128 %s -o - \ +// RUN: | FileCheck %s -check-prefix=CHECK-FORCEINT128 ---

[PATCH] D41271: [RISCV] Propagate -mabi and -march values to GNU assembler.

asb edited subscribers, added: cfe-commits; removed: llvm-commits. asb added a comment. Removing llvm-commits and adding cfe-commits. Thanks Ana. This looks good to me. We probably should have a default march, but I don't know what it should be. If most clang targets default to a Linux-capable

[PATCH] D41271: [RISCV] Propagate -mabi and -march values to GNU assembler.

asb added inline comments. Comment at: test/Driver/riscv-gnutools.c:6 +// RUN: %clang -target riscv64-unknown-elf -fno-integrated-as %s -### \ +// RUN: 2>&1 | FileCheck -check-prefix=MABI-ILP64 %s + s/MABI-ILP64/MABI-LP64 https://reviews.llvm.org/D41271

[PATCH] D39963: [RISCV] Add initial RISC-V target and driver support

This revision was automatically updated to reflect the committed changes. Closed by commit rC322276: [RISCV] Add the RISCV target and compiler driver (authored by asb, committed by ). Changed prior to commit: https://reviews.llvm.org/D39963?vs=126771&id=129436#toc Repository: rC Clang https

[PATCH] D41271: [RISCV] Propagate -mabi and -march values to GNU assembler.

asb added a comment. I've just had a painful time landing https://reviews.llvm.org/D39963 due to failures on the Windows buildbots. I think you'll have problems on Windows with the tests in this patch, as Windows surely won't default to /usr/bin/as. Sadly I don't have access to a windows Clang

[PATCH] D44189: [RISCV] Verify the input value of -march=

asb added a comment. Thanks for submitting this Kito. I've added some minor in-line comments. It might also be worth adding a couple of extra cases to the tests: - Repeated letters in the ISA string (e.g. rv32immafd) - Upper case letters in the ISA string. We currently reject these (as does GCC

[PATCH] D57055: [RISCV] Mark TLS as supported

asb added a comment. Could you add a test for this? I'm not sure if this is best done with a test that uses __has_feature or otherwise (I note other targets don't seem to have similar tests currently), but I think it would be handy. Repository: rC Clang CHANGES SINCE LAST ACTION https://r

[PATCH] D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics

asb created this revision. asb added reviewers: jfb, jyknight, wmi. Herald added subscribers: jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar. This ensures that libcalls

[PATCH] D57242: [RISCV] Specify MaxAtomicInlineWidth for RISC-V

asb added a comment. Thanks Lewis, I actually had a patch for this which I forgot to clean up and submit. I've done so now: D57450 . That adds tests, and sets MaxAtomicInlineWidth and MaxAtomicPromoteWidth conditionally based on whether the target has the atomic

[PATCH] D54091: [RISCV] Add inline asm constraints I, J & K for RISC-V

asb requested changes to this revision. asb added a comment. This revision now requires changes to proceed. Thanks for the patch Lewis. Could I please request the following changes: - It would be handy to link to https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html in the patch summar

[PATCH] D54816: [RISCV] Mark unit tests as "requires: riscv-registered-target"

asb added a comment. I'm a bit confused - what in these tests requires that lib/Target/RISCV was built? These tests obviously don't fail on the standard builders for instance. Repository: rL LLVM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D54816/new/ https://reviews.llvm.org/D548

[PATCH] D59233: libclang/CIndexer.cpp: Use loadquery() on AIX for path to library

asb added a comment. In D59233#1439656 , @hubert.reinterpretcast wrote: > Thanks @xingxue for the review. I will update for the error handling before > committing. Use of report_fatal_error/llvm_unreachable isn't fully consistent within the LLVM codeb

[PATCH] D59298: [RISCV] Pass -target-abi to -cc1as

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Herald added subscribers: benna, psnobl. Thanks, LGTM. Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D59298/new/ https://reviews.llvm.org/D59298 __

[PATCH] D53392: [RISCV] Collect library directories and triples for riscv64 triple too

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Herald added subscribers: benna, psnobl, MaskRay. This got missed somehow as I had a functionally identical patch in my local development tree (though not with as thorough tests - thanks for that!).

[PATCH] D53392: [RISCV] Collect library directories and triples for riscv64 triple too

This revision was automatically updated to reflect the committed changes. Closed by commit rL357699: [RISCV] Collect library directories and triples for riscv64 triple too (authored by asb, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Changed prior to com

[PATCH] D60456: [RISCV][WIP/RFC] Hard float ABI support

asb created this revision. asb added a reviewer: rjmccall. Herald added subscribers: benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar. Herald added a project

[PATCH] D60456: [RISCV][WIP/RFC] Hard float ABI support

asb updated this revision to Diff 198797. asb marked 3 inline comments as done. asb added a comment. Update: - Expanded and improved tests - Set ABI defines - Remove errant TODO - Use alignTo Still to do: - Review and test bitfield handling (which is likely incomplete) CHANGES SINCE LAST ACTI

[PATCH] D60456: [RISCV][WIP/RFC] Hard float ABI support

asb added inline comments. Comment at: lib/CodeGen/TargetInfo.cpp:9223 + + bool IsInt = Ty->isIntegralOrEnumerationType(); + bool IsFloat = Ty->isRealFloatingType(); rjmccall wrote: > Should this include pointers? Pointers are often interchangeably with > int

[PATCH] D47127: [RISCV] Default enable RISCV linker relaxation

asb edited subscribers, added: cfe-commits; removed: llvm-commits. asb added a comment. Removing llvm-commits and adding cfe-commits. This patch is mistakenly marked as targeting the LLVM repo rather than Clang. Repository: rL LLVM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D47127/

[PATCH] D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics

asb added a comment. Herald added a project: clang. Ping? Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57450/new/ https://reviews.llvm.org/D57450 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists

[PATCH] D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics

asb added a comment. In D57450#1402153 , @rogfer01 wrote: > Looks sensible to me. > > I'm just curious why we want to prevent emission of atomic LLVM instructions > at this point. Won't LLVM's AtomicExpand perform a similar lowering already? > Perhaps th

[PATCH] D57795: [RISCV] Add FreeBSD targets

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. This looks good to me, thanks! Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57795/new/ https://reviews.llvm.org/D57795 __

[PATCH] D54091: [RISCV] Add inline asm constraints I, J & K for RISC-V

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Herald added a subscriber: Jim. This looks good to me, but is blocked on the dependent patch being updated. I added a minor comment on riscv-inline-asm.c Comment at: test/CodeGen/

[PATCH] D60974: Clang IFSO driver action.

asb added inline comments. Comment at: cfe/trunk/lib/Frontend/CMakeLists.txt:58 clangDriver + clangIndex clangEdit plotfi wrote: > MaskRay wrote: > > This is a layering issue. clangIndex depends on clangFrontend so > > clangFrontend should not depend on c

[PATCH] D54295: [RISCV] Add inline asm constraint A for RISC-V

asb accepted this revision. asb added a comment. LGTM, thanks! Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D54295/new/ https://reviews.llvm.org/D54295 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://

[PATCH] D63498: [RISC-V] Add -msave-restore and -mno-save-restore to clang driver

asb added a comment. Can you add a CHECK line that shows the expected warning is emitted? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63498/new/ https://reviews.llvm.org/D63498 ___ cfe-commits mailin

[PATCH] D63497: Add support for openSUSE RISC-V triple

asb added a comment. Thanks for the contribution! I'd recommend adding a skeleton toolchain dir structure to clang/test/Driver/Inputs and adding a test to clang/test/Driver/riscv64-toolchain.c. You should be able to see examples in test/Driver/Inputs. Repository: rC Clang CHANGES SINCE LAS

[PATCH] D57055: [RISCV] Mark TLS as supported

asb accepted this revision. asb added a comment. Herald added subscribers: Jim, benna, psnobl. LGTM, thanks! Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57055/new/ https://reviews.llvm.org/D57055 ___ cfe-commits ma

[PATCH] D60456: [RISCV] Hard float ABI support

This revision was automatically updated to reflect the committed changes. Closed by commit rL366450: [RISCV] Hard float ABI support (authored by asb, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Changed prior to commit: https://reviews.llvm.org/D60456?v

[PATCH] D65500: [RISCV] Support 'f' Inline Assembly Constraint

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM, thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D65500/new/ https://reviews.llvm.org/D65500

[PATCH] D65634: [RISCV] Default to lp64d in 64-bit RISC-V Linux

asb added a comment. Thank Roger. While we're doing this, I think it would make sense to default to ilp32d on 32-bit Linux? I know the glibc support etc is less mature than for RV64, but it seems the sensible thing to do. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https

[PATCH] D65693: [driver][riscv] Support riscv64-linux-gnu multiarch paths

asb requested changes to this revision. asb added a comment. This revision now requires changes to proceed. Many thanks for the patch. Could you please add some tests for this behaviour? I imagine you'll want to add a new directory in test/Driver/Inputs with a Debian tree skeleton. See D63497

[PATCH] D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux

asb added a comment. In D65634#1618443 , @rogfer01 wrote: > Thanks @asb @lenary for the review! > > I understand that, after this change, we will also want to make > `-march=rv{32,64}gc` the default in Linux as well. Otherwise there will be an > ABI mism

[PATCH] D63498: [RISC-V] Add -msave-restore and -mno-save-restore to clang driver

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM, thanks! There was some discussion about the potential stdout+stderr merging issues http://lists.llvm.org/pipermail/llvm-dev/2017-February/110469.html but I don't think it resulted in any new

[PATCH] D64008: [RISCV] Avoid save-restore target feature warning

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM, thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D64008/new/ https://reviews.llvm.org/D64008

[PATCH] D63417: [RISCV] Specify registers used for exception handling

asb requested changes to this revision. asb added a comment. This revision now requires changes to proceed. Could you please add a riscv64 RUN line too, for completeness? Other archs seem to call the equivalent test file `builtins-archname.c` rather than `builtin-archname.c`, so I'd adjust the n

[PATCH] D63417: [RISCV] Specify registers used for exception handling

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Thanks, looks good to me! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63417/new/ https://reviews.llvm.org/D63417 ___ cfe-commits mailing lis

[PATCH] D63417: [RISCV] Specify registers used for exception handling

asb added inline comments. Comment at: test/CodeGen/builtins-riscv.c:4 + +void test_eh_return_data_regno() +{ Nit: having `{` on this line would be more consistent with usual LLVM style CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63417/new/ https://r

[PATCH] D63417: [RISCV] Specify registers used for exception handling

asb added a comment. Ed, if you haven't already could you request commit access so you can commit these approved patches yourself? See https://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access for details. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63417/new/ https://revie

[PATCH] D63497: Add support for openSUSE RISC-V triple

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Herald added a subscriber: lenary. LGTM, thanks! Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63497/new/ https://reviews.llvm.org/D63497

[PATCH] D60456: [RISCV] Hard float ABI support

asb added inline comments. Comment at: clang/lib/CodeGen/TargetInfo.cpp:9232 +if (IsFloat && Size > FLen) + return false; +// Can't be eligible if an integer type was already found (only fp+int or rjmccall wrote: > Is this the only consideration for

[PATCH] D63417: [RISCV] Specify registers used for exception handling

This revision was automatically updated to reflect the committed changes. Closed by commit rL365305: [RISCV] Specify registers used for exception handling (authored by asb, committed by ). Herald added subscribers: llvm-commits, lenary, MaskRay. Herald added a project: LLVM. Changed prior to comm

[PATCH] D60456: [RISCV] Hard float ABI support

asb updated this revision to Diff 208308. asb marked 7 inline comments as done. asb retitled this revision from "[RISCV][WIP/RFC] Hard float ABI support" to "[RISCV] Hard float ABI support". asb edited the summary of this revision. asb added a comment. Herald added subscribers: lenary, Jim, MaskRa

[PATCH] D60456: [RISCV] Hard float ABI support

asb marked an inline comment as done. asb added inline comments. Comment at: clang/lib/CodeGen/TargetInfo.cpp:9352 +return false; + // As a quirk of the ABI, zero-width bitfields aren't ignored for fp+fp + // or int+fp structs, but are ignored for a struct with

[PATCH] D60456: [RISCV] Hard float ABI support

asb updated this revision to Diff 208392. asb marked an inline comment as done. asb added a comment. Updated to address comment typo picked up by @rogfer01 (thanks!). As noted in another comment, it's not entirely clear what zero-width bitfield behaviour to match (see here

[PATCH] D60456: [RISCV] Hard float ABI support

asb added inline comments. Comment at: clang/lib/CodeGen/TargetInfo.cpp:9236 +if (IsInt && Field1Ty && Field1Ty->isIntegerTy()) + return false; +if (!Field1Ty) { rjmccall wrote: > asb wrote: > > rjmccall wrote: > > > The comment here is wrong because

[PATCH] D60456: [RISCV] Hard float ABI support

asb updated this revision to Diff 208477. asb marked 4 inline comments as done. asb added a comment. Tweaked a code comment. Just to confirm, @rjmccall are you happy for me to commit this? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D60456/new/ https://reviews.llvm.org/D60456 Files:

[PATCH] D60456: [RISCV] Hard float ABI support

asb added a comment. Thanks for the careful review John, I really appreciate it! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D60456/new/ https://reviews.llvm.org/D60456 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.

[PATCH] D45237: [RISCV] Fix logic to check if frame pointer should be used

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Thanks, looks good to me. https://reviews.llvm.org/D45237 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman

[PATCH] D45284: [RISCV] More validations on the input value of -march=

asb added a comment. I've added a few comments on tweaking the error messages based on your tests. Comment at: test/Driver/riscv-arch.c:157 +// RV32-STR: error: invalid arch name 'rv32', +// RV32-STR: string must begin with rv32 or rv64 + But the given string d

[PATCH] D44888: [RISCV] Default enable linker relaxation and add -mrelax, -mno-relax flags

asb added a comment. Looks good to me, just missing help text on the command line options. Repository: rL LLVM https://reviews.llvm.org/D44888 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/

[PATCH] D45284: [RISCV] More validations on the input value of -march=

asb added inline comments. Comment at: lib/Driver/ToolChains/Arch/RISCV.cpp:50 + +static void getExtensionVersion(StringRef In, std::string &Version) { + auto I = In.begin(); You should probably document the limitation that this doesn't currently parse minor ve

[PATCH] D44888: [RISCV] Default enable linker relaxation and add -mrelax, -mno-relax flags

asb requested changes to this revision. asb added a comment. This revision now requires changes to proceed. Thanks Kito. -mrelax and -mno-relax currently only affect the backend. For completeness, I think this patch needs to pass the appropriate flag to the linker depending on relax/no-relax.

[PATCH] D45284: [RISCV] More validations on the input value of -march=

asb added a comment. Herald added a subscriber: edward-jones. This is looking great, the only remaining code comment I have is that getExtensionFeatures needs a comment describing it. The remaining issue I have is more of a spec issue - do canonical ordering requirements apply to extension cate

[PATCH] D39053: [Bitfield] Add more cases to making the bitfield a separate location

asb added a comment. Hi @spetrovic - I think Hal Finkel's earlier request to update the comments of IsBetterAsSingleFieldRun remains unaddressed. It looks like at least the comment string immediately before `auto IsBetterAsSingleFieldRun` needs to be updated to reflect the changed behaviour. T

[PATCH] D45284: [RISCV] More validations on the input value of -march=

asb added a comment. In https://reviews.llvm.org/D45284#1074282, @apazos wrote: > Hi Alex, it seems the table expects these extensions in a canonical order > too: all x extensions, followed by all s extensions, and then all sx > extensions. > > I can make the change, no problem. I have also cod

[PATCH] D45284: [RISCV] More validations on the input value of -march=

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Looks good to me - thanks! https://reviews.llvm.org/D45284 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailma

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

asb added a comment. In D67185#1707849 , @lenary wrote: > Note, D68862 is in-progress at the moment, > which is related to this patch. Indeed - Simon, could you please go through that patch and ensure that the implemen

[PATCH] D71124: [RISCV] support clang driver to select cpu

asb accepted this revision. asb added a comment. LGTM, thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D71124/new/ https://reviews.llvm.org/D71124 ___ cfe-commits mailing list cfe-commits@lists.ll

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

asb added a comment. I've approved D65649 now, so I think this one can land as soon as that one does. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D73891/new/ https://reviews.llvm.org/D73891 ___

[PATCH] D79155: [CodeGen] Increase applicability of ffine-grained-bitfield-accesses for targets with limited native integer widths

asb added a comment. Ping on this. The patch still applies cleanly against current HEAD. @efriedma: was your comment an LGTM? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79155/new/ https://reviews.llvm.org/D79155 ___ cfe-commits mailing

[PATCH] D79155: [CodeGen] Increase applicability of ffine-grained-bitfield-accesses for targets with limited native integer widths

asb added a comment. In D79155#2088191 , @efriedma wrote: > Please add a comment explaining what OffsetInRecord means; then LGTM. Thanks. It's not easy to follow, but having stepped through it I agree with yu that it is the size in bits of the current r

[PATCH] D79155: [CodeGen] Increase applicability of ffine-grained-bitfield-accesses for targets with limited native integer widths

This revision was not accepted when it landed; it landed in state "Needs Review". This revision was automatically updated to reflect the committed changes. Closed by commit rG3dcfd482cb17: [CodeGen] Increase applicability of ffine-grained-bitfield-accesses for targets… (authored by asb). Changed

[PATCH] D71124: [RISCV] support clang driver to select cpu

asb added a comment. This has been hanging around for a while, but I think we'd basically agreed this is the right logic. The comments have ended up referring to flags that don't exist on Clang making it a little hard to follow, and I've added a request to slightly expand testing. If you make t

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

asb added a comment. I've gone through and can't see any obvious issues. I defer to one of the RISC-V Vector extension usual suspects for giving a LGTM on the detail of the altered instructions etc. Once we have that, this looks good to land IMHO. Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D81583: Update SystemZ ABI to handle C++20 [[no_unique_address]] attribute

asb added a comment. This LGTM from a RISC-V perspective. I'll likely follow up with a RISC-V test case similar to the SystemZ one post-commit, but given this is really fixing a cross-platform ABI issue this seems non-urgent. Thanks for spotting and addressing this issue. CHANGES SINCE LAST A

[PATCH] D71124: [RISCV] support clang driver to select cpu

asb added a comment. I've added some suggestions to clarify the code comments. I think before landing it would be good to address the crash Sam pointed out for an invalid -march, but otherwise I think this looks good to me (at least, it seems worth landing this and if further issues crop up we

[PATCH] D83819: [RISCV] Add error checking for extensions missing separating underscores

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM, thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83819/new/ https://reviews.llvm.org/D83819

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. In D69987#2079524 , @rogfer01 wrote: > The patch as it stands now LGTM and I think it can be committed. Is there any > objection remaining? > > Any further c

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

asb added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:9 +/// +/// This file describes the RISC-V instructions from the standard 'V', +/// Vector instruction set extension. Please add similar language as in RISCVInstrInfoB.td to indicate

[PATCH] D79155: [CodeGen] Increase applicability of ffine-grained-bitfield-accesses for targets with limited native integer widths

asb created this revision. asb added reviewers: wmi, hfinkel, efriedma. Herald added subscribers: cfe-commits, luismarques, sameer.abuasal, s.egerton, lenary, PkmX, simoncook. Herald added a project: clang. asb added a subscriber: apazos. As pointed out in PR45708

[PATCH] D79155: [CodeGen] Increase applicability of ffine-grained-bitfield-accesses for targets with limited native integer widths

asb updated this revision to Diff 261138. asb added a comment. Updated patch to include full context. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79155/new/ https://reviews.llvm.org/D79155 Files: clang/lib/CodeGen/CGRecordLayoutBuilder.cpp clang/test/CodeGenCXX/finegrain-bitfield

[PATCH] D79770: [RISCV] Fix passing two floating-point values in complex separately by two GPRs on RV64

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Good catch, thanks for the fix! The logic was incorrectly written assuming `isFloatingType` would return false for complex values which is of course incorrect. Comment at: clang/

[PATCH] D40023: [RISCV] Implement ABI lowering

asb added a comment. In https://reviews.llvm.org/D40023#933464, @majnemer wrote: > So how does something like the following work: > > union U { float f; int i; }; > void f(union U u); > > > The flattening described in > https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

[PATCH] D39963: [RISCV][RFC] Add initial RISC-V target and driver support

asb marked an inline comment as done. asb added a comment. In https://reviews.llvm.org/D39963#931026, @apazos wrote: > Can you push this as a patch to review/commit instead of RFC? It has received > a lot of comments/corrections already and I think it is getting in a shape we > can merge. I m

[PATCH] D39963: [RISCV] Add initial RISC-V target and driver support

asb updated this revision to Diff 126404. asb marked 3 inline comments as done. asb retitled this revision from "[RISCV][RFC] Add initial RISC-V target and driver support" to "[RISCV] Add initial RISC-V target and driver support". asb edited the summary of this revision. asb added a comment. Heral

[PATCH] D39963: [RISCV] Add initial RISC-V target and driver support

asb updated this revision to Diff 126769. asb edited the summary of this revision. asb added a comment. Update to add test cases based on the multilib Linux SDK produced by https://github.com/riscv/riscv-gnu-toolchain/. https://reviews.llvm.org/D39963 Files: lib/Basic/CMakeLists.txt lib/Ba

[PATCH] D39963: [RISCV] Add initial RISC-V target and driver support

asb updated this revision to Diff 126771. asb added a comment. Apologies, the last version had a few lines of debug code left in. I should say that this is to the best of my knowledge ready to merge (i.e. there are no outstanding flagged issues). Particularly now that the majority of the RV32I

[PATCH] D133444: [RISCV] Update error message to not call 'RV32' and 'RV64' an extension.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM, thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D133444/new/ https://reviews.llvm.org/D133444

[PATCH] D133443: [RISCV][MC] Add support for experimental Zawrs extension

asb added a comment. The change in set of instructions without changing the version number is concerning - do you know anyone involved in that group? It would be good to feedback the difficulties this can cause for us. It's also not clear if there might be changes again during ratification with

[PATCH] D133443: [RISCV][MC] Add support for experimental Zawrs extension

asb added a comment. I think the summary of our discussion on this was: - The versioning confusion is unfortunate - ideally there would be discussion elsewhere at RVI on improving the situation (either ELF attributes to indicate extensions are experimental, or making that unnecessary via never

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

asb added a comment. Thanks, I'll take another look. Rereading my previous comment I just wanted to clarify one part so it's not misunderstood. I said " I think it's unfortunate that this need for the ABI hasn't translated into effort to finalise the ABI definition in the psABI doc and to at le

[PATCH] D117432: [RISCV] Implement support for the Zicbom and Zicboz extensions

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG4f40ca53cefb: [RISCV] Implement support for the Zicbom and Zicboz extensions (authored by asb). Herald added a project: clang. Herald added a subscri

[PATCH] D117433: [RISCV] Implement support for the Zicbop extension

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG7bcfcabbd14e: [RISCV] Implement support for the Zicbop extension (authored by asb). Herald added a project: clang. Herald added a subscriber: cfe-com

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