[PATCH] D63417: [RISCV] Specify registers used for exception handling

[Alex Bradbury via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL365305: [RISCV] Specify registers used for exception 
handling (authored by asb, committed by ).
Herald added subscribers: llvm-commits, lenary, MaskRay.
Herald added a project: LLVM.

Changed prior to commit:
  https://reviews.llvm.org/D63417?vs=207769&id=208339#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63417/new/

https://reviews.llvm.org/D63417

Files:
  cfe/trunk/lib/Basic/Targets/RISCV.h
  cfe/trunk/test/CodeGen/builtins-riscv.c


Index: cfe/trunk/test/CodeGen/builtins-riscv.c
===================================================================
--- cfe/trunk/test/CodeGen/builtins-riscv.c
+++ cfe/trunk/test/CodeGen/builtins-riscv.c
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -Wall -Werror -triple riscv32 -disable-O0-optnone 
-emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -Wall -Werror -triple riscv64 -disable-O0-optnone 
-emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+
+void test_eh_return_data_regno() {
+  // CHECK: store volatile i32 10
+  // CHECK: store volatile i32 11
+  volatile int res;
+  res = __builtin_eh_return_data_regno(0);
+  res = __builtin_eh_return_data_regno(1);
+}
Index: cfe/trunk/lib/Basic/Targets/RISCV.h
===================================================================
--- cfe/trunk/lib/Basic/Targets/RISCV.h
+++ cfe/trunk/lib/Basic/Targets/RISCV.h
@@ -57,6 +57,15 @@
 
   ArrayRef<const char *> getGCCRegNames() const override;
 
+  int getEHDataRegisterNumber(unsigned RegNo) const override {
+    if (RegNo == 0)
+      return 10;
+    else if (RegNo == 1)
+      return 11;
+    else
+      return -1;
+  }
+
   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *&Name,



Index: cfe/trunk/test/CodeGen/builtins-riscv.c
===================================================================
--- cfe/trunk/test/CodeGen/builtins-riscv.c
+++ cfe/trunk/test/CodeGen/builtins-riscv.c
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -Wall -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -Wall -Werror -triple riscv64 -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+
+void test_eh_return_data_regno() {
+  // CHECK: store volatile i32 10
+  // CHECK: store volatile i32 11
+  volatile int res;
+  res = __builtin_eh_return_data_regno(0);
+  res = __builtin_eh_return_data_regno(1);
+}
Index: cfe/trunk/lib/Basic/Targets/RISCV.h
===================================================================
--- cfe/trunk/lib/Basic/Targets/RISCV.h
+++ cfe/trunk/lib/Basic/Targets/RISCV.h
@@ -57,6 +57,15 @@
 
   ArrayRef<const char *> getGCCRegNames() const override;
 
+  int getEHDataRegisterNumber(unsigned RegNo) const override {
+    if (RegNo == 0)
+      return 10;
+    else if (RegNo == 1)
+      return 11;
+    else
+      return -1;
+  }
+
   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *&Name,

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