[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

2024-08-21 Thread Sam Elliott via cfe-commits
https://github.com/lenary closed https://github.com/llvm/llvm-project/pull/102452 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

2024-08-20 Thread Michael Maitland via cfe-commits
https://github.com/michaelmaitland approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/102452 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

2024-08-20 Thread Sam Elliott via cfe-commits
https://github.com/lenary updated https://github.com/llvm/llvm-project/pull/102452 >From b125071eeb35ee4a76e126967b7c29d86a1fae56 Mon Sep 17 00:00:00 2001 From: Sam Elliott Date: Fri, 16 Aug 2024 07:52:53 -0700 Subject: [PATCH 1/2] [clang][test] Split invalid-cpu-note tests This change does tw

[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

2024-08-20 Thread Sam Elliott via cfe-commits
lenary wrote: The commit this was stacked on is merged, and I think we have sorted out naming issues and pinned down the exact cpu configuration, so I think this is ready for review and merge. https://github.com/llvm/llvm-project/pull/102452 ___ cfe-

[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

2024-08-19 Thread Sam Elliott via cfe-commits
lenary wrote: > Is this PR stacked on > [b125071](https://github.com/llvm/llvm-project/commit/b125071eeb35ee4a76e126967b7c29d86a1fae56) > (I don't see any note of that in the PR description at the moment)? > > Edit: I found the comment that says that! Yeah, sorry, I only stacked it about half

[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

2024-08-19 Thread Michael Maitland via cfe-commits
michaelmaitland wrote: Is this PR stacked on b125071eeb35ee4a76e126967b7c29d86a1fae56? https://github.com/llvm/llvm-project/pull/102452 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

2024-08-19 Thread Sam Elliott via cfe-commits
https://github.com/lenary updated https://github.com/llvm/llvm-project/pull/102452 >From b125071eeb35ee4a76e126967b7c29d86a1fae56 Mon Sep 17 00:00:00 2001 From: Sam Elliott Date: Fri, 16 Aug 2024 07:52:53 -0700 Subject: [PATCH 1/2] [clang][test] Split invalid-cpu-note tests This change does tw

[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

2024-08-17 Thread Luke Wren via cfe-commits
@@ -402,6 +402,21 @@ // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkt" // MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d" +// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rp2350-hazard3 | FileCheck -check-prefix=MCPU-HAZARD3 %s +// MCPU-HAZARD3: "-target-cpu" "rp2350-haza

[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

2024-08-17 Thread Craig Topper via cfe-commits
@@ -402,6 +402,21 @@ // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkt" // MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d" +// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rp2350-hazard3 | FileCheck -check-prefix=MCPU-HAZARD3 %s +// MCPU-HAZARD3: "-target-cpu" "rp2350-haza

[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

2024-08-17 Thread Luke Wren via cfe-commits
@@ -402,6 +402,21 @@ // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkt" // MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d" +// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rp2350-hazard3 | FileCheck -check-prefix=MCPU-HAZARD3 %s +// MCPU-HAZARD3: "-target-cpu" "rp2350-haza

[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

2024-08-16 Thread Craig Topper via cfe-commits
@@ -402,6 +402,21 @@ // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkt" // MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d" +// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rp2350-hazard3 | FileCheck -check-prefix=MCPU-HAZARD3 %s +// MCPU-HAZARD3: "-target-cpu" "rp2350-haza

[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

2024-08-16 Thread Sam Elliott via cfe-commits
@@ -108,6 +108,7 @@ Changes to the RISC-V Backend fill value) rather than NOPs. * Added Syntacore SCR4 and SCR5 CPUs: ``-mcpu=syntacore-scr4/5-rv32/64`` * ``-mcpu=sifive-p470`` was added. +* Added Hazard3 CPU: ``-mcpu=hazard3`` (32-bit only). lenary wrote: D

[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

2024-08-16 Thread Luke Wren via cfe-commits
@@ -402,6 +402,21 @@ // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkt" // MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d" +// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rp2350-hazard3 | FileCheck -check-prefix=MCPU-HAZARD3 %s +// MCPU-HAZARD3: "-target-cpu" "rp2350-haza

[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

2024-08-16 Thread Luke Wren via cfe-commits
@@ -108,6 +108,7 @@ Changes to the RISC-V Backend fill value) rather than NOPs. * Added Syntacore SCR4 and SCR5 CPUs: ``-mcpu=syntacore-scr4/5-rv32/64`` * ``-mcpu=sifive-p470`` was added. +* Added Hazard3 CPU: ``-mcpu=hazard3`` (32-bit only). Wren6991 wrote:

[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

2024-08-16 Thread Sam Elliott via cfe-commits
https://github.com/lenary edited https://github.com/llvm/llvm-project/pull/102452 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

2024-08-16 Thread Sam Elliott via cfe-commits
https://github.com/lenary edited https://github.com/llvm/llvm-project/pull/102452 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits