================ @@ -402,6 +402,21 @@ // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkt" // MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d" +// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rp2350-hazard3 | FileCheck -check-prefix=MCPU-HAZARD3 %s +// MCPU-HAZARD3: "-target-cpu" "rp2350-hazard3" +// MCPU-HAZARD3-SAME: "-target-feature" "+m" +// MCPU-HAZARD3-SAME: "-target-feature" "+a" +// MCPU-HAZARD3-SAME: "-target-feature" "+c" +// MCPU-HAZARD3-SAME: "-target-feature" "+zicsr" +// MCPU-HAZARD3-SAME: "-target-feature" "+zifencei" +// MCPU-HAZARD3-SAME: "-target-feature" "+zcb" +// MCPU-HAZARD3-SAME: "-target-feature" "+zcmp" +// MCPU-HAZARD3-SAME: "-target-feature" "+zba" ---------------- Wren6991 wrote:
What's LLVM's opinion on the relation between B and ZbaZbbZbs? Does flagging ZbaZbbZbs without B still allow people to check `#ifdef __riscv_b` in their code? This tapeout of Hazard3 predates the ratification of B as this combination, so `misa.b` is not set. However `misa.b` is a one-way implication: `misa.b` implies B, but `!misa.b` does not imply !B. Per the ISA manual: > When "B" bit is 1, the implementation supports the instructions provided by > the Zba, Zbb, and Zbs extensions. When "B" bit is 0, it indicates that the > implementation may not support one or more of the Zba, Zbb, or Zbs extensions. Based on this I would say this version of Hazard3 does implement the B extension, just not `misa.b`. It's a bit of a broader question about LLVM though. https://github.com/llvm/llvm-project/pull/102452 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
