================ @@ -108,6 +108,7 @@ Changes to the RISC-V Backend fill value) rather than NOPs. * Added Syntacore SCR4 and SCR5 CPUs: ``-mcpu=syntacore-scr4/5-rv32/64`` * ``-mcpu=sifive-p470`` was added. +* Added Hazard3 CPU: ``-mcpu=hazard3`` (32-bit only). ---------------- Wren6991 wrote:
Possibly wants tweaking to match the new flag https://github.com/llvm/llvm-project/pull/102452 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
