yetingk wrote:
Rebase and ping.
https://github.com/llvm/llvm-project/pull/99849
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>From 86221475bc98c0115cad564b1dc36a96544e921d Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Mon, 22 Jul 2024 01:18:51 -0700
Subject: [PATCH] [clang][CodeGen] Don't crash on output whose size is zero.
This fix
https://github.com/yetingk edited
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https://github.com/yetingk created
https://github.com/llvm/llvm-project/pull/99849
This fixes issue #63878 caused by creating an integer with zero bitwidth.
>From 44a0091b3e28b5c36f2eebe9e91d5c57f25a5d32 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Mon, 22 Jul 2024 01:18:51 -0700
Subject: [
https://github.com/yetingk closed
https://github.com/llvm/llvm-project/pull/98891
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>From be805db6c259d255b2ad3f0811bd1428bc8628c5 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Mon, 15 Jul 2024 19:51:55 -0700
Subject: [PATCH 1/2] [RISCV] Bump the version of Zicfilp/Zicfiss to 1.0
Both of them
yetingk wrote:
> > Since both of them should be experimental now, the pr is only change the
> > version of them now. Hence, I didn't change `llvm/docs/ReleaseNotes.rst`.
>
> Still need to note the version number change
Updated and rebase to fix conflicts.
https://github.com/llvm/llvm-project
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/98891
>From be805db6c259d255b2ad3f0811bd1428bc8628c5 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Mon, 15 Jul 2024 19:51:55 -0700
Subject: [PATCH 1/2] [RISCV] Bump the version of Zicfilp/Zicfiss to 1.0
Both of them
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/98891
>From 98002027bc0a1d4b9bb3d11f7a9bbb5717a81b49 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Mon, 15 Jul 2024 19:51:55 -0700
Subject: [PATCH 1/2] [RISCV] Bump the version of Zicfilp/Zicfiss to 1.0
Both of them
yetingk wrote:
Since both of them should be experimental now, the latest commit I didn't
remove the experimental for them. Hence, I didn't change
`llvm/docs/ReleaseNotes.rst`.
https://github.com/llvm/llvm-project/pull/98891
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>From 98002027bc0a1d4b9bb3d11f7a9bbb5717a81b49 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Mon, 15 Jul 2024 19:51:55 -0700
Subject: [PATCH] [RISCV] Bump the version of Zicfilp/Zicfiss to 1.0
Both of them are
yetingk wrote:
> AFAIK LLD doesn't support Zicfilp yet, which I feel is a prerequisite to
> marking it as non-experimental
I think we also not support Zicfiss to compiler-rt/libunwind, I think both of
them are still experimental now.
https://github.com/llvm/llvm-project/pull/98891
___
@@ -5,5 +5,5 @@
## Version strings are required for experimental extensions
-.attribute arch, "rv32izicfilp"
-# CHECK: error: invalid arch name 'rv32izicfilp', experimental extension
requires explicit version number `zicfilp`
+.attribute arch, "rv32izalasr"
https://github.com/yetingk created
https://github.com/llvm/llvm-project/pull/98891
Both of them are ratified.
https://wiki.riscv.org/display/HOME/Ratified+Extensions
>From fe7a971ae7c7dd7436bc39506bf660f49b37c974 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Mon, 15 Jul 2024 00:51:19 -0700
S
yetingk wrote:
I am sorry that I missed the commit for a long time. Very sorry about it.
https://github.com/llvm/llvm-project/pull/77414
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@@ -188,6 +188,8 @@ struct Config {
StringRef zBtiReport = "none";
StringRef zCetReport = "none";
StringRef zPauthReport = "none";
+ llvm::StringRef zZicfilpReport = "none";
yetingk wrote:
Use `StringRef` instead of `llvm::StringRef`.
https://github.co
@@ -7884,10 +7902,11 @@ template void
LLVMELFDumper::printNotes() {
W.printString("Type",
"Unknown (" + to_string(format_hex(Type, 10)) + ")");
+uint16_t Target = this->Obj.getHeader().e_machine;
yetingk wrote:
Move this defini
@@ -7884,10 +7902,11 @@ template void
LLVMELFDumper::printNotes() {
W.printString("Type",
"Unknown (" + to_string(format_hex(Type, 10)) + ")");
+uint16_t Target = this->Obj.getHeader().e_machine;
yetingk wrote:
Is it better to
@@ -954,9 +954,18 @@ void readGnuProperty(const InputSection &sec,
ObjFile &f) {
continue;
}
-uint32_t featureAndType = config->emachine == EM_AARCH64
- ? GNU_PROPERTY_AARCH64_FEATURE_1_AND
- : GN
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@@ -0,0 +1,7 @@
+// RUN: %clang --target=riscv64 -menable-experimental-extensions -c -o
/dev/null %s
yetingk wrote:
Yes. I am sorry that I didn't find out the obvious mistake. I am going to
review my development process.
https://github.com/llvm/llvm-project/pu
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@@ -0,0 +1,7 @@
+// RUN: %clang --target=riscv64 -menable-experimental-extensions -c -o
/dev/null %s
+// RUN: ! %clang --target=riscv64 -c -o /dev/null %s 2>&1 | FileCheck
-check-prefixes=CHECK-ERR %s
yetingk wrote:
Thank you. I will fix this if https://github.
https://github.com/yetingk created
https://github.com/llvm/llvm-project/pull/91324
PR #89727 added the two test cases to verify `.option arch` should only work
when having -menable-experimental-extensions. And the test idea could be
splitted to
1. When having menable-experimental-extensions, c
yetingk wrote:
@pogo59 Thank you for the advise. I will update the test cases.
https://github.com/llvm/llvm-project/pull/89727
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yetingk wrote:
@zmodem very thank you for the help.
https://github.com/llvm/llvm-project/pull/89727
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yetingk wrote:
@topperc Sorry, there was a quick fix after the approve.
`getTargetFeatureForExtension` could approve the extension with version. It may
be better to allow them, but I am not sure the error message could be enough
readable if we use wrong version number and is the format of out
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/89727
>From a43014cf3daa1b0fd9092bfe41da979205ba64aa Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 23 Apr 2024 02:16:04 -0700
Subject: [PATCH 1/6] [RISCV] Teach .option arch to support experimental
extensions.
@@ -51,7 +51,6 @@ STATISTIC(RISCVNumInstrsCompressed,
static cl::opt AddBuildAttributes("riscv-add-build-attributes",
cl::init(false));
-
yetingk wrote:
Done.
https://github.com/llvm/llvm-project/pull/89727
___
@@ -2824,8 +2826,12 @@ bool RISCVAsmParser::parseDirectiveOption() {
break;
}
- auto Ext = llvm::lower_bound(RISCVFeatureKV, Arch);
- if (Ext == std::end(RISCVFeatureKV) || StringRef(Ext->Key) != Arch ||
+ std::string Feature = RISCVISAInfo::getTar
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/89727
>From a43014cf3daa1b0fd9092bfe41da979205ba64aa Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 23 Apr 2024 02:16:04 -0700
Subject: [PATCH 1/5] [RISCV] Teach .option arch to support experimental
extensions.
@@ -169,6 +169,9 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back("-relax");
}
+ if (!Args.hasArg(options::OPT_menable_experimental_extensions))
+Features.push_back("+no-experimental-ext");
yetin
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/89727
>From a43014cf3daa1b0fd9092bfe41da979205ba64aa Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 23 Apr 2024 02:16:04 -0700
Subject: [PATCH 1/4] [RISCV] Teach .option arch to support experimental
extensions.
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/89727
>From a43014cf3daa1b0fd9092bfe41da979205ba64aa Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 23 Apr 2024 02:16:04 -0700
Subject: [PATCH 1/4] [RISCV] Teach .option arch to support experimental
extensions.
yetingk wrote:
I fix the issue by using feature to control the permission of experimental
extension.
> Does this disable use of experimental extensions for a `.option arch` in an
> inline assembly block without -menable-experimental-extensions.
https://github.com/llvm/llvm-project/pull/8972
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/89727
>From a43014cf3daa1b0fd9092bfe41da979205ba64aa Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 23 Apr 2024 02:16:04 -0700
Subject: [PATCH 1/4] [RISCV] Teach .option arch to support experimental
extensions.
yetingk wrote:
> Does this disable use of experimental extensions for a `.option arch` in an
> inline assembly block without -menable-experimental-extensions.
No. my patch could not block the case. I will try to think this problem after
my sleep.
https://github.com/llvm/llvm-project/pull/8972
@@ -2824,8 +2827,12 @@ bool RISCVAsmParser::parseDirectiveOption() {
break;
}
- auto Ext = llvm::lower_bound(RISCVFeatureKV, Arch);
- if (Ext == std::end(RISCVFeatureKV) || StringRef(Ext->Key) != Arch ||
+ std::string &&Feature = RISCVISAInfo::getT
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/89727
>From a43014cf3daa1b0fd9092bfe41da979205ba64aa Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 23 Apr 2024 02:16:04 -0700
Subject: [PATCH 1/3] [RISCV] Teach .option arch to support experimental
extensions.
https://github.com/yetingk edited
https://github.com/llvm/llvm-project/pull/89727
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@@ -2824,8 +2827,12 @@ bool RISCVAsmParser::parseDirectiveOption() {
break;
}
- auto Ext = llvm::lower_bound(RISCVFeatureKV, Arch);
- if (Ext == std::end(RISCVFeatureKV) || StringRef(Ext->Key) != Arch ||
+ std::string &&Feature = RISCVISAInfo::getT
@@ -51,6 +51,9 @@ STATISTIC(RISCVNumInstrsCompressed,
static cl::opt AddBuildAttributes("riscv-add-build-attributes",
cl::init(false));
+static cl::opt
+DisableExperimentalExtension("riscv-disable-experimental-ext",
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/89727
>From a43014cf3daa1b0fd9092bfe41da979205ba64aa Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 23 Apr 2024 02:16:04 -0700
Subject: [PATCH 1/2] [RISCV] Teach .option arch to support experimental
extensions.
https://github.com/yetingk closed
https://github.com/llvm/llvm-project/pull/68075
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@@ -51,9 +51,15 @@ static void emitSCSPrologue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (!STI.hasForcedSWShadowStack() &&
+
@@ -106,9 +112,15 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (!STI.hasForcedSWShadowStack() &&
+
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/68075
>From faed2ea0b0cd7dc207e0886be8cb1647343793d4 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 3 Oct 2023 16:08:06 +0800
Subject: [PATCH 1/9] [RISCV] Implement shadow stack on shadow stack mode with
Zicfiss
yetingk wrote:
> Will
> [riscv-non-isa/riscv-elf-psabi-doc#417](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/417)
> be implemented in a separate patch?
Sure.
https://github.com/llvm/llvm-project/pull/68075
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yetingk wrote:
Ping.
https://github.com/llvm/llvm-project/pull/68075
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@@ -27,6 +27,11 @@
// DEFAULT-NOT: "-target-feature" "-save-restore"
// DEFAULT-NOT: "-target-feature" "+save-restore"
+// RUN: %clang --target=riscv32-unknown-elf -### %s -mforced-sw-shadow-stack
2>&1 | FileCheck %s -check-prefix=FORCE-SW-SCS
yetingk wrote:
@@ -151,9 +157,12 @@ Usage
To enable ShadowCallStack, just pass the ``-fsanitize=shadow-call-stack`` flag
to both compile and link command lines. On aarch64, you also need to pass
-``-ffixed-x18`` unless your target already reserves ``x18``. On RISC-V, ``x3``
-(``gp``) is alwa
@@ -57,11 +57,16 @@ compiled application or the operating system. Integrating
the runtime into
the operating system should be preferred since otherwise all thread creation
and destruction would need to be intercepted by the application.
-The instrumentation makes use of the p
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/68075
>From faed2ea0b0cd7dc207e0886be8cb1647343793d4 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 3 Oct 2023 16:08:06 +0800
Subject: [PATCH 1/8] [RISCV] Implement shadow stack on shadow stack mode with
Zicfiss
yetingk wrote:
Ping.
https://github.com/llvm/llvm-project/pull/68075
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@@ -151,9 +155,10 @@ Usage
To enable ShadowCallStack, just pass the ``-fsanitize=shadow-call-stack`` flag
to both compile and link command lines. On aarch64, you also need to pass
-``-ffixed-x18`` unless your target already reserves ``x18``. On RISC-V, ``x3``
-(``gp``) is alwa
@@ -57,11 +57,14 @@ compiled application or the operating system. Integrating
the runtime into
the operating system should be preferred since otherwise all thread creation
and destruction would need to be intercepted by the application.
-The instrumentation makes use of the p
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/68075
>From faed2ea0b0cd7dc207e0886be8cb1647343793d4 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 3 Oct 2023 16:08:06 +0800
Subject: [PATCH 1/6] [RISCV] Implement shadow stack on shadow stack mode with
Zicfiss
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/68075
>From be70878169742f7e9cbb276a05254019c586897b Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 3 Oct 2023 16:08:06 +0800
Subject: [PATCH 1/6] [RISCV] Implement shadow stack on shadow stack mode with
Zicfiss
https://github.com/yetingk edited
https://github.com/llvm/llvm-project/pull/68075
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@@ -57,11 +57,12 @@ compiled application or the operating system. Integrating
the runtime into
the operating system should be preferred since otherwise all thread creation
and destruction would need to be intercepted by the application.
-The instrumentation makes use of the p
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/68075
>From be70878169742f7e9cbb276a05254019c586897b Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 3 Oct 2023 16:08:06 +0800
Subject: [PATCH 1/5] [RISCV] Implement shadow stack on shadow stack mode with
Zicfiss
yetingk wrote:
Unwinder could use property `GNU_PROPERTY_RISCV_FEATURE_1_ZICFISS` to know the
binary uses `ssp` as the shadow stack register.
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/417/files
https://github.com/llvm/llvm-project/pull/68075
_
yetingk wrote:
Rebase and ping. I also update the first comment of the first comment of this
pr since the control stack mode is removed and we add new feature
`forced-sw-shadow-stack`.
https://github.com/llvm/llvm-project/pull/68075
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https://github.com/llvm/llvm-project/pull/68075
>From be70878169742f7e9cbb276a05254019c586897b Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 3 Oct 2023 16:08:06 +0800
Subject: [PATCH 1/4] [RISCV] Implement shadow stack on shadow stack mode with
Zicfiss
https://github.com/yetingk edited
https://github.com/llvm/llvm-project/pull/68075
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@@ -1024,6 +1024,7 @@ static const char *ImpliedExtsZfinx[] = {"zicsr"};
static const char *ImpliedExtsZhinx[] = {"zhinxmin"};
static const char *ImpliedExtsZhinxmin[] = {"zfinx"};
static const char *ImpliedExtsZicntr[] = {"zicsr"};
+static const char *ImpliedExtsZicfiss[] = {"
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 4a73535ec7206951c6b843e11c81e6c0c01cc1d0 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/4] [RISCV] Add MC layer support for Zicfiss.
The patch adds the in
@@ -60,12 +60,3 @@ defm SSAMOSWAP_W : AMO_rr_aq_rl<0b01001, 0b010,
"ssamoswap.w">;
let Predicates = [HasStdExtZicfiss, IsRV64] in
defm SSAMOSWAP_D : AMO_rr_aq_rl<0b01001, 0b011, "ssamoswap.d">;
-
-//===--==
yetingk wrote:
Rebase but I didn't use alias to Zimop and Zcmop ways to achieve this code,
since using them will lose some information like `Uses = [SSP]`.
https://github.com/llvm/llvm-project/pull/66043
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https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 4a73535ec7206951c6b843e11c81e6c0c01cc1d0 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/3] [RISCV] Add MC layer support for Zicfiss.
The patch adds the in
https://github.com/yetingk approved this pull request.
LGTM. But please wait for @topperc's review.
https://github.com/llvm/llvm-project/pull/76395
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https://github.com/yetingk approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/76422
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@@ -693,6 +693,13 @@ def HasStdExtZimop :
Predicate<"Subtarget->hasStdExtZimop()">,
AssemblerPredicate<(all_of FeatureStdExtZimop),
"'Zimop' (May-Be-Operations)">;
+def FeatureStdExtZcmop : SubtargetFeature<"experi
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https://github.com/yetingk edited
https://github.com/llvm/llvm-project/pull/76395
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https://github.com/yetingk edited
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@@ -0,0 +1,30 @@
+//===-- RISCVInstrInfoZcmop.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,71 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/76390
>From 71c202c4f16451f7d0d9e17239f95418ea315c0a Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 26 Dec 2023 02:11:30 -0800
Subject: [PATCH] [RISCV][Clang] Remove default feature -save-restore.
It's unnecessa
https://github.com/yetingk edited
https://github.com/llvm/llvm-project/pull/76390
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@@ -0,0 +1,71 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
https://github.com/yetingk created
https://github.com/llvm/llvm-project/pull/76390
It's unnecessary to defaultly pass feature `-save-restore`, since risc-v
backend defaultly disables save-restore functionality.
>From 97fe56d808f1752ac4b7d26deecabb857e0a4208 Mon Sep 17 00:00:00 2001
From: Yetin
yetingk wrote:
Rebase.
> It seems that the author of Zimop implementation doesn't have commit access.
> @yetingk Would you mind to commit it and rebase your PR on that? It will make
> this PR simpler.
It's weird that `SSPUSH` and `SSPOPCHK` are not fit into `mop.r` instruction
now.
https://
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 99d35bbe5bab93b4a39a436d1bc9626e68c401ef Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH] [RISCV] Add MC layer support for Zicfiss.
The patch adds the instru
https://github.com/yetingk closed
https://github.com/llvm/llvm-project/pull/75182
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yetingk wrote:
> It seems that the author of Zimop implementation doesn't have commit access.
> @yetingk Would you mind to commit it and rebase your PR on that? It will make
> this PR simpler.
Sure.
https://github.com/llvm/llvm-project/pull/66043
__
yetingk wrote:
Ping.
https://github.com/llvm/llvm-project/pull/66043
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@@ -165,6 +167,10 @@ def SP : GPRRegisterClass<(add X2)>;
def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
(sequence "X%u", 18, 23))>;
+def GPRX1X5 : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X5)> {
yetingk wrote:
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 01222b781e3a0a925d2cdf793c54c7d6050f82af Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/2] [RISCV] Add MC layer support for Zicfiss.
The patch adds the in
yetingk wrote:
Rebase and ping.
https://github.com/llvm/llvm-project/pull/66043
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