https://github.com/yetingk updated https://github.com/llvm/llvm-project/pull/66043
>From 99d35bbe5bab93b4a39a436d1bc9626e68c401ef Mon Sep 17 00:00:00 2001 From: Yeting Kuo <yeting....@sifive.com> Date: Tue, 12 Sep 2023 12:28:00 +0800 Subject: [PATCH] [RISCV] Add MC layer support for Zicfiss. The patch adds the instructions in Zicfiss extension. Zicfiss extension is to support shadow stack for control flow integrity. Differential Revision: https://reviews.llvm.org/D152793 --- .../test/Preprocessor/riscv-target-features.c | 9 ++ llvm/docs/RISCVUsage.rst | 2 +- llvm/lib/Support/RISCVISAInfo.cpp | 2 + .../RISCV/Disassembler/RISCVDisassembler.cpp | 25 +++++ llvm/lib/Target/RISCV/RISCVFeatures.td | 7 ++ llvm/lib/Target/RISCV/RISCVInstrInfo.td | 9 +- .../lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 71 ++++++++++++ llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 3 + llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 7 ++ llvm/test/MC/RISCV/attribute-arch.s | 3 + llvm/test/MC/RISCV/compressed-zicfiss.s | 53 +++++++++ llvm/test/MC/RISCV/rv32zicfiss-invalid.s | 17 +++ llvm/test/MC/RISCV/rv64zicfiss-invalid.s | 17 +++ llvm/test/MC/RISCV/zicfiss-valid.s | 102 ++++++++++++++++++ llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 + 15 files changed, 323 insertions(+), 5 deletions(-) create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td create mode 100644 llvm/test/MC/RISCV/compressed-zicfiss.s create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-invalid.s create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-invalid.s create mode 100644 llvm/test/MC/RISCV/zicfiss-valid.s diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 2111b3f1c5832b..4229dca8dc3374 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -119,6 +119,7 @@ // CHECK-NOT: __riscv_zfa {{.*$}} // CHECK-NOT: __riscv_zfbfmin {{.*$}} // CHECK-NOT: __riscv_zicfilp {{.*$}} +// CHECK-NOT: __riscv_zicfiss {{.*$}} // CHECK-NOT: __riscv_zicond {{.*$}} // CHECK-NOT: __riscv_zimop {{.*$}} // CHECK-NOT: __riscv_ztso {{.*$}} @@ -1287,3 +1288,11 @@ // RUN: %clang --target=riscv64-unknown-linux-gnu -march=rv64i -E -dM %s \ // RUN: -munaligned-access -o - | FileCheck %s --check-prefix=CHECK-MISALIGNED-FAST // CHECK-MISALIGNED-FAST: __riscv_misaligned_fast 1 + +// RUN: %clang -target riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32izicfiss0p4 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s +// RUN: %clang -target riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64izicfiss0p4 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s +// CHECK-ZICFISS-EXT: __riscv_zicfiss 4000{{$}} diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 3125f2d7c9cfdb..1666f8093c7b7b 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -212,7 +212,7 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma`` LLVM implements assembler support for the `0.8.0 draft specification <https://github.com/riscv/riscv-bfloat16/releases/tag/20230629>`_. -``experimental-zicfilp`` +``experimental-zicfilp``, ``experimental-zicfiss`` LLVM implements the `0.4 draft specification <https://github.com/riscv/riscv-cfi/releases/tag/v0.4.0>`__. ``experimental-zicond`` diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index e71e96e3417e46..83d7162822ad5a 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -194,6 +194,8 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"zfbfmin", RISCVExtensionVersion{0, 8}}, {"zicfilp", RISCVExtensionVersion{0, 4}}, + {"zicfiss", RISCVExtensionVersion{0, 4}}, + {"zicond", RISCVExtensionVersion{1, 0}}, {"zimop", RISCVExtensionVersion{0, 1}}, diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 53e2b6b4d94ea0..8e7ba6a7029c29 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -74,6 +74,17 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo, return MCDisassembler::Success; } +static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo, + uint64_t Address, + const MCDisassembler *Decoder) { + MCRegister Reg = RISCV::X0 + RegNo; + if (Reg != RISCV::X1 && Reg != RISCV::X5) + return MCDisassembler::Fail; + + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder) { @@ -359,6 +370,10 @@ static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address, static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder); +static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn, + uint64_t Address, + const MCDisassembler *Decoder); + #include "RISCVGenDisassemblerTables.inc" static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn, @@ -373,6 +388,16 @@ static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn, return MCDisassembler::Success; } +static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn, + uint64_t Address, + const MCDisassembler *Decoder) { + uint32_t Rs1 = fieldFromInstruction(Insn, 7, 5); + DecodeStatus Result = DecodeGPRX1X5RegisterClass(Inst, Rs1, Address, Decoder); + (void)Result; + assert(Result == MCDisassembler::Success && "Invalid register"); + return MCDisassembler::Success; +} + static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder) { diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index a6e7c15b50e978..2ca35531431462 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -79,6 +79,13 @@ def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">, AssemblerPredicate<(all_of FeatureStdExtZihintntl), "'Zihintntl' (Non-Temporal Locality Hints)">; +def FeatureStdExtZicfiss + : SubtargetFeature<"experimental-zicfiss", "HasStdExtZicfiss", "true", + "'Zicfiss' (Shadow stack)">; +def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">, + AssemblerPredicate<(all_of FeatureStdExtZicfiss), + "'Zicfiss' (Shadow stack)">; + def FeatureStdExtZifencei : SubtargetFeature<"zifencei", "HasStdExtZifencei", "true", "'Zifencei' (fence.i)">; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 099cc0abd14240..a0f7527febc193 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -2139,14 +2139,15 @@ include "RISCVInstrInfoZk.td" include "RISCVInstrInfoV.td" include "RISCVInstrInfoZvk.td" -// Integer -include "RISCVInstrInfoZicbo.td" -include "RISCVInstrInfoZicond.td" - // Compressed include "RISCVInstrInfoC.td" include "RISCVInstrInfoZc.td" +// Integer +include "RISCVInstrInfoZicbo.td" +include "RISCVInstrInfoZicond.td" +include "RISCVInstrInfoZicfiss.td" + //===----------------------------------------------------------------------===// // Vendor extensions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td new file mode 100644 index 00000000000000..631f36624bd8f5 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td @@ -0,0 +1,71 @@ +//===------ RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen -*------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction class templates +//===----------------------------------------------------------------------===// + +class RVC_SSInst<bits<5> rs1val, RegisterClass reg_class, string opcodestr> : + RVInst16<(outs), (ins reg_class:$rs1), opcodestr, "$rs1", [], InstFormatOther> { + let Inst{15-13} = 0b011; + let Inst{12} = 0; + let Inst{11-7} = rs1val; + let Inst{6-2} = 0b00000; + let Inst{1-0} = 0b01; + let DecoderMethod = "decodeCSSPushPopchk"; +} + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +let Predicates = [HasStdExtZicfiss] in { +let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in +def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1), "sspopchk", + "$rs1"> { + let rd = 0; + let imm12 = 0b110011011100; +} // Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 + +let Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +def SSRDP : RVInstI<0b100, OPC_SYSTEM, (outs GPRNoX0:$rd), (ins), "ssrdp", "$rd"> { + let imm12 = 0b110011011100; + let rs1 = 0b00000; +} +} // Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0 + +let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in +def SSPUSH : RVInstR<0b1100111, 0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs2), + "sspush", "$rs2"> { + let rd = 0b00000; + let rs1 = 0b00000; +} +} // Predicates = [HasStdExtZicfiss] + +let Predicates = [HasStdExtZicfiss, HasStdExtCOrZca] in { +let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in +def C_SSPUSH : RVC_SSInst<0b00001, GPRX1, "c.sspush">; + +let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in +def C_SSPOPCHK : RVC_SSInst<0b00101, GPRX5, "c.sspopchk">; +} // Predicates = [HasStdExtZicfiss, HasStdExtCOrZca] + +let Predicates = [HasStdExtZicfiss] in +defm SSAMOSWAP_W : AMO_rr_aq_rl<0b01001, 0b010, "ssamoswap.w">; + +let Predicates = [HasStdExtZicfiss, IsRV64] in +defm SSAMOSWAP_D : AMO_rr_aq_rl<0b01001, 0b011, "ssamoswap.d">; + +//===----------------------------------------------------------------------===/ +// Compress Instruction tablegen backend. +//===----------------------------------------------------------------------===// + +let Predicates = [HasStdExtZicfiss, HasStdExtCOrZca] in { +def : CompressPat<(SSPUSH X1), (C_SSPUSH X1)>; +def : CompressPat<(SSPOPCHK X5), (C_SSPOPCHK X5)>; +} // Predicates = [HasStdExtZicfiss, HasStdExtCOrZca] diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp index a3c19115bd3178..24f8d600f1eafc 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -127,6 +127,9 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const { markSuperRegs(Reserved, RISCV::X27); } + // Shadow stack pointer. + markSuperRegs(Reserved, RISCV::SSP); + assert(checkAllSuperRegsMarked(Reserved)); return Reserved; } diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index c59c9b294d793e..840fd149d68198 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -137,6 +137,8 @@ def GPR : GPRRegisterClass<(add (sequence "X%u", 10, 17), (sequence "X%u", 0, 4))>; def GPRX0 : GPRRegisterClass<(add X0)>; +def GPRX1 : GPRRegisterClass<(add X1)>; +def GPRX5 : GPRRegisterClass<(add X5)>; def GPRNoX0 : GPRRegisterClass<(sub GPR, X0)>; @@ -165,6 +167,8 @@ def SP : GPRRegisterClass<(add X2)>; def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9), (sequence "X%u", 18, 23))>; +def GPRX1X5 : GPRRegisterClass<(add X1, X5)>; + // Floating point registers let RegAltNameIndices = [ABIRegAltName] in { def F0_H : RISCVReg16<0, "f0", ["ft0"]>, DwarfRegNum<[32]>; @@ -591,3 +595,6 @@ foreach m = LMULList in { // Special registers def FFLAGS : RISCVReg<0, "fflags">; def FRM : RISCVReg<0, "frm">; + +// Shadow Stack register +def SSP : RISCVReg<0, "ssp">; diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index f1c080580fe254..214b02690be03d 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -312,5 +312,8 @@ .attribute arch, "rv32i_zicfilp0p4" # CHECK: attribute 5, "rv32i2p1_zicfilp0p4" +.attribute arch, "rv32i_zicfiss0p4" +# CHECK: .attribute 5, "rv32i2p1_zicfiss0p4" + .attribute arch, "rv64i_xsfvfwmaccqqq" # CHECK: attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0_xsfvfwmaccqqq1p0" diff --git a/llvm/test/MC/RISCV/compressed-zicfiss.s b/llvm/test/MC/RISCV/compressed-zicfiss.s new file mode 100644 index 00000000000000..54893555256d14 --- /dev/null +++ b/llvm/test/MC/RISCV/compressed-zicfiss.s @@ -0,0 +1,53 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+c < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+c < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# +# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s + +# CHECK-ASM-AND-OBJ: c.sspopchk t0 +# CHECK-ASM: encoding: [0x81,0x62] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspopchk x5 + +# CHECK-ASM-AND-OBJ: c.sspopchk t0 +# CHECK-ASM: encoding: [0x81,0x62] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspopchk t0 + +# CHECK-ASM-AND-OBJ: c.sspush ra +# CHECK-ASM: encoding: [0x81,0x60] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspush x1 + +# CHECK-ASM-AND-OBJ: c.sspush ra +# CHECK-ASM: encoding: [0x81,0x60] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspush ra + +# CHECK-ASM-AND-OBJ: c.sspush ra +# CHECK-ASM: encoding: [0x81,0x60] +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack) +c.sspush x1 + +# CHECK-ASM-AND-OBJ: c.sspush ra +# CHECK-ASM: encoding: [0x81,0x60] +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack) +c.sspush ra + +# CHECK-ASM-AND-OBJ: c.sspopchk t0 +# CHECK-ASM: encoding: [0x81,0x62] +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack) +c.sspopchk x5 + +# CHECK-ASM-AND-OBJ: c.sspopchk t0 +# CHECK-ASM: encoding: [0x81,0x62] +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack) +c.sspopchk t0 diff --git a/llvm/test/MC/RISCV/rv32zicfiss-invalid.s b/llvm/test/MC/RISCV/rv32zicfiss-invalid.s new file mode 100644 index 00000000000000..1cedcb97e2e7ff --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zicfiss-invalid.s @@ -0,0 +1,17 @@ +# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \ +# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ERR %s + +# CHECK-ERR: error: invalid operand for instruction +sspopchk a1 + +# CHECK-ERR: error: invalid operand for instruction +c.sspush t0 + +# CHECK-ERR: error: invalid operand for instruction +c.sspopchk ra + +# CHECK-ERR: error: invalid operand for instruction +sspush a0 + +# CHECK-ERR: error: invalid operand for instruction +ssrdp zero diff --git a/llvm/test/MC/RISCV/rv64zicfiss-invalid.s b/llvm/test/MC/RISCV/rv64zicfiss-invalid.s new file mode 100644 index 00000000000000..1296940455e850 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zicfiss-invalid.s @@ -0,0 +1,17 @@ +# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \ +# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ERR %s + +# CHECK-ERR: error: invalid operand for instruction +sspopchk a1 + +# CHECK-ERR: error: invalid operand for instruction +c.sspush t0 + +# CHECK-ERR: error: invalid operand for instruction +c.sspopchk ra + +# CHECK-ERR: error: invalid operand for instruction +sspush a0 + +# CHECK-ERR: error: invalid operand for instruction +ssrdp zero diff --git a/llvm/test/MC/RISCV/zicfiss-valid.s b/llvm/test/MC/RISCV/zicfiss-valid.s new file mode 100644 index 00000000000000..fd69d37d7cfa01 --- /dev/null +++ b/llvm/test/MC/RISCV/zicfiss-valid.s @@ -0,0 +1,102 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+a,+experimental-zicfiss -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a,+experimental-zicfiss < %s \ +# RUN: | llvm-objdump --mattr=+a,+experimental-zicfiss -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -defsym=RV64=1 -mattr=+a,+experimental-zicfiss -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM-RV64,CHECK-ASM,CHECK-ASM-AND-OBJ-RV64,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -defsym=RV64=1 -mattr=+a,+experimental-zicfiss < %s \ +# RUN: | llvm-objdump --mattr=+a,+experimental-zicfiss -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ-RV64,CHECK-ASM-AND-OBJ %s +# +# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s +# RUN: not llvm-mc -triple riscv64 -defsym=RV64=1 -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-RV64 %s + +# CHECK-ASM-AND-OBJ: sspopchk ra +# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0xcd] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspopchk x1 + +# CHECK-ASM-AND-OBJ: sspopchk ra +# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0xcd] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspopchk ra + +# CHECK-ASM-AND-OBJ: sspopchk t0 +# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0xcd] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspopchk x5 + +# CHECK-ASM-AND-OBJ: sspopchk t0 +# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0xcd] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspopchk t0 + +# CHECK-ASM-AND-OBJ: sspush ra +# CHECK-ASM: encoding: [0x73,0x40,0x10,0xce] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspush x1 + +# CHECK-ASM-AND-OBJ: sspush ra +# CHECK-ASM: encoding: [0x73,0x40,0x10,0xce] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspush ra + +# check-asm-and-obj: sspush t0 +# check-asm: encoding: [0x73,0x40,0x50,0xce] +# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspush x5 + +# check-asm-and-obj: sspush t0 +# check-asm: encoding: [0x73,0x40,0x50,0xce] +# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspush t0 + +# CHECK-ASM-AND-OBJ: ssrdp ra +# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0xcd] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +ssrdp ra + +# CHECK-ASM-AND-OBJ: ssamoswap.w a4, ra, (s0) +# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x48] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +ssamoswap.w a4, ra, (s0) + +# CHECK-ASM-AND-OBJ: ssamoswap.w.aq a4, ra, (s0) +# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x4c] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +ssamoswap.w.aq a4, ra, (s0) + +# CHECK-ASM-AND-OBJ: ssamoswap.w.rl a4, ra, (s0) +# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x4a] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +ssamoswap.w.rl a4, ra, (s0) + +# CHECK-ASM-AND-OBJ: ssamoswap.w.aqrl a4, ra, (s0) +# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x4e] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +ssamoswap.w.aqrl a4, ra, (s0) + +.ifdef RV64 +# CHECK-ASM-AND-OBJ-RV64: ssamoswap.d a4, ra, (s0) +# CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x48] +# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack) +ssamoswap.d a4, ra, (s0) + +# CHECK-ASM-AND-OBJ-RV64: ssamoswap.d.aq a4, ra, (s0) +# CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x4c] +# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack) +ssamoswap.d.aq a4, ra, (s0) + +# CHECK-ASM-AND-OBJ-RV64: ssamoswap.d.rl a4, ra, (s0) +# CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x4a] +# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack) +ssamoswap.d.rl a4, ra, (s0) + +# CHECK-ASM-AND-OBJ-RV64: ssamoswap.d.aqrl a4, ra, (s0) +# CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x4e] +# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack) +ssamoswap.d.aqrl a4, ra, (s0) +.endif diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp index eeac1e81756583..ccbfa615ea2c0c 100644 --- a/llvm/unittests/Support/RISCVISAInfoTest.cpp +++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -755,6 +755,7 @@ R"(All available -march extensions for RISC-V Experimental extensions zicfilp 0.4 This is a long dummy description + zicfiss 0.4 zicond 1.0 zimop 0.1 zacas 1.0 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
