https://github.com/yetingk updated https://github.com/llvm/llvm-project/pull/98891
>From be805db6c259d255b2ad3f0811bd1428bc8628c5 Mon Sep 17 00:00:00 2001 From: Yeting Kuo <yeting....@sifive.com> Date: Mon, 15 Jul 2024 19:51:55 -0700 Subject: [PATCH 1/2] [RISCV] Bump the version of Zicfilp/Zicfiss to 1.0 Both of them are ratified now. https://wiki.riscv.org/display/HOME/Ratified+Extensions This patch does not set them to non-experimental, since Zicfilp lacks lld support and Zicfiss also lacks compiler-rt/libunwind support. --- clang/test/Driver/print-supported-extensions-riscv.c | 4 ++-- clang/test/Preprocessor/riscv-target-features.c | 12 ++++++------ llvm/docs/RISCVUsage.rst | 2 +- llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++-- llvm/test/CodeGen/RISCV/attributes.ll | 4 ++-- llvm/test/MC/RISCV/attribute-arch.s | 8 ++++---- llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 8 ++++---- 7 files changed, 21 insertions(+), 21 deletions(-) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 875472202d242..88cbcc1296244 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -169,8 +169,8 @@ // CHECK-NEXT: xwchc 2.2 'Xwchc' (WCH/QingKe additional compressed opcodes) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions -// CHECK-NEXT: zicfilp 0.4 'Zicfilp' (Landing pad) -// CHECK-NEXT: zicfiss 0.4 'Zicfiss' (Shadow stack) +// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad) +// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack) // CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions) // CHECK-NEXT: smmpm 1.0 'Smmpm' (Machine-level Pointer Masking for M-mode) // CHECK-NEXT: smnpm 1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 34ec19c70f48a..fd718a126aaa7 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -1643,12 +1643,12 @@ // CHECK-ZFBFMIN-EXT: __riscv_zfbfmin 1000000{{$}} // RUN: %clang --target=riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32i_zicfilp0p4 -E -dM %s \ +// RUN: -march=rv32i_zicfilp1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s // RUN: %clang --target=riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64i_zicfilp0p4 -E -dM %s \ +// RUN: -march=rv64i_zicfilp1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s -// CHECK-ZICFILP-EXT: __riscv_zicfilp 4000{{$}} +// CHECK-ZICFILP-EXT: __riscv_zicfilp 1000000{{$}} // RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32iztso1p0 -E -dM %s \ @@ -1675,12 +1675,12 @@ // CHECK-ZVFBFWMA-EXT: __riscv_zvfbfwma 1000000{{$}} // RUN: %clang -target riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32izicfiss0p4 -E -dM %s \ +// RUN: -march=rv32izicfiss1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s // RUN: %clang -target riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64izicfiss0p4 -E -dM %s \ +// RUN: -march=rv64izicfiss1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s -// CHECK-ZICFISS-EXT: __riscv_zicfiss 4000{{$}} +// CHECK-ZICFISS-EXT: __riscv_zicfiss 1000000{{$}} // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32i_ssnpm1p0 -E -dM %s \ diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index d16753ea09f8f..4474478b6d3f8 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -303,7 +303,7 @@ The primary goal of experimental support is to assist in the process of ratifica LLVM implements the `0.0.5 draft specification <https://github.com/mehnadnerd/riscv-zalasr>`__. ``experimental-zicfilp``, ``experimental-zicfiss`` - LLVM implements the `0.4 draft specification <https://github.com/riscv/riscv-cfi/releases/tag/v0.4.0>`__. + LLVM implements the `1.0 release specification <https://github.com/riscv/riscv-cfi/releases/tag/v1.0>`__. To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`. diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index d3cb2aeab41cb..5a8605aa4a197 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -151,7 +151,7 @@ def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">, "'Zimop' (May-Be-Operations)">; def FeatureStdExtZicfilp - : RISCVExperimentalExtension<"zicfilp", 0, 4, + : RISCVExperimentalExtension<"zicfilp", 1, 0, "'Zicfilp' (Landing pad)", [FeatureStdExtZicsr]>; def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">, @@ -161,7 +161,7 @@ def NoStdExtZicfilp : Predicate<"!Subtarget->hasStdExtZicfilp()">, AssemblerPredicate<(all_of (not FeatureStdExtZicfilp))>; def FeatureStdExtZicfiss - : RISCVExperimentalExtension<"zicfiss", 0, 4, + : RISCVExperimentalExtension<"zicfiss", 1, 0, "'Zicfiss' (Shadow stack)", [FeatureStdExtZicsr, FeatureStdExtZimop]>; def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">, diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 5f82d757a22ec..c9fe1059b1378 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -407,7 +407,7 @@ ; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0" ; RV32ZALASR: .attribute 5, "rv32i2p1_zalasr0p1" ; RV32ZAMA16B: .attribute 5, "rv32i2p1_zama16b1p0" -; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p4_zicsr2p0" +; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp1p0_zicsr2p0" ; RV32ZABHA: .attribute 5, "rv32i2p1_a2p1_zabha1p0" ; RV32SSNPM: .attribute 5, "rv32i2p1_ssnpm1p0" ; RV32SMNPM: .attribute 5, "rv32i2p1_smnpm1p0" @@ -543,7 +543,7 @@ ; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" ; RV64ZACAS: .attribute 5, "rv64i2p1_a2p1_zacas1p0" ; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr0p1" -; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p4_zicsr2p0" +; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp1p0_zicsr2p0" ; RV64ZABHA: .attribute 5, "rv64i2p1_a2p1_zabha1p0" ; RV64SSNPM: .attribute 5, "rv64i2p1_ssnpm1p0" ; RV64SMNPM: .attribute 5, "rv64i2p1_smnpm1p0" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 7d0858ff2ebba..0ba15cfd489cb 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -408,11 +408,11 @@ .attribute arch, "rv32i_xcvbi" # CHECK: attribute 5, "rv32i2p1_xcvbi1p0" -.attribute arch, "rv32i_zicfilp0p4" -# CHECK: attribute 5, "rv32i2p1_zicfilp0p4_zicsr2p0" +.attribute arch, "rv32i_zicfilp1p0" +# CHECK: attribute 5, "rv32i2p1_zicfilp1p0_zicsr2p0" -.attribute arch, "rv32i_zicfiss0p4" -# CHECK: .attribute 5, "rv32i2p1_zicfiss0p4_zicsr2p0_zimop1p0" +.attribute arch, "rv32i_zicfiss1p0" +# CHECK: .attribute 5, "rv32i2p1_zicfiss1p0_zicsr2p0_zimop1p0" .attribute arch, "rv64i_xsfvfwmaccqqq" # CHECK: attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0_xsfvfwmaccqqq1p0" diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index d50079870f7ac..e0a848351d06f 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1026,8 +1026,8 @@ R"(All available -march extensions for RISC-V xwchc 2.2 Experimental extensions - zicfilp 0.4 This is a long dummy description - zicfiss 0.4 + zicfilp 1.0 This is a long dummy description + zicfiss 1.0 zalasr 0.1 smmpm 1.0 smnpm 1.0 @@ -1079,9 +1079,9 @@ R"(Extensions enabled for the given RISC-V target i 2.1 'I' (Base Integer Instruction Set) Experimental extensions - zicfilp 0.4 'Zicfilp' (Landing pad) + zicfilp 1.0 'Zicfilp' (Landing pad) -ISA String: rv64i2p1_zicfilp0p4_zicsr2p0 +ISA String: rv64i2p1_zicfilp1p0_zicsr2p0 )"; // clang-format on >From bd096e2bb34c63f1ad93eac889ba1c3b363ec2fb Mon Sep 17 00:00:00 2001 From: Yeting Kuo <yeting....@sifive.com> Date: Mon, 15 Jul 2024 20:47:07 -0700 Subject: [PATCH 2/2] Update llvm/docs/ReleaseNotes.rst. --- llvm/docs/ReleaseNotes.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index f803a7bb134c4..d92d5e146da21 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -204,6 +204,8 @@ Changes to the RISC-V Backend * The WCH / Nanjing Qinheng Microelectronics QingKe "XW" compressed opcodes are supported under the name "Xwchc". * ``-mcpu=native`` now detects available features with hwprobe (RISC-V Hardware Probing Interface) on Linux 6.4 or later. +======= +* The version of Zicfilp/Zicfiss is updated to 1.0. Changes to the WebAssembly Backend ---------------------------------- _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
