[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

wangpc added a comment. In D70401#4657101 , @jrtc27 wrote: > In D70401#4657098 , @jrtc27 wrote: > >> GCC only ever defines __riscv_32e > > Hm, seems the comments about __riscv_32e were from months ago, ignore them i

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

wangpc added a comment. @craig.topper Thanks! @asb Hi Alex, I'd like to get another approval from you. Are there any more concerns? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70401/new/ https://reviews.llvm.org/D70401 _

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

wangpc added a comment. In D70401#4655408 , @asb wrote: > First of all, thank you to everyone who has been trying to nudge this forward > and apologies it must have been a frustrating experience. > > I appreciate there are users who want to see this and I

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

wangpc added a comment. @asb @kito-cheng @jrtc27 @craig.topper Can I commit this since the support of RVE is really of great importance for some downstreams? If there are some problems, I will be there to fix them. If we all agree with this, I will mark RVE as exprimental and commit it then. R

[PATCH] D154576: [RISCV] RISCV vector calling convention (1/2)

wangpc added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVCallingConv.td:52 // Same as CSR_Interrupt, but including all 64-bit FP registers. def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt, (sequence "F%u_D

[PATCH] D159479: [ASTImport]CXXBoolLiteralExpr should be handled explicitly in statement comparation

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGb0ea2790c41d: [ASTImport]CXXBoolLiteralExpr should be handled explicitly in statement… (authored by jcsxky, committed by wangpc). Repository: rG L

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

wangpc added a comment. In D70401#4635875 , @koute wrote: > I know that there are still open issues regarding the psABI, but considering > how slow it's been going, couldn't we merge this in anyway and mark it as > experimental and subject to change? Ple

[PATCH] D159145: [RISCV] Don't add -unaligned-scalar-mem to target features by default.

wangpc accepted this revision. wangpc added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D159145/new/ https://reviews.llvm.org/D159145 __

[PATCH] D159145: [RISCV] Don't add -unaligned-scalar-mem to target features by default.

wangpc added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVProcessors.td:185 + FeatureStdExtZbb, + FeatureUnalignedScalarMem], [TuneSiFive7, --

[PATCH] D159145: [RISCV] Don't add -unaligned-scalar-mem to target features by default.

wangpc added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVProcessors.td:185 + FeatureStdExtZbb, + FeatureUnalignedScalarMem], [TuneSiFive7, --

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc added a comment. In D112921#4624674 , @aaron.ballman wrote: > Because the issues have been ongoing for a few hours now, I think it'd make > sense to revert these changes while trying to determine what the appropriate > fix is. @wangpc would you

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc added a comment. In D112921#4624141 , @nikic wrote: > FYI this resulted in some pretty wild code size swings, in particular between > -10% and -15% for tramp3d-v4 > (http://llvm-compile-time-tracker.com/compare.php?from=6cde64a94986165547ae5237ac

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc added a comment. In D112921#4624547 , @jhuber6 wrote: > This caused some linking errors with the GPU libc test suite, see > https://lab.llvm.org/staging/#/builders/247/builds/5659. > > clang++: error: ld.lld command failed with exit code 1 (use

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc added a comment. In D112921#4624488 , @thakis wrote: > Looks like this breaks tests on windows: > http://45.33.8.238/win/83485/step_7.txt > > Please take a look and revert for now if it takes a while to fix. > > (Also, if the patch doesn't already

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

This revision was not accepted when it landed; it landed in state "Needs Review". This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG2916b125f686: [clang] Enable sized deallocation by default in C++1

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc added a comment. Thanks all! I will land this patch later. If there are some failures (especially `libcxx` part @Mordante :-) ), please help me to fix them. Thanks in advance! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https:

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 554197. wangpc marked 2 inline comments as done. wangpc added a comment. Rebase. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 Files: clang-tools-extra/clangd/unit

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc marked 2 inline comments as done. wangpc added inline comments. Comment at: clang/include/clang/Basic/SizedDeallocation.h:23 +namespace clang { +inline llvm::VersionTuple sizedDeallocMinVersion(llvm::Triple::OSType OS) { + switch (OS) { MaskRay wrote: > D

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc added a comment. In D112921#4621019 , @aaron.ballman wrote: > In D112921#4620399 , @wangpc wrote: > >> Gentle ping. Can I move forward and land this? > > What name and email address would you like us to us

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc added a comment. Gentle ping. Can I move forward and land this? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 ___ cfe-commits mailing list cfe-commits@

[PATCH] D156693: [clang][ASTImporter]Skip check depth of friend template parameter

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG07ab5140080e: [clang][ASTImporter]Skip check depth of friend template parameter (authored by jcsxky, committed by wangpc). Repository: rG LLVM Git

[PATCH] D151730: [RISCV] Support target attribute for function

wangpc added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:376 + + if (AttrString.startswith("+") || AttrString.startswith("-")) { +// EXTENSION like arch=+v,+zbb,-c `-` is removed in https://github.com/riscv-non-isa/riscv-c-api-doc

[PATCH] D142144: [RISCV][Driver] Add -mrvv-vector-bits= option similar to -msve-vector-bits=

wangpc added inline comments. Herald added subscribers: jobnoorman, sunshaoce. Comment at: clang/test/Driver/riscv-rvv-vector-bits.c:43 +// RUN: %clang -c %s -### --target=riscv64-linux-gnu -march=rv64gcv \ +// RUN: -mrvv-vector-bits=64 2>&1 | FileCheck --check-prefix=CHECK-BAD

[PATCH] D155647: [RISCV] Add C intrinsics for scalar bitmanip and crypto

wangpc accepted this revision. wangpc added a comment. This revision is now accepted and ready to land. Herald added a subscriber: sunshaoce. LGTM if the proposal is merged. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155647/new/ https://reviews.

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc added a comment. @ldionne Sorry for bothering, what do you think about landing this patch? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 ___ cfe-commit

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 551890. wangpc added a comment. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 Files: clang-tools-extra/clangd/unittests/FindTargetTests.cpp clang-tools-ex

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 551702. wangpc added a comment. - Rebase. - Remove abilist changes. - Add clang-18. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 Files: clang-tools-extra/clangd/u

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 551367. wangpc added a comment. Rebase and fix failed tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 Files: clang-tools-extra/clangd/unittests/FindTargetTest

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc added a comment. In D112921#4595918 , @Mordante wrote: > In D112921#4594092 , @wangpc wrote: > >> - Rebase. >> - Update tests, remove clang-17. > > The removal of the markers in the libc++ tests breaks thes

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 550983. wangpc marked 10 inline comments as done. wangpc added a comment. - Rebase. - Update tests, remove clang-17. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 Fi

[PATCH] D157680: [X86]Support options -mno-gather -mno-scatter

wangpc added inline comments. Comment at: clang/lib/Driver/ToolChains/Clang.cpp:7527 + // -mno-gather, -mno-scatter support + if (Args.hasArg(options::OPT_mno_gather)) { +CmdArgs.push_back("-target-feature"); Put these in `clang/lib/Driver/ToolChains/Arch/X

[PATCH] D149017: [RISCV] Rewrite all found class-based subroutines to functions

wangpc added a comment. In D149017#4579179 , @zixuan-wu wrote: > Is it going to commit? This patch is stuck since the patch to support function/lambda is WIP (I may not work on it recently). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST AC

[PATCH] D157476: [RISCV] Fix wrong type prototype of RVVSlideOneBuiltinSet

This revision was automatically updated to reflect the committed changes. Closed by commit rG5a3753f35632: [RISCV] Fix wrong type prototype of RVVSlideOneBuiltinSet (authored by wangpc). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D157476/new/ http

[PATCH] D157580: [RISCV][NFC] Use named arguments in newly added changes

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGa2684f76204c: [RISCV][NFC] Use named arguments in newly added changes (authored by wangpc). Repository: rG LLVM Github Monorepo CHANGES SINCE LAS

[PATCH] D157476: [RISCV] Fix wrong type prototype of RVVSlideOneBuiltinSet

wangpc added a comment. In D157476#4575656 , @eopXD wrote: > You do agree with my latest comment that `long` is the righteous fix, right? > :) Oh sorry, somwhow I missed it. I still think that using the element type is the right way. Because user will

[PATCH] D157476: [RISCV] Fix wrong type prototype of RVVSlideOneBuiltinSet

wangpc added a comment. > I still think that modifying the generated test cases is needed. If you find > it tedious, may I open up a revision that resolves the problem while adding > you as co-author since you gave this problem the first try? @eopXD Yeah, it's OK! I will hand over the work to y

[PATCH] D157580: [RISCV][NFC] Use named arguments in newly added changes

wangpc created this revision. wangpc added reviewers: 4vtomat, craig.topper. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzhen

[PATCH] D157476: [RISCV] Fix wrong type prototype of RVVSlideOneBuiltinSet

wangpc added a comment. In D157476#4572135 , @eopXD wrote: > I mean > > vint8mf8_t test_vslide1up_vx_i8mf8(vint8mf8_t src, int8_t value, size_t vl) > { > return __riscv_vslide1up_vx_i8mf8(src, value, vl); > } > > should change into > > vint8mf8

[PATCH] D157476: [RISCV] Fix wrong type prototype of RVVSlideOneBuiltinSet

wangpc added a comment. In D157476#4572073 , @eopXD wrote: > I guess we need to update the test cases too, are you able to generate them > by modifying the the generator under `riscv-non-isa/rvv-intrinsic-doc`? For this patch, we don't need to update te

[PATCH] D157476: [RISCV] Fix wrong type prototype of RVVSlideOneBuiltinSet

wangpc created this revision. wangpc added reviewers: kito-cheng, eopXD, craig.topper. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jo

[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG23ce5368409c: [RISCV] Support -m[no-]strict-align options (authored by wangpc). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION h

[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

wangpc updated this revision to Diff 546772. wangpc added a comment. Rebase since `ReleaseNotes.rst` is changed. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155456/new/ https://reviews.llvm.org/D155456 Files: clang/docs/ReleaseNotes.rst clan

[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

wangpc added a comment. Thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155456/new/ https://reviews.llvm.org/D155456 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/c

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 546760. wangpc added a comment. Rebase. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 Files: clang-tools-extra/clangd/unittests/FindTargetTests.cpp clang-tools-e

[PATCH] D156779: [RISCV] Use correct LMUL!=1 types for __attribute__((riscv_rvv_vector_bits(N)))

This revision was automatically updated to reflect the committed changes. Closed by commit rGedb5056300bb: [RISCV] Use correct LMUL!=1 types for __attribute__((riscv_rvv_vector_bits(N))) (authored by wangpc). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.

[PATCH] D156779: [RISCV] Use correct LMUL!=1 types for __attribute__((riscv_rvv_vector_bits(N)))

wangpc created this revision. wangpc added a reviewer: craig.topper. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc2

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 545006. wangpc added a comment. - Rebase. - Unsupport clang-18. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 Files: clang-tools-extra/clangd/unittests/FindTargetT

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc added a comment. In D112921#4536088 , @Mordante wrote: > In D112921#4535716 , @wangpc wrote: > >> In D112921#4532378 , @Mordante >> wrote: >> >>> In D112921#453091

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 544640. wangpc added a comment. - Remove usages of `-fsized-deallocation` in some tests. - Rebase. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 Files: clang-tools

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc added a comment. In D112921#4532378 , @Mordante wrote: > In D112921#4530916 , @wangpc wrote: > >> In D112921#4529182 , @Mordante >> wrote: >> >>> I noticed some of

[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies

wangpc added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:948 - // TODO: The 'q' extension requires rv64. - // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'. I think the comment is outdated here. `E` can be combined with all

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc added a comment. In D112921#4529182 , @Mordante wrote: > I noticed some of the CI jobs are still failing with the patch, I didn't look > into them. I don't think they are related to this patch, so I rebased again. If still failed, I will try to

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 543828. wangpc added a comment. Rebase. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 Files: clang-tools-extra/clangd/unittests/FindTargetTests.cpp clang-tools-e

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc added a comment. Ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi

[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

wangpc added inline comments. Comment at: clang/test/Driver/riscv-features.c:41 +// DEFAULT: "-target-feature" "-unaligned-scalar-mem" +// DEFAULT-NOT: "-target-feature" "+unaligned-scalar-mem" + arichardson wrote: > This looks a bit fragile, can we just check al

[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

wangpc planned changes to this revision. wangpc added a comment. I don't have any thoughts on this patch now. In D125765#4511637 , @eopXD wrote: > Sorry for the late reply, I missed this in may mails. > > I see that the motivation start from where you sp

[PATCH] D155647: [RISCV] Add C intrinsics for scalar crypto

wangpc added a comment. Can we run mem2reg pass in RUNs just like RVV tests (maybe another cleanup patch)? I think there are a lot of noises in CHECKS. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155647/new/ https://reviews.llvm.org/D155647 ___

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 541415. wangpc added a comment. Rebase and fix libcxx tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 Files: clang-tools-extra/clangd/unittests/FindTargetTest

[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

wangpc updated this revision to Diff 541374. wangpc added a comment. Update ReleaseNotes. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155456/new/ https://reviews.llvm.org/D155456 Files: clang/docs/ReleaseNotes.rst clang/include/clang/Driver/

[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

wangpc updated this revision to Diff 540994. wangpc added a comment. Remove includes. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155456/new/ https://reviews.llvm.org/D155456 Files: clang/include/clang/Driver/Options.td clang/lib/Driver/Tool

[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

wangpc updated this revision to Diff 540989. wangpc added a comment. Add `+unaligned-vector-mem` if V exists. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155456/new/ https://reviews.llvm.org/D155456 Files: clang/include/clang/Driver/Options.td

[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

wangpc created this revision. wangpc added reviewers: reames, craig.topper, asb, kito-cheng. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edw

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 540915. wangpc added a comment. - Add comments. - clang-format. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 Files: clang-tools-extra/clangd/unittests/FindTargetT

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 540913. wangpc added a comment. - Rebase - Fix tests. @ldionne I don't know the details about DriverKit so I assumed that sized deallocation is available just like aligned allocation. @Mordante I will leave libcxx tests to folks who are more familiar with th

[PATCH] D154596: [RISCV] Fix required features checking with empty string

wangpc accepted this revision. wangpc added a comment. LGTM as well. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154596/new/ https://reviews.llvm.org/D154596 ___ cfe-commits mailing list cfe-commits@li

[PATCH] D154596: [RISCV] Fix required features checking with empty string

wangpc added a comment. In D154596#4499718 , @Jim wrote: > In D154596#4499647 , @wangpc wrote: > >> Can you give an example of intrinsic that doesn't require any extra >> extension enabled? > > Like read/write cs

[PATCH] D154596: [RISCV] Fix required features checking with empty string

wangpc added a comment. Can you give an example of intrinsic that doesn't require any extra extension enabled? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154596/new/ https://reviews.llvm.org/D154596

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

wangpc added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:908 static const MCPhysReg CSRegs[] = { RISCV::X1, /* ra */ RISCV::X5, RISCV::X6, RISCV::X7, /* t0-t2 */ zixuan-wu wrote: > Hi, @wangpc it's

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

pcwang-thead added a comment. In D70401#4411560 , @david-sawatzke wrote: > Thank you for the reply, I've compiled this with the most recent patch and > also didn't see a problem (but can't get it running with rustc). Building the > .ll with the older pa

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

pcwang-thead added a comment. In D70401#4409782 , @david-sawatzke wrote: > Hey I've tried using this patch (roughly following > https://noxim.xyz/blog/rust-ch32v003/). > > It uses the older version of this patch for the rust llvm version (here the > llv

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

pcwang-thead added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:41 +// Helper function to get the largest LMUL from MxList +// Precondition: MxList is sorted in ascending LMUL order. michaelmaitland wrote: > michaelmaitland wrote: > > pc

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

pcwang-thead accepted this revision. pcwang-thead added a comment. LGTM. Though I don't like the way that we need to loop `MxList` again when defining scheduling model, I think this can be a good practice to define RVV scheduling model in current TableGen's grammar. Comment a

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

pcwang-thead added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td:15 +class SiFive7IsWorstCaseMX MxList> { + string LLMUL = LargestLMUL.r; + bit c = !eq(mx, LLMUL); I think I have fixed the issue that `defar` can't refer to template arg

[PATCH] D149017: [RISCV] Rewrite all found class-based subroutines to functions

pcwang-thead added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:703 class VPseudoUSLoadMask : - Pseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$merge, + Pseudo<(outs GetVRegNoV0'(RetClass):$rd), + (ins Ge

[PATCH] D149017: [RISCV] Rewrite RVV-related class-based subroutines to functions

pcwang-thead updated this revision to Diff 516224. pcwang-thead added a comment. Herald added a project: clang. Herald added a subscriber: cfe-commits. Rewrite all found subroutines. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149017/new/ https:/

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

pcwang-thead added a comment. In D70401#4226549 , @recallmenot wrote: > In D70401#4205333 , @pcwang-thead > wrote: > >> In D70401#4204511 , @recallmenot >> wrote: >> >>> Hi

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

pcwang-thead added a comment. In D70401#4204511 , @recallmenot wrote: > Hi, I'm working on CH32V003 for rust and it uses RV32EC core. > I tried replacing my distros llvm and clang with a patched version of this > like this: > > git clone https://aur.arc

[PATCH] D144853: [Clang][RISCV] Add CMake options to configure default CPU

pcwang-thead abandoned this revision. pcwang-thead added a comment. In D144853#4157629 , @MaskRay wrote: > I object to this change which further complicates the build system and makes > the difference difficult to observe by users. > If your `clang` exec

[PATCH] D144853: [Clang][RISCV] Add CMake options to configure default CPU

pcwang-thead added a comment. In D144853#4155482 , @asb wrote: > If this is a useful thing to have, would it make more sense as a > target-independent option? Yes, I agree. I need to do some researches here to figure out if all targets have the same b

[PATCH] D144853: [Clang][RISCV] Add CMake options to configure default CPU

pcwang-thead updated this revision to Diff 501035. pcwang-thead added a comment. Simplify code. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D144853/new/ https://reviews.llvm.org/D144853 Files: clang/CMakeLists.txt clang/include/clang/Config/c

[PATCH] D144853: [Clang][RISCV] Add CMake options to configure default CPU

pcwang-thead created this revision. pcwang-thead added reviewers: asb, jrtc27, kito-cheng, craig.topper, reames, eopXD. Herald added subscribers: luke, VincentWu, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, Mar

[PATCH] D144696: [RISCV][NFC] Package version number information using RISCVExtensionVersion.

pcwang-thead added a comment. In D144696#4149706 , @craig.topper wrote: > How much of the existing vector code in the backend including tablegen can be > reused for 0.71? How much of the intrinsic interface can be used? If we’re > talking about complet

[PATCH] D144696: [RISCV][NFC] Package version number information using RISCVExtensionVersion.

pcwang-thead added a comment. > My intention is to support RVV0.71, since specific cpu's exist for the > XuanTie C900 series. In LLVM use Feature to distinguish between different > versions of extensions. I am considering how to solve this problem, using > multiple `.td` files in the worst case

[PATCH] D143549: [clang][AIX] Remove test for the default OpenMP runtime

This revision was automatically updated to reflect the committed changes. Closed by commit rG5ae99be03772: [clang][AIX] Remove test for the default OpenMP runtime (authored by pcwang-thead). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D143549/new/

[PATCH] D143549: [clang][AIX] Remove test for the default OpenMP runtime

pcwang-thead created this revision. pcwang-thead added reviewers: xingxue, daltenty, jdoerfert. Herald added subscribers: guansong, yaxunl. Herald added a project: All. pcwang-thead requested review of this revision. Herald added subscribers: cfe-commits, sstefan1. Herald added a project: clang. T

[PATCH] D131230: [RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values

pcwang-thead added a comment. I have reverted it in 3df16e6f6e4d933f3839003e29b8a4b70e4c7ec8 . Please update `CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c` and reland this patch again. Repository: rG LLVM Github Monorep

[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

pcwang-thead added inline comments. Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c:33 +// RV32: !2 = !{i32 1, !"SmallDataLimit", i32 0} +// RV32: !3 = !{!"clang version 16.0.0 (g...@github.com:llvm/llvm-project.git e80f0cc0a318fe8473ba460d6a16166d81b303b1)"} +// RV3

[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

pcwang-thead added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1579 + llvm::Function *F = +CGM.getIntrinsic(llvm::Intrinsic::read_register, {Int64Ty}); + return Builder.CreateCall(F, Metadata); craig.topper wrote: > pc

[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

pcwang-thead accepted this revision. pcwang-thead added a comment. This revision is now accepted and ready to land. The code is OK to me, except that a few small comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1579 + llvm::Function *F = +CGM.getIntr

[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

pcwang-thead added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1565 + unsigned long __rv = 0; + __asm__ __volatile__ ("csrr\t%0, vlenb" : "=r"(__rv) : : "memory"); + return __rv; Inline assembly may not be elegant since it can't be o

[PATCH] D141032: [Clang][RISCV] Expose vlenb to vread_csr

pcwang-thead added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1559 __asm__ __volatile__ ("csrw\tvcsr, %z0" : : "rJ"(__value) : "memory"); break; } Should we report errors if `vwrite_csr(RVV_VLENB, some_value)`? Repos

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

pcwang-thead added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:568 -def : ProcessorModel<"generic-rv32", NoSchedModel, [Feature32Bit]>; -def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; +class RISCVProcessorModelPROCRISCVProcessorModel? RISCVP

[PATCH] D137838: [Support] Move TargetParsers to new component

pcwang-thead added inline comments. Comment at: llvm/include/llvm/Support/RISCVISAInfo.h:10 +/// \file +/// This header is deprecated in favour of `llvm/Support/RISCVISAInfo.h`. +/// zixuan-wu wrote: > I think there is a typo that should be 'in favour of > `llvm

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

pcwang-thead added a comment. > @pcwang-thead, may I ask you to own these further optimisations of the > generative process, and submit a patch for it after the current patch lands? > I'd happily review it! > > The reason I am asking this is because the current patch is mostly dealing > with ma

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

pcwang-thead added a comment. In D137517#4012307 , @craig.topper wrote: > In D137517#4012298 , @pcwang-thead > wrote: > >> In D137517#4009175 , @fpetrogalli >> wrote: >

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

pcwang-thead added a comment. In D137517#4009175 , @fpetrogalli wrote: > @pcwang-thead, I addressed some of your comments. > > The value of `EnumFeatures` is now computed dynamicaly from the > `Features` field of the `Processor` class. Thanks! That soun

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

pcwang-thead added a comment. In D112921#4003939 , @Romain-Geissler-1A wrote: > Hi, > > Is there any update about this ? Currently, no. If someone is interesting in this, please feel free to commandeer. :-) Repository: rG LLVM Github Monorepo CHANG

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

pcwang-thead added a comment. In D70401#3948829 , @StephenFan wrote: > In D70401#3873874 , @pcwang-thead > wrote: > >> In D70401#3873347 , @luojia wrote: >> >>> Hello! Any f

[PATCH] D137044: [ClangFE] Add support for option -mno-pic-data-is-text-relative

pcwang-thead added a comment. The test `clang/test/Driver/pic.c` failed when we compiled Clang/LLVM with `-DCLANG_DEFAULT_PIE_ON_LINUX=False`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137044/new/ https://reviews.llvm.org/D137044

[PATCH] D137517: [TargetSupport] Generate the defs for RISCV CPUs using llvm-tblgen.

pcwang-thead added a comment. A rough implementation just for your reference: diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp index 47e11b9a1eab..f91f969c2b17 100644 --- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp +++ b/llvm/

  1   2   >