pcwang-thead updated this revision to Diff 516224.
pcwang-thead added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.
Rewrite all found subroutines.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D149017/new/
https://reviews.llvm.org/D149017
Files:
clang/include/clang/Basic/riscv_vector.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
llvm/lib/Target/RISCV/RISCVScheduleV.td
Index: llvm/lib/Target/RISCV/RISCVScheduleV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -18,24 +18,24 @@
// Used for widening floating-point Reduction as it doesn't contain MF8.
defvar SchedMxListFWRed = SchedMxListF;
-class SchedSEWSet<string mx> {
- list<int> val = !cond(!eq(mx, "M1"): [8, 16, 32, 64],
- !eq(mx, "M2"): [8, 16, 32, 64],
- !eq(mx, "M4"): [8, 16, 32, 64],
- !eq(mx, "M8"): [8, 16, 32, 64],
- !eq(mx, "MF2"): [8, 16, 32],
- !eq(mx, "MF4"): [8, 16],
- !eq(mx, "MF8"): [8]);
+function SchedSEWSet(string mx): list<int> {
+ return !cond(!eq(mx, "M1"): [8, 16, 32, 64],
+ !eq(mx, "M2"): [8, 16, 32, 64],
+ !eq(mx, "M4"): [8, 16, 32, 64],
+ !eq(mx, "M8"): [8, 16, 32, 64],
+ !eq(mx, "MF2"): [8, 16, 32],
+ !eq(mx, "MF4"): [8, 16],
+ !eq(mx, "MF8"): [8]);
}
// For floating-point instructions, SEW won't be 8.
-class SchedSEWSetF<string mx> {
- list<int> val = !cond(!eq(mx, "M1"): [16, 32, 64],
- !eq(mx, "M2"): [16, 32, 64],
- !eq(mx, "M4"): [16, 32, 64],
- !eq(mx, "M8"): [16, 32, 64],
- !eq(mx, "MF2"): [16, 32],
- !eq(mx, "MF4"): [16]);
+function SchedSEWSetF(string mx): list<int> {
+ return !cond(!eq(mx, "M1"): [16, 32, 64],
+ !eq(mx, "M2"): [16, 32, 64],
+ !eq(mx, "M4"): [16, 32, 64],
+ !eq(mx, "M8"): [16, 32, 64],
+ !eq(mx, "MF2"): [16, 32],
+ !eq(mx, "MF4"): [16]);
}
// Define multiclasses to define SchedWrite, SchedRead, WriteRes, and
@@ -79,14 +79,14 @@
multiclass LMULSEWSchedWritesImpl<string name, list<string> MxList, bit isF = 0> {
def name # "_WorstCase" : SchedWrite;
foreach mx = MxList in {
- foreach sew = !if(isF, SchedSEWSetF<mx>.val, SchedSEWSet<mx>.val) in
+ foreach sew = !if(isF, SchedSEWSetF(mx), SchedSEWSet(mx)) in
def name # "_" # mx # "_E" # sew : SchedWrite;
}
}
multiclass LMULSEWSchedReadsImpl<string name, list<string> MxList, bit isF = 0> {
def name # "_WorstCase" : SchedRead;
foreach mx = MxList in {
- foreach sew = !if(isF, SchedSEWSetF<mx>.val, SchedSEWSet<mx>.val) in
+ foreach sew = !if(isF, SchedSEWSetF(mx), SchedSEWSet(mx)) in
def name # "_" # mx # "_E" # sew : SchedRead;
}
}
@@ -94,7 +94,7 @@
bit isF = 0> {
def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
foreach mx = !if(isF, SchedMxListF, SchedMxList) in {
- foreach sew = !if(isF, SchedSEWSetF<mx>.val, SchedSEWSet<mx>.val) in
+ foreach sew = !if(isF, SchedSEWSetF(mx), SchedSEWSet(mx)) in
def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>;
}
}
@@ -102,7 +102,7 @@
bit isF = 0> {
def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>;
foreach mx = !if(isF, SchedMxListF, SchedMxList) in {
- foreach sew = !if(isF, SchedSEWSetF<mx>.val, SchedSEWSet<mx>.val) in
+ foreach sew = !if(isF, SchedSEWSetF(mx), SchedSEWSet(mx)) in
def : ReadAdvance<!cast<SchedRead>(name # "_" # mx # "_E" # sew), val, writes>;
}
}
Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -345,22 +345,22 @@
// LMUL == 1, NF = 2, 3, 4, 5, 6, 7, 8
// LMUL == 2, NF = 2, 3, 4
// LMUL == 4, NF = 2
-class NFList<int lmul> {
- list<int> L = !cond(!eq(lmul, 1): [2, 3, 4, 5, 6, 7, 8],
- !eq(lmul, 2): [2, 3, 4],
- !eq(lmul, 4): [2],
- !eq(lmul, 8): []);
+function NFList(int lmul): list<int> {
+ return !cond(!eq(lmul, 1): [2, 3, 4, 5, 6, 7, 8],
+ !eq(lmul, 2): [2, 3, 4],
+ !eq(lmul, 4): [2],
+ !eq(lmul, 8): []);
}
// Generate [start, end) SubRegIndex list.
-class SubRegSet<int nf, int lmul> {
- list<SubRegIndex> L = !foldl([]<SubRegIndex>,
- [0, 1, 2, 3, 4, 5, 6, 7],
- AccList, i,
- !listconcat(AccList,
- !if(!lt(i, nf),
- [!cast<SubRegIndex>("sub_vrm" # lmul # "_" # i)],
- [])));
+function SubRegSet(int nf, int lmul): list<SubRegIndex> {
+ return !foldl([]<SubRegIndex>,
+ [0, 1, 2, 3, 4, 5, 6, 7],
+ AccList, i,
+ !listconcat(AccList,
+ !if(!lt(i, nf),
+ [!cast<SubRegIndex>("sub_vrm" # lmul # "_" # i)],
+ [])));
}
// Collect the valid indexes into 'R' under NF and LMUL values from TUPLE_INDEX.
@@ -378,8 +378,8 @@
// (1 + i) x 4 <= 28
// The class will return [12, 16, 20, 24, 28, 8].
//
-class IndexSet<int tuple_index, int nf, int lmul, bit isV0 = false> {
- list<int> R =
+function IndexSet(int tuple_index, int nf, int lmul, bit isV0 = false): list<int> {
+ return
!foldl([]<int>,
!if(isV0, [0],
!cond(
@@ -405,19 +405,19 @@
// ([ V8M4, V12M4, V16M4, V20M4, V24M4, V4M4],
// [V12M4, V16M4, V20M4, V24M4, V28M4, V8M4])
//
-class VRegList<list<dag> LIn, int start, int nf, int lmul, bit isV0> {
- list<dag> L =
+function VRegList(list<dag> LIn, int start, int nf, int lmul, bit isV0): list<dag> {
+ return
!if(!ge(start, nf),
LIn,
!listconcat(
[!dag(add,
- !foreach(i, IndexSet<start, nf, lmul, isV0>.R,
+ !foreach(i, IndexSet(start, nf, lmul, isV0),
!cast<Register>("V" # i # !cond(!eq(lmul, 2): "M2",
!eq(lmul, 4): "M4",
true: ""))),
!listsplat("",
- !size(IndexSet<start, nf, lmul, isV0>.R)))],
- VRegList<LIn, !add(start, 1), nf, lmul, isV0>.L));
+ !size(IndexSet(start, nf, lmul, isV0))))],
+ VRegList(LIn, !add(start, 1), nf, lmul, isV0)));
}
// Vector registers
@@ -468,13 +468,13 @@
foreach m = [1, 2, 4] in {
- foreach n = NFList<m>.L in {
+ foreach n = NFList(m) in {
def "VN" # n # "M" # m # "NoV0": RegisterTuples<
- SubRegSet<n, m>.L,
- VRegList<[], 0, n, m, false>.L>;
+ SubRegSet(n, m),
+ VRegList([], 0, n, m, false)>;
def "VN" # n # "M" # m # "V0" : RegisterTuples<
- SubRegSet<n, m>.L,
- VRegList<[], 0, n, m, true>.L>;
+ SubRegSet(n, m),
+ VRegList([], 0, n, m, true)>;
}
}
@@ -569,7 +569,7 @@
(sequence "V%u", 0, 7)), 1>;
foreach m = LMULList.m in {
- foreach nf = NFList<m>.L in {
+ foreach nf = NFList(m) in {
def "VRN" # nf # "M" # m # "NoV0": VReg<[untyped],
(add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")),
!mul(nf, m)>;
Index: llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
@@ -27,8 +27,8 @@
def VCIX_XVV : VCIXType<0b1010>;
def VCIX_XVW : VCIXType<0b1111>;
-class SwapVCIXIns<dag funct6, dag rd, dag rs2, dag rs1, bit swap> {
- dag Ins = !con(funct6, !if(swap, rs2, rd), !if(swap, rd, rs2), rs1);
+function SwapVCIXIns(dag funct6, dag rd, dag rs2, dag rs1, bit swap): dag {
+ return !con(funct6, !if(swap, rs2, rd), !if(swap, rd, rs2), rs1);
}
class RVInstVCCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins,
@@ -88,14 +88,14 @@
dag Outs = !if(!not(HaveOutputDst), (outs),
!if(!or(!eq(type, VCIX_XVV), !eq(type, VCIX_XVW)),
(outs TyRd:$rd_wb), (outs TyRd:$rd)));
- dag Ins = SwapVCIXIns<!if(!ne(TyRs1, FPR32), (ins uimm2:$funct6_lo2),
+ dag Ins = SwapVCIXIns(!if(!ne(TyRs1, FPR32), (ins uimm2:$funct6_lo2),
(ins uimm1:$funct6_lo1)),
!if(!and(HaveOutputDst, !or(!eq(type, VCIX_X),
!eq(type, VCIX_XV))),
(ins), (ins TyRd:$rd)),
(ins TyRs2:$rs2),
(ins TyRs1:$rs1),
- !if(!eq(type, VCIX_X), 1, 0)>.Ins;
+ !if(!eq(type, VCIX_X), 1, 0));
string Prototype = !if(!eq(type, VCIX_X), "$funct6_lo2, $rs2, $rd, $rs1",
!if(!ne(TyRs1, FPR32), "$funct6_lo2, $rd, $rs2, $rs1",
"$funct6_lo1, $rd, $rs2, $rs1"));
Index: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -976,7 +976,7 @@
multiclass VPatConvertFP2IVL_V<SDPatternOperator vop, string instruction_name> {
foreach fvti = AllFloatVectors in {
- defvar ivti = GetIntVTypeInfo<fvti>.Vti;
+ defvar ivti = GetIntVTypeInfo(fvti);
def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
(fvti.Mask V0),
VLOpFrag)),
@@ -988,7 +988,7 @@
multiclass VPatConvertFP2I_RM_VL_V<SDNode vop, string instruction_name> {
foreach fvti = AllFloatVectors in {
- defvar ivti = GetIntVTypeInfo<fvti>.Vti;
+ defvar ivti = GetIntVTypeInfo(fvti);
def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
(fvti.Mask V0), (XLenVT timm:$frm),
VLOpFrag)),
@@ -1001,7 +1001,7 @@
multiclass VPatConvertI2FPVL_V<SDPatternOperator vop, string instruction_name> {
foreach fvti = AllFloatVectors in {
- defvar ivti = GetIntVTypeInfo<fvti>.Vti;
+ defvar ivti = GetIntVTypeInfo(fvti);
def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),
(ivti.Mask V0),
VLOpFrag)),
@@ -1013,7 +1013,7 @@
multiclass VPatConvertI2FP_RM_VL_V<SDNode vop, string instruction_name> {
foreach fvti = AllFloatVectors in {
- defvar ivti = GetIntVTypeInfo<fvti>.Vti;
+ defvar ivti = GetIntVTypeInfo(fvti);
def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),
(ivti.Mask V0), (XLenVT timm:$frm),
VLOpFrag)),
@@ -1028,7 +1028,7 @@
multiclass VPatWConvertFP2IVL_V<SDPatternOperator vop, string instruction_name> {
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
- defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
+ defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti);
def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
(fvti.Mask V0),
VLOpFrag)),
@@ -1041,7 +1041,7 @@
multiclass VPatWConvertFP2I_RM_VL_V<SDNode vop, string instruction_name> {
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
- defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
+ defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti);
def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
(fvti.Mask V0), (XLenVT timm:$frm),
VLOpFrag)),
@@ -1113,7 +1113,7 @@
string instruction_name> {
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
- defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
+ defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti);
def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1),
(iwti.Mask V0),
VLOpFrag)),
@@ -1126,7 +1126,7 @@
multiclass VPatNConvertI2FP_RM_VL_W<SDNode vop, string instruction_name> {
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
- defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
+ defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti);
def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1),
(iwti.Mask V0), (XLenVT timm:$frm),
VLOpFrag)),
@@ -2265,7 +2265,7 @@
defvar octuple_lmul = vlmul.octuple;
defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW);
if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
- defvar emul_str = octuple_to_str<octuple_emul>.ret;
+ defvar emul_str = octuple_to_str(octuple_emul);
defvar ivti = !cast<VTypeInfo>("VI16" # emul_str);
defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str;
@@ -2303,7 +2303,7 @@
(!cast<Instruction>("PseudoVFMV_S_"#vti.ScalarSuffix#"_"#vti.LMul.MX)
vti.RegClass:$merge,
(vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>;
- defvar ivti = GetIntVTypeInfo<vti>.Vti;
+ defvar ivti = GetIntVTypeInfo(vti);
def : Pat<(vti.Vector
(riscv_vrgather_vv_vl vti.RegClass:$rs2,
@@ -2335,7 +2335,7 @@
defvar octuple_lmul = vlmul.octuple;
defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW);
if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
- defvar emul_str = octuple_to_str<octuple_emul>.ret;
+ defvar emul_str = octuple_to_str(octuple_emul);
defvar ivti = !cast<VTypeInfo>("VI16" # emul_str);
defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str;
Index: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -376,7 +376,7 @@
multiclass VPatConvertI2FPSDNode_V<SDPatternOperator vop,
string instruction_name> {
foreach fvti = AllFloatVectors in {
- defvar ivti = GetIntVTypeInfo<fvti>.Vti;
+ defvar ivti = GetIntVTypeInfo(fvti);
def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1))),
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
ivti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>;
@@ -386,7 +386,7 @@
multiclass VPatConvertFP2ISDNode_V<SDPatternOperator vop,
string instruction_name> {
foreach fvti = AllFloatVectors in {
- defvar ivti = GetIntVTypeInfo<fvti>.Vti;
+ defvar ivti = GetIntVTypeInfo(fvti);
def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1))),
(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX)
fvti.RegClass:$rs1, ivti.AVL, ivti.Log2SEW)>;
@@ -408,7 +408,7 @@
string instruction_name> {
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
- defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
+ defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti);
def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1))),
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
fvti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>;
@@ -419,7 +419,7 @@
string instruction_name> {
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
- defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
+ defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti);
def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1))),
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
iwti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>;
Index: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -47,7 +47,7 @@
// Utilities.
//===----------------------------------------------------------------------===//
-class PseudoToVInst<string PseudoInst> {
+function PseudoToVInst(string PseudoInst): string {
defvar AffixSubsts = [["Pseudo", ""],
["_E64", ""],
["_E32", ""],
@@ -80,8 +80,8 @@
["_M4", ""],
["_M8", ""]
];
- string VInst = !foldl(PseudoInst, AffixSubsts, Acc, AffixSubst,
- !subst(AffixSubst[0], AffixSubst[1], Acc));
+ return !foldl(PseudoInst, AffixSubsts, Acc, AffixSubst,
+ !subst(AffixSubst[0], AffixSubst[1], Acc));
}
// This class describes information associated to the LMUL.
@@ -126,11 +126,11 @@
// Use for zext/sext.vf8
defvar MxListVF8 = [V_M1, V_M2, V_M4, V_M8];
-class MxSet<int eew> {
- list<LMULInfo> m = !cond(!eq(eew, 8) : [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],
- !eq(eew, 16) : [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],
- !eq(eew, 32) : [V_MF2, V_M1, V_M2, V_M4, V_M8],
- !eq(eew, 64) : [V_M1, V_M2, V_M4, V_M8]);
+function MxSet(int eew): list<LMULInfo> {
+ return !cond(!eq(eew, 8) : [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],
+ !eq(eew, 16) : [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],
+ !eq(eew, 32) : [V_MF2, V_M1, V_M2, V_M4, V_M8],
+ !eq(eew, 64) : [V_M1, V_M2, V_M4, V_M8]);
}
class FPR_Info<RegisterClass regclass, string fx, list<LMULInfo> mxlist,
@@ -141,34 +141,34 @@
list<LMULInfo> MxListFW = mxlistfw;
}
-def SCALAR_F16 : FPR_Info<FPR16, "F16", MxSet<16>.m, [V_MF4, V_MF2, V_M1, V_M2, V_M4]>;
-def SCALAR_F32 : FPR_Info<FPR32, "F32", MxSet<32>.m, [V_MF2, V_M1, V_M2, V_M4]>;
-def SCALAR_F64 : FPR_Info<FPR64, "F64", MxSet<64>.m, []>;
+def SCALAR_F16 : FPR_Info<FPR16, "F16", MxSet(16), [V_MF4, V_MF2, V_M1, V_M2, V_M4]>;
+def SCALAR_F32 : FPR_Info<FPR32, "F32", MxSet(32), [V_MF2, V_M1, V_M2, V_M4]>;
+def SCALAR_F64 : FPR_Info<FPR64, "F64", MxSet(64), []>;
defvar FPList = [SCALAR_F16, SCALAR_F32, SCALAR_F64];
// Used for widening instructions. It excludes F64.
defvar FPListW = [SCALAR_F16, SCALAR_F32];
-class NFSet<LMULInfo m> {
- list<int> L = !cond(!eq(m.value, V_M8.value): [],
- !eq(m.value, V_M4.value): [2],
- !eq(m.value, V_M2.value): [2, 3, 4],
- true: [2, 3, 4, 5, 6, 7, 8]);
+function NFSet(LMULInfo m): list<int> {
+ return !cond(!eq(m.value, V_M8.value): [],
+ !eq(m.value, V_M4.value): [2],
+ !eq(m.value, V_M2.value): [2, 3, 4],
+ true: [2, 3, 4, 5, 6, 7, 8]);
}
-class log2<int num> {
- int val = !if(!eq(num, 1), 0, !add(1, log2<!srl(num, 1)>.val));
+function log2(int num): int {
+ return !if(!eq(num, 1), 0, !add(1, log2(!srl(num, 1))));
}
-class octuple_to_str<int octuple> {
- string ret = !cond(!eq(octuple, 1): "MF8",
- !eq(octuple, 2): "MF4",
- !eq(octuple, 4): "MF2",
- !eq(octuple, 8): "M1",
- !eq(octuple, 16): "M2",
- !eq(octuple, 32): "M4",
- !eq(octuple, 64): "M8");
+function octuple_to_str(int octuple): string {
+ return !cond(!eq(octuple, 1): "MF8",
+ !eq(octuple, 2): "MF4",
+ !eq(octuple, 4): "MF2",
+ !eq(octuple, 8): "M1",
+ !eq(octuple, 16): "M2",
+ !eq(octuple, 32): "M4",
+ !eq(octuple, 64): "M8");
}
def VLOpFrag : PatFrag<(ops), (XLenVT (VLOp (XLenVT AVL:$vl)))>;
@@ -181,11 +181,11 @@
// List of EEW.
defvar EEWList = [8, 16, 32, 64];
-class SegRegClass<LMULInfo m, int nf> {
- VReg RC = !cast<VReg>("VRN" # nf # !cond(!eq(m.value, V_MF8.value): V_M1.MX,
- !eq(m.value, V_MF4.value): V_M1.MX,
- !eq(m.value, V_MF2.value): V_M1.MX,
- true: m.MX));
+function SegRegClass(LMULInfo m, int nf): VReg {
+ return !cast<VReg>("VRN" # nf # !cond(!eq(m.value, V_MF8.value): V_M1.MX,
+ !eq(m.value, V_MF4.value): V_M1.MX,
+ !eq(m.value, V_MF2.value): V_M1.MX,
+ true: m.MX));
}
//===----------------------------------------------------------------------===//
@@ -198,7 +198,7 @@
ValueType Vector = Vec;
ValueType Mask = Mas;
int SEW = Sew;
- int Log2SEW = log2<Sew>.val;
+ int Log2SEW = log2(Sew);
VReg RegClass = Reg;
LMULInfo LMul = M;
ValueType Scalar = Scal;
@@ -293,14 +293,13 @@
}
}
-// This functor is used to obtain the int vector type that has the same SEW and
+// This function is used to obtain the int vector type that has the same SEW and
// multiplier as the input parameter type
-class GetIntVTypeInfo<VTypeInfo vti>
-{
+function GetIntVTypeInfo(VTypeInfo vti): VTypeInfo {
// Equivalent integer vector type. Eg.
// VI8M1 â VI8M1 (identity)
// VF64M4 â VI64M4
- VTypeInfo Vti = !cast<VTypeInfo>(!subst("VF", "VI", !cast<string>(vti)));
+ return !cast<VTypeInfo>(!subst("VF", "VI", !cast<string>(vti)));
}
class MTypeInfo<ValueType Mas, LMULInfo M, string Bx> {
@@ -441,7 +440,7 @@
def InvalidIndex : CONST8b<0x80>;
class RISCVVPseudo {
Pseudo Pseudo = !cast<Pseudo>(NAME); // Used as a key.
- Instruction BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+ Instruction BaseInstr = !cast<Instruction>(PseudoToVInst(NAME));
}
// The actual table.
@@ -637,33 +636,33 @@
// overlap the source mask register (v0), unless the destination vector register
// is being written with a mask value (e.g., comparisons) or the scalar result
// of a reduction.
-class GetVRegNoV0<VReg VRegClass> {
- VReg R = !cond(!eq(VRegClass, VR) : VRNoV0,
- !eq(VRegClass, VRM2) : VRM2NoV0,
- !eq(VRegClass, VRM4) : VRM4NoV0,
- !eq(VRegClass, VRM8) : VRM8NoV0,
- !eq(VRegClass, VRN2M1) : VRN2M1NoV0,
- !eq(VRegClass, VRN2M2) : VRN2M2NoV0,
- !eq(VRegClass, VRN2M4) : VRN2M4NoV0,
- !eq(VRegClass, VRN3M1) : VRN3M1NoV0,
- !eq(VRegClass, VRN3M2) : VRN3M2NoV0,
- !eq(VRegClass, VRN4M1) : VRN4M1NoV0,
- !eq(VRegClass, VRN4M2) : VRN4M2NoV0,
- !eq(VRegClass, VRN5M1) : VRN5M1NoV0,
- !eq(VRegClass, VRN6M1) : VRN6M1NoV0,
- !eq(VRegClass, VRN7M1) : VRN7M1NoV0,
- !eq(VRegClass, VRN8M1) : VRN8M1NoV0,
- true : VRegClass);
+function GetVRegNoV0(VReg VRegClass): VReg {
+ return !cond(!eq(VRegClass, VR) : VRNoV0,
+ !eq(VRegClass, VRM2) : VRM2NoV0,
+ !eq(VRegClass, VRM4) : VRM4NoV0,
+ !eq(VRegClass, VRM8) : VRM8NoV0,
+ !eq(VRegClass, VRN2M1) : VRN2M1NoV0,
+ !eq(VRegClass, VRN2M2) : VRN2M2NoV0,
+ !eq(VRegClass, VRN2M4) : VRN2M4NoV0,
+ !eq(VRegClass, VRN3M1) : VRN3M1NoV0,
+ !eq(VRegClass, VRN3M2) : VRN3M2NoV0,
+ !eq(VRegClass, VRN4M1) : VRN4M1NoV0,
+ !eq(VRegClass, VRN4M2) : VRN4M2NoV0,
+ !eq(VRegClass, VRN5M1) : VRN5M1NoV0,
+ !eq(VRegClass, VRN6M1) : VRN6M1NoV0,
+ !eq(VRegClass, VRN7M1) : VRN7M1NoV0,
+ !eq(VRegClass, VRN8M1) : VRN8M1NoV0,
+ true : VRegClass);
}
// Join strings in list using separator and ignoring empty elements
-class Join<list<string> strings, string separator> {
- string ret = !foldl(!head(strings), !tail(strings), a, b,
- !cond(
- !and(!empty(a), !empty(b)) : "",
- !empty(a) : b,
- !empty(b) : a,
- 1 : a#separator#b));
+function Join(list<string> strings, string separator): string {
+ return !foldl(!head(strings), !tail(strings), a, b,
+ !cond(
+ !and(!empty(a), !empty(b)) : "",
+ !empty(a) : b,
+ !empty(b) : a,
+ 1 : a#separator#b));
}
class VPseudo<Instruction instr, LMULInfo m, dag outs, dag ins> :
@@ -676,7 +675,7 @@
Pseudo<(outs RetClass:$rd),
(ins GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVLE</*Masked*/0, /*TU*/0, /*Strided*/0, /*FF*/0, log2<EEW>.val, VLMul> {
+ RISCVVLE</*Masked*/0, /*TU*/0, /*Strided*/0, /*FF*/0, log2(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -689,7 +688,7 @@
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVLE</*Masked*/0, /*TU*/1, /*Strided*/0, /*FF*/0, log2<EEW>.val, VLMul> {
+ RISCVVLE</*Masked*/0, /*TU*/1, /*Strided*/0, /*FF*/0, log2(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -701,12 +700,12 @@
}
class VPseudoUSLoadMask<VReg RetClass, int EEW> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$merge,
+ Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+ (ins GetVRegNoV0'(RetClass):$merge,
GPRMem:$rs1,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>,
RISCVVPseudo,
- RISCVVLE</*Masked*/1, /*TU*/1, /*Strided*/0, /*FF*/0, log2<EEW>.val, VLMul> {
+ RISCVVLE</*Masked*/1, /*TU*/1, /*Strided*/0, /*FF*/0, log2(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -722,7 +721,7 @@
Pseudo<(outs RetClass:$rd, GPR:$vl),
(ins GPRMem:$rs1, AVL:$avl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVLE</*Masked*/0, /*TU*/0, /*Strided*/0, /*FF*/1, log2<EEW>.val, VLMul> {
+ RISCVVLE</*Masked*/0, /*TU*/0, /*Strided*/0, /*FF*/1, log2(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -735,7 +734,7 @@
Pseudo<(outs RetClass:$rd, GPR:$vl),
(ins RetClass:$dest, GPRMem:$rs1, AVL:$avl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVLE</*Masked*/0, /*TU*/1, /*Strided*/0, /*FF*/1, log2<EEW>.val, VLMul> {
+ RISCVVLE</*Masked*/0, /*TU*/1, /*Strided*/0, /*FF*/1, log2(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -747,12 +746,12 @@
}
class VPseudoUSLoadFFMask<VReg RetClass, int EEW> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
- (ins GetVRegNoV0<RetClass>.R:$merge,
+ Pseudo<(outs GetVRegNoV0'(RetClass):$rd, GPR:$vl),
+ (ins GetVRegNoV0'(RetClass):$merge,
GPRMem:$rs1,
VMaskOp:$vm, AVL:$avl, ixlenimm:$sew, ixlenimm:$policy),[]>,
RISCVVPseudo,
- RISCVVLE</*Masked*/1, /*TU*/1, /*Strided*/0, /*FF*/1, log2<EEW>.val, VLMul> {
+ RISCVVLE</*Masked*/1, /*TU*/1, /*Strided*/0, /*FF*/1, log2(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -768,7 +767,7 @@
Pseudo<(outs RetClass:$rd),
(ins GPRMem:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVLE</*Masked*/0, /*TU*/0, /*Strided*/1, /*FF*/0, log2<EEW>.val, VLMul> {
+ RISCVVLE</*Masked*/0, /*TU*/0, /*Strided*/1, /*FF*/0, log2(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -781,7 +780,7 @@
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPRMem:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVLE</*Masked*/0, /*TU*/1, /*Strided*/1, /*FF*/0, log2<EEW>.val, VLMul> {
+ RISCVVLE</*Masked*/0, /*TU*/1, /*Strided*/1, /*FF*/0, log2(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -793,12 +792,12 @@
}
class VPseudoSLoadMask<VReg RetClass, int EEW>:
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$merge,
+ Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+ (ins GetVRegNoV0'(RetClass):$merge,
GPRMem:$rs1, GPR:$rs2,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>,
RISCVVPseudo,
- RISCVVLE</*Masked*/1, /*TU*/1, /*Strided*/1, /*FF*/0, log2<EEW>.val, VLMul> {
+ RISCVVLE</*Masked*/1, /*TU*/1, /*Strided*/1, /*FF*/0, log2(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -816,7 +815,7 @@
(ins GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVLX</*Masked*/0, /*TU*/0, Ordered, log2<EEW>.val, VLMul, LMUL> {
+ RISCVVLX</*Masked*/0, /*TU*/0, Ordered, log2(EEW), VLMul, LMUL> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -832,7 +831,7 @@
(ins RetClass:$dest, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVLX</*Masked*/0, /*TU*/1, Ordered, log2<EEW>.val, VLMul, LMUL> {
+ RISCVVLX</*Masked*/0, /*TU*/1, Ordered, log2(EEW), VLMul, LMUL> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -845,12 +844,12 @@
class VPseudoILoadMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
bit Ordered, bit EarlyClobber>:
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$merge,
+ Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+ (ins GetVRegNoV0'(RetClass):$merge,
GPRMem:$rs1, IdxClass:$rs2,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>,
RISCVVPseudo,
- RISCVVLX</*Masked*/1, /*TU*/1, Ordered, log2<EEW>.val, VLMul, LMUL> {
+ RISCVVLX</*Masked*/1, /*TU*/1, Ordered, log2(EEW), VLMul, LMUL> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -866,7 +865,7 @@
Pseudo<(outs),
(ins StClass:$rd, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVSE</*Masked*/0, /*Strided*/0, log2<EEW>.val, VLMul> {
+ RISCVVSE</*Masked*/0, /*Strided*/0, log2(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
let hasSideEffects = 0;
@@ -879,7 +878,7 @@
Pseudo<(outs),
(ins StClass:$rd, GPRMem:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVSE</*Masked*/1, /*Strided*/0, log2<EEW>.val, VLMul> {
+ RISCVVSE</*Masked*/1, /*Strided*/0, log2(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
let hasSideEffects = 0;
@@ -891,7 +890,7 @@
Pseudo<(outs),
(ins StClass:$rd, GPRMem:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVSE</*Masked*/0, /*Strided*/1, log2<EEW>.val, VLMul> {
+ RISCVVSE</*Masked*/0, /*Strided*/1, log2(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
let hasSideEffects = 0;
@@ -904,7 +903,7 @@
Pseudo<(outs),
(ins StClass:$rd, GPRMem:$rs1, GPR:$rs2, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVSE</*Masked*/1, /*Strided*/1, log2<EEW>.val, VLMul> {
+ RISCVVSE</*Masked*/1, /*Strided*/1, log2(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
let hasSideEffects = 0;
@@ -966,8 +965,8 @@
}
class VPseudoNullaryMask<VReg RegClass>:
- Pseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
- (ins GetVRegNoV0<RegClass>.R:$merge, VMaskOp:$vm, AVL:$vl,
+ Pseudo<(outs GetVRegNoV0'(RegClass):$rd),
+ (ins GetVRegNoV0'(RegClass):$merge, VMaskOp:$vm, AVL:$vl,
ixlenimm:$sew, ixlenimm:$policy), []>, RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1017,7 +1016,7 @@
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
- let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+ let Constraints = Join([Constraint, "$rd = $merge"], ",");
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
@@ -1025,14 +1024,14 @@
}
class VPseudoUnaryMask<VReg RetClass, VReg OpClass, string Constraint = ""> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,
+ Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+ (ins GetVRegNoV0'(RetClass):$merge, OpClass:$rs2,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
- let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+ let Constraints = Join([Constraint, "$rd = $merge"], ",");
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
@@ -1040,14 +1039,14 @@
}
class VPseudoUnaryMaskTA<VReg RetClass, VReg OpClass, string Constraint = ""> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,
+ Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+ (ins GetVRegNoV0'(RetClass):$merge, OpClass:$rs2,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
- let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+ let Constraints = Join([Constraint, "$rd = $merge"], ",");
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
@@ -1056,13 +1055,13 @@
}
class VPseudoUnaryMaskTA_NoExcept<VReg RetClass, VReg OpClass, string Constraint = ""> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2, VMaskOp:$vm,
+ Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+ (ins GetVRegNoV0'(RetClass):$merge, OpClass:$rs2, VMaskOp:$vm,
AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
- let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+ let Constraints = Join([Constraint, "$rd = $merge"], ",");
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
@@ -1072,13 +1071,13 @@
}
class VPseudoUnaryMaskTA_FRM<VReg RetClass, VReg OpClass, string Constraint = ""> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,
+ Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+ (ins GetVRegNoV0'(RetClass):$merge, OpClass:$rs2,
VMaskOp:$vm, ixlenimm:$frm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
- let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+ let Constraints = Join([Constraint, "$rd = $merge"], ",");
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
@@ -1144,7 +1143,7 @@
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
- let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+ let Constraints = Join([Constraint, "$rd = $merge"], ",");
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
@@ -1164,7 +1163,7 @@
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
- let Constraints = Join<[Constraint, "$rd = $rs2"], ",">.ret;
+ let Constraints = Join([Constraint, "$rd = $rs2"], ",");
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
@@ -1177,7 +1176,7 @@
Pseudo<(outs),
(ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVSX</*Masked*/0, Ordered, log2<EEW>.val, VLMul, LMUL> {
+ RISCVVSX</*Masked*/0, Ordered, log2(EEW), VLMul, LMUL> {
let mayLoad = 0;
let mayStore = 1;
let hasSideEffects = 0;
@@ -1191,7 +1190,7 @@
Pseudo<(outs),
(ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVSX</*Masked*/1, Ordered, log2<EEW>.val, VLMul, LMUL> {
+ RISCVVSX</*Masked*/1, Ordered, log2(EEW), VLMul, LMUL> {
let mayLoad = 0;
let mayStore = 1;
let hasSideEffects = 0;
@@ -1203,15 +1202,15 @@
RegisterClass Op1Class,
DAGOperand Op2Class,
string Constraint> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$merge,
+ Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+ (ins GetVRegNoV0'(RetClass):$merge,
Op1Class:$rs2, Op2Class:$rs1,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
- let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+ let Constraints = Join([Constraint, "$rd = $merge"], ",");
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
@@ -1221,15 +1220,15 @@
RegisterClass Op1Class,
DAGOperand Op2Class,
string Constraint> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$merge,
+ Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+ (ins GetVRegNoV0'(RetClass):$merge,
Op1Class:$rs2, Op2Class:$rs1,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
- let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+ let Constraints = Join([Constraint, "$rd = $merge"], ",");
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
@@ -1241,15 +1240,15 @@
RegisterClass Op1Class,
DAGOperand Op2Class,
string Constraint> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$merge,
+ Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+ (ins GetVRegNoV0'(RetClass):$merge,
Op1Class:$rs2, Op2Class:$rs1,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
- let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+ let Constraints = Join([Constraint, "$rd = $merge"], ",");
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
@@ -1269,7 +1268,7 @@
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
- let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+ let Constraints = Join([Constraint, "$rd = $merge"], ",");
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
@@ -1282,15 +1281,15 @@
class VPseudoTiedBinaryMask<VReg RetClass,
DAGOperand Op2Class,
string Constraint> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$merge,
+ Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+ (ins GetVRegNoV0'(RetClass):$merge,
Op2Class:$rs1,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
- let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+ let Constraints = Join([Constraint, "$rd = $merge"], ",");
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 0; // Merge is also rs2.
@@ -1335,7 +1334,7 @@
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
- let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+ let Constraints = Join([Constraint, "$rd = $merge"], ",");
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
@@ -1355,7 +1354,7 @@
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
- let Constraints = Join<[Constraint, "$rd = $rs3"], ",">.ret;
+ let Constraints = Join([Constraint, "$rd = $rs3"], ",");
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
@@ -1374,7 +1373,7 @@
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
- let Constraints = Join<[Constraint, "$rd = $rs3"], ",">.ret;
+ let Constraints = Join([Constraint, "$rd = $rs3"], ",");
let HasVecPolicyOp = 1;
let HasVLOp = 1;
let HasSEWOp = 1;
@@ -1386,7 +1385,7 @@
Pseudo<(outs RetClass:$rd),
(ins GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVLSEG<NF, /*Masked*/0, /*TU*/0, /*Strided*/0, /*FF*/0, log2<EEW>.val, VLMul> {
+ RISCVVLSEG<NF, /*Masked*/0, /*TU*/0, /*Strided*/0, /*FF*/0, log2(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1399,7 +1398,7 @@
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVLSEG<NF, /*Masked*/0, /*TU*/1, /*Strided*/0, /*FF*/0, log2<EEW>.val, VLMul> {
+ RISCVVLSEG<NF, /*Masked*/0, /*TU*/1, /*Strided*/0, /*FF*/0, log2(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1411,11 +1410,11 @@
}
class VPseudoUSSegLoadMask<VReg RetClass, int EEW, bits<4> NF>:
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$merge, GPRMem:$rs1,
+ Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+ (ins GetVRegNoV0'(RetClass):$merge, GPRMem:$rs1,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>,
RISCVVPseudo,
- RISCVVLSEG<NF, /*Masked*/1, /*TU*/1, /*Strided*/0, /*FF*/0, log2<EEW>.val, VLMul> {
+ RISCVVLSEG<NF, /*Masked*/1, /*TU*/1, /*Strided*/0, /*FF*/0, log2(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1431,7 +1430,7 @@
Pseudo<(outs RetClass:$rd, GPR:$vl),
(ins GPRMem:$rs1, AVL:$avl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVLSEG<NF, /*Masked*/0, /*TU*/0, /*Strided*/0, /*FF*/1, log2<EEW>.val, VLMul> {
+ RISCVVLSEG<NF, /*Masked*/0, /*TU*/0, /*Strided*/0, /*FF*/1, log2(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1444,7 +1443,7 @@
Pseudo<(outs RetClass:$rd, GPR:$vl),
(ins RetClass:$dest, GPRMem:$rs1, AVL:$avl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVLSEG<NF, /*Masked*/0, /*TU*/1, /*Strided*/0, /*FF*/1, log2<EEW>.val, VLMul> {
+ RISCVVLSEG<NF, /*Masked*/0, /*TU*/1, /*Strided*/0, /*FF*/1, log2(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1456,11 +1455,11 @@
}
class VPseudoUSSegLoadFFMask<VReg RetClass, int EEW, bits<4> NF>:
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
- (ins GetVRegNoV0<RetClass>.R:$merge, GPRMem:$rs1,
+ Pseudo<(outs GetVRegNoV0'(RetClass):$rd, GPR:$vl),
+ (ins GetVRegNoV0'(RetClass):$merge, GPRMem:$rs1,
VMaskOp:$vm, AVL:$avl, ixlenimm:$sew, ixlenimm:$policy),[]>,
RISCVVPseudo,
- RISCVVLSEG<NF, /*Masked*/1, /*TU*/1, /*Strided*/0, /*FF*/1, log2<EEW>.val, VLMul> {
+ RISCVVLSEG<NF, /*Masked*/1, /*TU*/1, /*Strided*/0, /*FF*/1, log2(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1476,7 +1475,7 @@
Pseudo<(outs RetClass:$rd),
(ins GPRMem:$rs1, GPR:$offset, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVLSEG<NF, /*Masked*/0, /*TU*/0, /*Strided*/1, /*FF*/0, log2<EEW>.val, VLMul> {
+ RISCVVLSEG<NF, /*Masked*/0, /*TU*/0, /*Strided*/1, /*FF*/0, log2(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1489,7 +1488,7 @@
Pseudo<(outs RetClass:$rd),
(ins RetClass:$merge, GPRMem:$rs1, GPR:$offset, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVLSEG<NF, /*Masked*/0, /*TU*/1, /*Strided*/1, /*FF*/0, log2<EEW>.val, VLMul> {
+ RISCVVLSEG<NF, /*Masked*/0, /*TU*/1, /*Strided*/1, /*FF*/0, log2(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1501,12 +1500,12 @@
}
class VPseudoSSegLoadMask<VReg RetClass, int EEW, bits<4> NF>:
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$merge, GPRMem:$rs1,
+ Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+ (ins GetVRegNoV0'(RetClass):$merge, GPRMem:$rs1,
GPR:$offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew,
ixlenimm:$policy),[]>,
RISCVVPseudo,
- RISCVVLSEG<NF, /*Masked*/1, /*TU*/1, /*Strided*/1, /*FF*/0, log2<EEW>.val, VLMul> {
+ RISCVVLSEG<NF, /*Masked*/1, /*TU*/1, /*Strided*/1, /*FF*/0, log2(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1523,7 +1522,7 @@
Pseudo<(outs RetClass:$rd),
(ins GPRMem:$rs1, IdxClass:$offset, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVLXSEG<NF, /*Masked*/0, /*TU*/0, Ordered, log2<EEW>.val, VLMul, LMUL> {
+ RISCVVLXSEG<NF, /*Masked*/0, /*TU*/0, Ordered, log2(EEW), VLMul, LMUL> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1540,7 +1539,7 @@
Pseudo<(outs RetClass:$rd),
(ins RetClass:$merge, GPRMem:$rs1, IdxClass:$offset, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVLXSEG<NF, /*Masked*/0, /*TU*/1, Ordered, log2<EEW>.val, VLMul, LMUL> {
+ RISCVVLXSEG<NF, /*Masked*/0, /*TU*/1, Ordered, log2(EEW), VLMul, LMUL> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1555,12 +1554,12 @@
class VPseudoISegLoadMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
bits<4> NF, bit Ordered>:
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$merge, GPRMem:$rs1,
+ Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+ (ins GetVRegNoV0'(RetClass):$merge, GPRMem:$rs1,
IdxClass:$offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew,
ixlenimm:$policy),[]>,
RISCVVPseudo,
- RISCVVLXSEG<NF, /*Masked*/1, /*TU*/1, Ordered, log2<EEW>.val, VLMul, LMUL> {
+ RISCVVLXSEG<NF, /*Masked*/1, /*TU*/1, Ordered, log2(EEW), VLMul, LMUL> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1578,7 +1577,7 @@
Pseudo<(outs),
(ins ValClass:$rd, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVSSEG<NF, /*Masked*/0, /*Strided*/0, log2<EEW>.val, VLMul> {
+ RISCVVSSEG<NF, /*Masked*/0, /*Strided*/0, log2(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
let hasSideEffects = 0;
@@ -1592,7 +1591,7 @@
(ins ValClass:$rd, GPRMem:$rs1,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVSSEG<NF, /*Masked*/1, /*Strided*/0, log2<EEW>.val, VLMul> {
+ RISCVVSSEG<NF, /*Masked*/1, /*Strided*/0, log2(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
let hasSideEffects = 0;
@@ -1604,7 +1603,7 @@
Pseudo<(outs),
(ins ValClass:$rd, GPRMem:$rs1, GPR: $offset, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVSSEG<NF, /*Masked*/0, /*Strided*/1, log2<EEW>.val, VLMul> {
+ RISCVVSSEG<NF, /*Masked*/0, /*Strided*/1, log2(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
let hasSideEffects = 0;
@@ -1618,7 +1617,7 @@
(ins ValClass:$rd, GPRMem:$rs1, GPR: $offset,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVSSEG<NF, /*Masked*/1, /*Strided*/1, log2<EEW>.val, VLMul> {
+ RISCVVSSEG<NF, /*Masked*/1, /*Strided*/1, log2(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
let hasSideEffects = 0;
@@ -1632,7 +1631,7 @@
(ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index,
AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVSXSEG<NF, /*Masked*/0, Ordered, log2<EEW>.val, VLMul, LMUL> {
+ RISCVVSXSEG<NF, /*Masked*/0, Ordered, log2(EEW), VLMul, LMUL> {
let mayLoad = 0;
let mayStore = 1;
let hasSideEffects = 0;
@@ -1647,7 +1646,7 @@
(ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
- RISCVVSXSEG<NF, /*Masked*/1, Ordered, log2<EEW>.val, VLMul, LMUL> {
+ RISCVVSXSEG<NF, /*Masked*/1, Ordered, log2(EEW), VLMul, LMUL> {
let mayLoad = 0;
let mayStore = 1;
let hasSideEffects = 0;
@@ -1657,7 +1656,7 @@
multiclass VPseudoUSLoad {
foreach eew = EEWList in {
- foreach lmul = MxSet<eew>.m in {
+ foreach lmul = MxSet(eew) in {
defvar LInfo = lmul.MX;
defvar vreg = lmul.vrclass;
let VLMul = lmul.value in {
@@ -1678,7 +1677,7 @@
multiclass VPseudoFFLoad {
foreach eew = EEWList in {
- foreach lmul = MxSet<eew>.m in {
+ foreach lmul = MxSet(eew) in {
defvar LInfo = lmul.MX;
defvar vreg = lmul.vrclass;
let VLMul = lmul.value in {
@@ -1710,7 +1709,7 @@
multiclass VPseudoSLoad {
foreach eew = EEWList in {
- foreach lmul = MxSet<eew>.m in {
+ foreach lmul = MxSet(eew) in {
defvar LInfo = lmul.MX;
defvar vreg = lmul.vrclass;
let VLMul = lmul.value in {
@@ -1730,13 +1729,13 @@
multiclass VPseudoILoad<bit Ordered> {
foreach eew = EEWList in {
foreach sew = EEWList in {
- foreach lmul = MxSet<sew>.m in {
+ foreach lmul = MxSet(sew) in {
defvar octuple_lmul = lmul.octuple;
// Calculate emul = eew * lmul / sew
- defvar octuple_emul = !srl(!mul(eew, octuple_lmul), log2<sew>.val);
+ defvar octuple_emul = !srl(!mul(eew, octuple_lmul), log2(sew));
if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
defvar DataLInfo = lmul.MX;
- defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
+ defvar IdxLInfo = octuple_to_str(octuple_emul);
defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
defvar Vreg = lmul.vrclass;
defvar IdxVreg = idx_lmul.vrclass;
@@ -1762,7 +1761,7 @@
multiclass VPseudoUSStore {
foreach eew = EEWList in {
- foreach lmul = MxSet<eew>.m in {
+ foreach lmul = MxSet(eew) in {
defvar LInfo = lmul.MX;
defvar vreg = lmul.vrclass;
let VLMul = lmul.value in {
@@ -1788,7 +1787,7 @@
multiclass VPseudoSStore {
foreach eew = EEWList in {
- foreach lmul = MxSet<eew>.m in {
+ foreach lmul = MxSet(eew) in {
defvar LInfo = lmul.MX;
defvar vreg = lmul.vrclass;
let VLMul = lmul.value in {
@@ -1804,13 +1803,13 @@
multiclass VPseudoIStore<bit Ordered> {
foreach eew = EEWList in {
foreach sew = EEWList in {
- foreach lmul = MxSet<sew>.m in {
+ foreach lmul = MxSet(sew) in {
defvar octuple_lmul = lmul.octuple;
// Calculate emul = eew * lmul / sew
- defvar octuple_emul = !srl(!mul(eew, octuple_lmul), log2<sew>.val);
+ defvar octuple_emul = !srl(!mul(eew, octuple_lmul), log2(sew));
if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
defvar DataLInfo = lmul.MX;
- defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
+ defvar IdxLInfo = octuple_to_str(octuple_emul);
defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
defvar Vreg = lmul.vrclass;
defvar IdxVreg = idx_lmul.vrclass;
@@ -1927,7 +1926,7 @@
multiclass VPseudoVCPR_V {
foreach m = MxList in {
defvar mx = m.MX;
- defvar sews = SchedSEWSet<mx>.val;
+ defvar sews = SchedSEWSet(mx);
let VLMul = m.value in
foreach e = sews in {
defvar suffix = "_" # m.MX # "_E" # e;
@@ -2060,11 +2059,11 @@
foreach sew = EEWList in {
defvar octuple_lmul = m.octuple;
// emul = lmul * eew / sew
- defvar octuple_emul = !srl(!mul(octuple_lmul, eew), log2<sew>.val);
+ defvar octuple_emul = !srl(!mul(octuple_lmul, eew), log2(sew));
if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
- defvar emulMX = octuple_to_str<octuple_emul>.ret;
+ defvar emulMX = octuple_to_str(octuple_emul);
defvar emul = !cast<LMULInfo>("V_" # emulMX);
- defvar sews = SchedSEWSet<mx>.val;
+ defvar sews = SchedSEWSet(mx);
foreach e = sews in {
defvar WriteVRGatherVV_MX_E = !cast<SchedWrite>("WriteVRGatherVV_" # mx # "_E" # e);
defvar ReadVRGatherVV_data_MX_E = !cast<SchedRead>("ReadVRGatherVV_data_" # mx # "_E" # e);
@@ -2207,7 +2206,7 @@
def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX :
VPseudoBinaryCarryIn<!if(CarryOut, VR,
!if(!and(CarryIn, !not(CarryOut)),
- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
+ GetVRegNoV0(m.vrclass), m.vrclass)),
m.vrclass, m.vrclass, m, CarryIn, Constraint>;
}
@@ -2216,7 +2215,7 @@
def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX # "_TU" :
VPseudoTiedBinaryCarryIn<!if(CarryOut, VR,
!if(!and(CarryIn, !not(CarryOut)),
- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
+ GetVRegNoV0(m.vrclass), m.vrclass)),
m.vrclass, m.vrclass, m, CarryIn, Constraint>;
}
@@ -2225,7 +2224,7 @@
def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX :
VPseudoBinaryCarryIn<!if(CarryOut, VR,
!if(!and(CarryIn, !not(CarryOut)),
- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
+ GetVRegNoV0(m.vrclass), m.vrclass)),
m.vrclass, GPR, m, CarryIn, Constraint>;
}
@@ -2234,7 +2233,7 @@
def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX # "_TU":
VPseudoTiedBinaryCarryIn<!if(CarryOut, VR,
!if(!and(CarryIn, !not(CarryOut)),
- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
+ GetVRegNoV0(m.vrclass), m.vrclass)),
m.vrclass, GPR, m, CarryIn, Constraint>;
}
@@ -2247,12 +2246,12 @@
defvar ReadVFMergeF_MX = !cast<SchedRead>("ReadVFMergeF_" # mx);
def "_V" # f.FX # "M_" # mx :
- VPseudoBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
+ VPseudoBinaryCarryIn<GetVRegNoV0(m.vrclass),
m.vrclass, f.fprclass, m, /*CarryIn=*/1, "">,
Sched<[WriteVFMergeV_MX, ReadVFMergeV_MX, ReadVFMergeF_MX, ReadVMask]>;
// Tied version to allow codegen control over the tail elements
def "_V" # f.FX # "M_" # mx # "_TU":
- VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
+ VPseudoTiedBinaryCarryIn<GetVRegNoV0(m.vrclass),
m.vrclass, f.fprclass, m, /*CarryIn=*/1, "">,
Sched<[WriteVFMergeV_MX, ReadVFMergeV_MX, ReadVFMergeF_MX, ReadVMask]>;
}
@@ -2264,7 +2263,7 @@
def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX :
VPseudoBinaryCarryIn<!if(CarryOut, VR,
!if(!and(CarryIn, !not(CarryOut)),
- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
+ GetVRegNoV0(m.vrclass), m.vrclass)),
m.vrclass, simm5, m, CarryIn, Constraint>;
}
@@ -2273,7 +2272,7 @@
def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX # "_TU":
VPseudoTiedBinaryCarryIn<!if(CarryOut, VR,
!if(!and(CarryIn, !not(CarryOut)),
- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
+ GetVRegNoV0(m.vrclass), m.vrclass)),
m.vrclass, simm5, m, CarryIn, Constraint>;
}
@@ -2345,7 +2344,7 @@
multiclass VPseudoVSQR_V {
foreach m = MxListF in {
defvar mx = m.MX;
- defvar sews = SchedSEWSetF<m.MX>.val;
+ defvar sews = SchedSEWSetF(mx);
let VLMul = m.value in
foreach e = sews in {
@@ -2496,7 +2495,7 @@
defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
Sched<[WriteVRGatherVI_MX, ReadVRGatherVI_data_MX, ReadVMask]>;
- defvar sews = SchedSEWSet<mx>.val;
+ defvar sews = SchedSEWSet(mx);
foreach e = sews in {
defvar WriteVRGatherVV_MX_E = !cast<SchedWrite>("WriteVRGatherVV_" # mx # "_E" # e);
defvar ReadVRGatherVV_data_MX_E = !cast<SchedRead>("ReadVRGatherVV_data_" # mx # "_E" # e);
@@ -2659,7 +2658,7 @@
multiclass VPseudoVDIV_VV_VX {
foreach m = MxList in {
defvar mx = m.MX;
- defvar sews = SchedSEWSet<mx>.val;
+ defvar sews = SchedSEWSet(mx);
foreach e = sews in {
defvar WriteVIDivV_MX_E = !cast<SchedWrite>("WriteVIDivV_" # mx # "_E" # e);
defvar WriteVIDivX_MX_E = !cast<SchedWrite>("WriteVIDivX_" # mx # "_E" # e);
@@ -2700,7 +2699,7 @@
multiclass VPseudoVFDIV_VV_VF {
foreach m = MxListF in {
defvar mx = m.MX;
- defvar sews = SchedSEWSetF<mx>.val;
+ defvar sews = SchedSEWSetF(mx);
foreach e = sews in {
defvar WriteVFDivV_MX_E = !cast<SchedWrite>("WriteVFDivV_" # mx # "_E" # e);
defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
@@ -2713,7 +2712,7 @@
foreach f = FPList in {
foreach m = f.MxList in {
defvar mx = m.MX;
- defvar sews = SchedSEWSetF<mx>.val;
+ defvar sews = SchedSEWSetF(mx);
foreach e = sews in {
defvar WriteVFDivF_MX_E = !cast<SchedWrite>("WriteVFDivF_" # mx # "_E" # e);
defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
@@ -2730,7 +2729,7 @@
foreach f = FPList in {
foreach m = f.MxList in {
defvar mx = m.MX;
- defvar sews = SchedSEWSetF<mx>.val;
+ defvar sews = SchedSEWSetF(mx);
foreach e = sews in {
defvar WriteVFDivF_MX_E = !cast<SchedWrite>("WriteVFDivF_" # mx # "_E" # e);
defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
@@ -3171,7 +3170,7 @@
bit Commutable = 0> {
let VLMul = MInfo.value in {
defvar mx = MInfo.MX;
- defvar sews = SchedSEWSet<mx>.val;
+ defvar sews = SchedSEWSet(mx);
foreach e = sews in {
let isCommutable = Commutable in
def "_" # mx # "_E" # e : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>;
@@ -3696,11 +3695,11 @@
multiclass VPseudoUSSegLoad {
foreach eew = EEWList in {
- foreach lmul = MxSet<eew>.m in {
+ foreach lmul = MxSet(eew) in {
defvar LInfo = lmul.MX;
let VLMul = lmul.value in {
- foreach nf = NFSet<lmul>.L in {
- defvar vreg = SegRegClass<lmul, nf>.RC;
+ foreach nf = NFSet(lmul) in {
+ defvar vreg = SegRegClass(lmul, nf);
def nf # "E" # eew # "_V_" # LInfo :
VPseudoUSSegLoadNoMask<vreg, eew, nf>, VLSEGSched<nf, eew, LInfo>;
def nf # "E" # eew # "_V_" # LInfo # "_TU" :
@@ -3715,11 +3714,11 @@
multiclass VPseudoUSSegLoadFF {
foreach eew = EEWList in {
- foreach lmul = MxSet<eew>.m in {
+ foreach lmul = MxSet(eew) in {
defvar LInfo = lmul.MX;
let VLMul = lmul.value in {
- foreach nf = NFSet<lmul>.L in {
- defvar vreg = SegRegClass<lmul, nf>.RC;
+ foreach nf = NFSet(lmul) in {
+ defvar vreg = SegRegClass(lmul, nf);
def nf # "E" # eew # "FF_V_" # LInfo :
VPseudoUSSegLoadFFNoMask<vreg, eew, nf>, VLSEGFFSched<nf, eew, LInfo>;
def nf # "E" # eew # "FF_V_" # LInfo # "_TU" :
@@ -3734,11 +3733,11 @@
multiclass VPseudoSSegLoad {
foreach eew = EEWList in {
- foreach lmul = MxSet<eew>.m in {
+ foreach lmul = MxSet(eew) in {
defvar LInfo = lmul.MX;
let VLMul = lmul.value in {
- foreach nf = NFSet<lmul>.L in {
- defvar vreg = SegRegClass<lmul, nf>.RC;
+ foreach nf = NFSet(lmul) in {
+ defvar vreg = SegRegClass(lmul, nf);
def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegLoadNoMask<vreg, eew, nf>,
VLSSEGSched<nf, eew, LInfo>;
def nf # "E" # eew # "_V_" # LInfo # "_TU" : VPseudoSSegLoadNoMaskTU<vreg, eew, nf>,
@@ -3754,20 +3753,20 @@
multiclass VPseudoISegLoad<bit Ordered> {
foreach idx_eew = EEWList in {
foreach sew = EEWList in {
- foreach val_lmul = MxSet<sew>.m in {
+ foreach val_lmul = MxSet(sew) in {
defvar octuple_lmul = val_lmul.octuple;
// Calculate emul = eew * lmul / sew
- defvar octuple_emul = !srl(!mul(idx_eew, octuple_lmul), log2<sew>.val);
+ defvar octuple_emul = !srl(!mul(idx_eew, octuple_lmul), log2(sew));
if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
defvar ValLInfo = val_lmul.MX;
- defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
+ defvar IdxLInfo = octuple_to_str(octuple_emul);
defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
defvar Vreg = val_lmul.vrclass;
defvar IdxVreg = idx_lmul.vrclass;
defvar Order = !if(Ordered, "O", "U");
let VLMul = val_lmul.value in {
- foreach nf = NFSet<val_lmul>.L in {
- defvar ValVreg = SegRegClass<val_lmul, nf>.RC;
+ foreach nf = NFSet(val_lmul) in {
+ defvar ValVreg = SegRegClass(val_lmul, nf);
def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo :
VPseudoISegLoadNoMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value,
nf, Ordered>,
@@ -3790,11 +3789,11 @@
multiclass VPseudoUSSegStore {
foreach eew = EEWList in {
- foreach lmul = MxSet<eew>.m in {
+ foreach lmul = MxSet(eew) in {
defvar LInfo = lmul.MX;
let VLMul = lmul.value in {
- foreach nf = NFSet<lmul>.L in {
- defvar vreg = SegRegClass<lmul, nf>.RC;
+ foreach nf = NFSet(lmul) in {
+ defvar vreg = SegRegClass(lmul, nf);
def nf # "E" # eew # "_V_" # LInfo : VPseudoUSSegStoreNoMask<vreg, eew, nf>,
VSSEGSched<nf, eew, LInfo>;
def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSSegStoreMask<vreg, eew, nf>,
@@ -3807,11 +3806,11 @@
multiclass VPseudoSSegStore {
foreach eew = EEWList in {
- foreach lmul = MxSet<eew>.m in {
+ foreach lmul = MxSet(eew) in {
defvar LInfo = lmul.MX;
let VLMul = lmul.value in {
- foreach nf = NFSet<lmul>.L in {
- defvar vreg = SegRegClass<lmul, nf>.RC;
+ foreach nf = NFSet(lmul) in {
+ defvar vreg = SegRegClass(lmul, nf);
def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegStoreNoMask<vreg, eew, nf>,
VSSSEGSched<nf, eew, LInfo>;
def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegStoreMask<vreg, eew, nf>,
@@ -3825,20 +3824,20 @@
multiclass VPseudoISegStore<bit Ordered> {
foreach idx_eew = EEWList in {
foreach sew = EEWList in {
- foreach val_lmul = MxSet<sew>.m in {
+ foreach val_lmul = MxSet(sew) in {
defvar octuple_lmul = val_lmul.octuple;
// Calculate emul = eew * lmul / sew
- defvar octuple_emul = !srl(!mul(idx_eew, octuple_lmul), log2<sew>.val);
+ defvar octuple_emul = !srl(!mul(idx_eew, octuple_lmul), log2(sew));
if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
defvar ValLInfo = val_lmul.MX;
- defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
+ defvar IdxLInfo = octuple_to_str(octuple_emul);
defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
defvar Vreg = val_lmul.vrclass;
defvar IdxVreg = idx_lmul.vrclass;
defvar Order = !if(Ordered, "O", "U");
let VLMul = val_lmul.value in {
- foreach nf = NFSet<val_lmul>.L in {
- defvar ValVreg = SegRegClass<val_lmul, nf>.RC;
+ foreach nf = NFSet(val_lmul) in {
+ defvar ValVreg = SegRegClass(val_lmul, nf);
def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo :
VPseudoISegStoreNoMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value,
nf, Ordered>,
@@ -4706,7 +4705,7 @@
multiclass VPatBinaryV_VV_INT_E<string intrinsic, string instruction,
list<VTypeInfo> vtilist> {
foreach vti = vtilist in {
- defvar ivti = GetIntVTypeInfo<vti>.Vti;
+ defvar ivti = GetIntVTypeInfo(vti);
defm : VPatBinaryTA<intrinsic,
instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW,
vti.Vector, vti.Vector, ivti.Vector, vti.Mask,
@@ -4723,7 +4722,7 @@
defvar octuple_lmul = vlmul.octuple;
defvar octuple_emul = !srl(!mul(octuple_lmul, eew), vti.Log2SEW);
if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
- defvar emul_str = octuple_to_str<octuple_emul>.ret;
+ defvar emul_str = octuple_to_str(octuple_emul);
defvar ivti = !cast<VTypeInfo>("VI" # eew # emul_str);
defvar inst = instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str;
defm : VPatBinaryTA<intrinsic, inst,
@@ -5297,7 +5296,7 @@
{
foreach fvti = AllFloatVectors in
{
- defvar ivti = GetIntVTypeInfo<fvti>.Vti;
+ defvar ivti = GetIntVTypeInfo(fvti);
defm : VPatConversionTA<intrinsic, instruction, "V",
ivti.Vector, fvti.Vector, ivti.Mask, fvti.Log2SEW,
@@ -5310,7 +5309,7 @@
{
foreach fvti = AllFloatVectors in
{
- defvar ivti = GetIntVTypeInfo<fvti>.Vti;
+ defvar ivti = GetIntVTypeInfo(fvti);
defm : VPatConversionTA<intrinsic, instruction, "V",
fvti.Vector, ivti.Vector, fvti.Mask, ivti.Log2SEW,
@@ -5322,7 +5321,7 @@
foreach fvtiToFWti = AllWidenableFloatVectors in
{
defvar fvti = fvtiToFWti.Vti;
- defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
+ defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti);
defm : VPatConversionTA<intrinsic, instruction, "V",
iwti.Vector, fvti.Vector, iwti.Mask, fvti.Log2SEW,
@@ -5370,7 +5369,7 @@
foreach fvtiToFWti = AllWidenableFloatVectors in
{
defvar fvti = fvtiToFWti.Vti;
- defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
+ defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti);
defm : VPatConversionTA<intrinsic, instruction, "W",
fvti.Vector, iwti.Vector, fvti.Mask, fvti.Log2SEW,
@@ -5435,8 +5434,8 @@
PseudoInstExpansion<(CSRRS GPR:$rd, SysRegVL.Encoding, X0)>;
foreach lmul = MxList in {
- foreach nf = NFSet<lmul>.L in {
- defvar vreg = SegRegClass<lmul, nf>.RC;
+ foreach nf = NFSet(lmul) in {
+ defvar vreg = SegRegClass(lmul, nf);
let hasSideEffects = 0, mayLoad = 0, mayStore = 1, isCodeGenOnly = 1,
Size = !mul(4, !sub(!mul(nf, 2), 1)) in {
def "PseudoVSPILL" # nf # "_" # lmul.MX :
Index: clang/include/clang/Basic/riscv_vector.td
===================================================================
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -907,8 +907,8 @@
about any masked-off elements.
*/
-class PVString<int nf, bit signed> {
- string S =
+function PVString(int nf, bit signed): string {
+ return
!cond(!eq(nf, 2): !if(signed, "PvPv", "PUvPUv"),
!eq(nf, 3): !if(signed, "PvPvPv", "PUvPUvPUv"),
!eq(nf, 4): !if(signed, "PvPvPvPv", "PUvPUvPUvPUv"),
@@ -972,8 +972,8 @@
return V;
}
}] in {
- defvar PV = PVString<nf, /*signed=*/true>.S;
- defvar PUV = PVString<nf, /*signed=*/false>.S;
+ defvar PV = PVString(nf, /*signed=*/true);
+ defvar PUV = PVString(nf, /*signed=*/false);
def : RVVBuiltin<"v", "0" # PV # "PCe", type>;
if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "0" # PUV # "PCUe", type>;
@@ -1039,8 +1039,8 @@
return Builder.CreateStore(Val, Address(NewVLOperand, Val->getType(), Align));
}
}] in {
- defvar PV = PVString<nf, /*signed=*/true>.S;
- defvar PUV = PVString<nf, /*signed=*/false>.S;
+ defvar PV = PVString(nf, /*signed=*/true);
+ defvar PUV = PVString(nf, /*signed=*/false);
def : RVVBuiltin<"v", "0" # PV # "PCe" # "Pz", type>;
if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "0" # PUV # "PCUe" # "Pz", type>;
@@ -1106,8 +1106,8 @@
return V;
}
}] in {
- defvar PV = PVString<nf, /*signed=*/true>.S;
- defvar PUV = PVString<nf, /*signed=*/false>.S;
+ defvar PV = PVString(nf, /*signed=*/true);
+ defvar PUV = PVString(nf, /*signed=*/false);
def : RVVBuiltin<"v", "0" # PV # "PCe" # "t", type>;
if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "0" # PUV # "PCUe" # "t", type>;
@@ -1169,8 +1169,8 @@
return V;
}
}] in {
- defvar PV = PVString<nf, /*signed=*/true>.S;
- defvar PUV = PVString<nf, /*signed=*/false>.S;
+ defvar PV = PVString(nf, /*signed=*/true);
+ defvar PUV = PVString(nf, /*signed=*/false);
def : RVVBuiltin<"v", "0" # PV # "PCe" # eew_type # "Uv", type>;
if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "0" # PUV # "PCUe" # eew_type # "Uv", type>;
@@ -1181,14 +1181,14 @@
}
}
-class VString<int nf, bit signed> {
- string S = !cond(!eq(nf, 2): !if(signed, "vv", "UvUv"),
- !eq(nf, 3): !if(signed, "vvv", "UvUvUv"),
- !eq(nf, 4): !if(signed, "vvvv", "UvUvUvUv"),
- !eq(nf, 5): !if(signed, "vvvvv", "UvUvUvUvUv"),
- !eq(nf, 6): !if(signed, "vvvvvv", "UvUvUvUvUvUv"),
- !eq(nf, 7): !if(signed, "vvvvvvv", "UvUvUvUvUvUvUv"),
- !eq(nf, 8): !if(signed, "vvvvvvvv", "UvUvUvUvUvUvUvUv"));
+function VString(int nf, bit signed): string {
+ return !cond(!eq(nf, 2): !if(signed, "vv", "UvUv"),
+ !eq(nf, 3): !if(signed, "vvv", "UvUvUv"),
+ !eq(nf, 4): !if(signed, "vvvv", "UvUvUvUv"),
+ !eq(nf, 5): !if(signed, "vvvvv", "UvUvUvUvUv"),
+ !eq(nf, 6): !if(signed, "vvvvvv", "UvUvUvUvUvUv"),
+ !eq(nf, 7): !if(signed, "vvvvvvv", "UvUvUvUvUvUvUv"),
+ !eq(nf, 8): !if(signed, "vvvvvvvv", "UvUvUvUvUvUvUvUv"));
}
multiclass RVVUnitStridedSegStore<string op> {
@@ -1225,8 +1225,8 @@
}
}
}] in {
- defvar V = VString<nf, /*signed=*/true>.S;
- defvar UV = VString<nf, /*signed=*/false>.S;
+ defvar V = VString(nf, /*signed=*/true);
+ defvar UV = VString(nf, /*signed=*/false);
def : RVVBuiltin<"v", "0Pe" # V, type>;
if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "0PUe" # UV, type>;
@@ -1269,8 +1269,8 @@
IntrinsicTypes = {Ops[0]->getType(), Ops[NF + 1]->getType()};
}
}] in {
- defvar V = VString<nf, /*signed=*/true>.S;
- defvar UV = VString<nf, /*signed=*/false>.S;
+ defvar V = VString(nf, /*signed=*/true);
+ defvar UV = VString(nf, /*signed=*/false);
def : RVVBuiltin<"v", "0Pet" # V, type>;
if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "0PUet" # UV, type>;
@@ -1312,8 +1312,8 @@
}
}
}] in {
- defvar V = VString<nf, /*signed=*/true>.S;
- defvar UV = VString<nf, /*signed=*/false>.S;
+ defvar V = VString(nf, /*signed=*/true);
+ defvar UV = VString(nf, /*signed=*/false);
def : RVVBuiltin<"v", "0Pe" # eew_type # "Uv" # V, type>;
if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "0PUe" # eew_type # "Uv" # UV, type>;
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