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https://github.com/llvm/llvm-project/pull/120936
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sunshaoce wrote:
Gently ping.
https://github.com/llvm/llvm-project/pull/120936
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>From 3efc4c7e0dab2714f5e776c513242d2df956c25e Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Mon, 23 Dec 2024 14:54:06 +0800
Subject: [PATCH 1/2] [RISCV] Add support of Sdext,Sdtrig extention
The full spec
@@ -842,6 +842,12 @@ def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
AssemblerPredicate<(all_of FeatureStdExtH),
"'H' (Hypervisor)">;
+// Debugger extensions
sunshaoce wrote:
Done. Thanks!
https://g
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/120936
>From 4a44a8551cc8e2c790bec2b6b4300e002216bfc0 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Mon, 23 Dec 2024 14:54:06 +0800
Subject: [PATCH 1/2] [RISCV] Add support of Sdext,Sdtrig extention
The full spec
https://github.com/sunshaoce created
https://github.com/llvm/llvm-project/pull/120936
`Sdext` and `Sdtrig` are RISC-V extensions related to debugging.
The full specification can be found at
https://github.com/riscv/riscv-debug-spec/releases/download/1.0.0-rc4/riscv-debug-specification.pdf
>Fro
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@@ -22,11 +24,21 @@
// uses the record name by replacing Feature with Has.
// value - Value to assign to the field in RISCVSubtarget when this
// extension is enabled. Usually "true", but can be changed.
-class RISCVExtension implies = [],
@@ -12,21 +12,32 @@
// Subclass of SubtargetFeature to be used when the feature is also a RISC-V
// extension. Extensions have a version and may be experimental.
+// NOTE: The extension name must start with
+// - "FeatureStdExt" for standard extensions
+// - "Featu
@@ -12,21 +12,32 @@
// Subclass of SubtargetFeature to be used when the feature is also a RISC-V
// extension. Extensions have a version and may be experimental.
+// NOTE: The extension name must start with
+// - "FeatureStdExt" for standard extensions
+// - "Featu
@@ -22,11 +22,20 @@
// uses the record name by replacing Feature with Has.
// value - Value to assign to the field in RISCVSubtarget when this
// extension is enabled. Usually "true", but can be changed.
-class RISCVExtension implies = [],
@@ -22,11 +22,17 @@
// uses the record name by replacing Feature with Has.
// value - Value to assign to the field in RISCVSubtarget when this
// extension is enabled. Usually "true", but can be changed.
-class RISCVExtension implies = [],
https://github.com/sunshaoce created
https://github.com/llvm/llvm-project/pull/105476
Ratified: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0
>From acffcc86ffd145849ffeb884ab31d32c5cff5710 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Wed, 21 Aug 2024 15:12:32 +0800
Subject: [PAT
https://github.com/sunshaoce closed
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@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/94564
>From 363e29385277c049bc91a86e76ff6f6ae70ceaa9 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Thu, 6 Jun 2024 12:05:33 +0800
Subject: [PATCH 1/8] [RISCV] Add processor definition for Spacemit-K1
---
clang/t
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+
https://github.com/sunshaoce edited
https://github.com/llvm/llvm-project/pull/94564
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@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+
sunshaoce wrote:
> Could you explain these numbers? It looks like data in some columns is
> missing.
I only ran the default `base metrics` once. The geometric mean of this
`Estimated Base Ratio` column can be regarded as the comprehensive score for
this item.
[Q14. What is the difference be
sunshaoce wrote:
I've tested this patch with `spec 2006 int`. Everything seems to be running
smoothly:
```
Estimated Estimated
Base Base BasePeak Peak Peak
Benchmarks Ref. Run Time Rati
@@ -381,3 +381,21 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/94564
>From 363e29385277c049bc91a86e76ff6f6ae70ceaa9 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Thu, 6 Jun 2024 12:05:33 +0800
Subject: [PATCH 1/7] [RISCV] Add processor definition for Spacemit-K1
---
clang/t
sunshaoce wrote:
Added:
- Sscofpmf
- Sstc
- Zvkt
- TuneDLenFactor2
Removed:
- Zvl32b
- Zvl64b
- Zvl128b
https://github.com/llvm/llvm-project/pull/94564
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>From 363e29385277c049bc91a86e76ff6f6ae70ceaa9 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Thu, 6 Jun 2024 12:05:33 +0800
Subject: [PATCH 1/6] [RISCV] Add processor definition for Spacemit-K1
---
clang/t
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+
https://github.com/sunshaoce edited
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sunshaoce wrote:
All done. Thanks!
Is there anything else that needs to be modified?
https://github.com/llvm/llvm-project/pull/94564
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>From 363e29385277c049bc91a86e76ff6f6ae70ceaa9 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Thu, 6 Jun 2024 12:05:33 +0800
Subject: [PATCH 1/5] [RISCV] Add processor definition for Spacemit-K1
---
clang/t
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/94564
>From 363e29385277c049bc91a86e76ff6f6ae70ceaa9 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Thu, 6 Jun 2024 12:05:33 +0800
Subject: [PATCH 1/4] [RISCV] Add processor definition for Spacemit-K1
---
clang/t
https://github.com/sunshaoce edited
https://github.com/llvm/llvm-project/pull/94564
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@@ -381,3 +381,14 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/94564
>From 363e29385277c049bc91a86e76ff6f6ae70ceaa9 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Thu, 6 Jun 2024 12:05:33 +0800
Subject: [PATCH 1/3] [RISCV] Add processor definition for Spacemit-K1
---
clang/t
@@ -381,3 +381,32 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/94564
>From 363e29385277c049bc91a86e76ff6f6ae70ceaa9 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Thu, 6 Jun 2024 12:05:33 +0800
Subject: [PATCH 1/2] [RISCV] Add processor definition for Spacemit-K1
---
clang/t
https://github.com/sunshaoce edited
https://github.com/llvm/llvm-project/pull/94564
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https://github.com/sunshaoce created
https://github.com/llvm/llvm-project/pull/94564
Spacemit-k1 is a new 8-core CPU that supports RVV 1.0, and it is now integrated
into the BPi-F3 development board.
Through [ruapo](https://github.com/nihui/ruapu) detection, this is the march
information of
@@ -0,0 +1,142 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --check-globals all --include-generated-funcs --version 4
+// RUN: %clang_cc1 -triple riscv64-linux-gnu -target-feature +i -S -emit-llvm
-o - %s | FileCheck %s
+
+__attribu
sunshaoce wrote:
> > > By the way, is there any plan to support `CFLUSH.I.L1` in the future?
> >
> >
> > Flushing the instruction cache doesn't make sense given it can never be
> > dirty. Invalidating/discarding does, but that's just what fence.i is doing?
>
> A cflush.i.l1 did appear in some
sunshaoce wrote:
By the way, is there any plan to support `CFLUSH.I.L1` in the future?
https://github.com/llvm/llvm-project/pull/83896
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sunshaoce wrote:
I tried compiling it and then got two warnings.
```
llvm-project/clang/lib/CodeGen/CGDebugInfo.cpp:1408:11: warning: enumeration
value 'CC_RISCVVectorCall' not handled in switch [-Wswitch]
1408 | switch (CC) {
| ^~
1 warning generated.
[3629/3776] Building CXX
https://github.com/sunshaoce closed
https://github.com/llvm/llvm-project/pull/71140
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>From d8d0fcdd00b422e48af733ef638fe9857a05686e Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Fri, 3 Nov 2023 11:50:58 +0800
Subject: [PATCH 1/6] [RISCV][Clang] Add bf16-type vector support for RVV
---
clan
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/71140
>From d8d0fcdd00b422e48af733ef638fe9857a05686e Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Fri, 3 Nov 2023 11:50:58 +0800
Subject: [PATCH 1/5] [RISCV][Clang] Add bf16-type vector support for RVV
---
clan
@@ -6046,6 +6046,13 @@ void Sema::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, Decl *D) {
!TI.hasFeature("zvfh") && !TI.hasFeature("zvfhmin"))
Diag(Loc, diag::err_riscv_type_requires_extension, D)
<< Ty << "zvfh or zvfhmin";
+ // Check if enabled zfb
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/71140
>From d8d0fcdd00b422e48af733ef638fe9857a05686e Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Fri, 3 Nov 2023 11:50:58 +0800
Subject: [PATCH 1/4] [RISCV][Clang] Add bf16-type vector support for RVV
---
clan
sunshaoce wrote:
> I believe we need to update `Sema::checkRVVTypeSupport` too
Addressed.
https://github.com/llvm/llvm-project/pull/71140
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>From d8d0fcdd00b422e48af733ef638fe9857a05686e Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Fri, 3 Nov 2023 11:50:58 +0800
Subject: [PATCH 1/3] [RISCV][Clang] Add bf16-type vector support for RVV
---
clan
https://github.com/sunshaoce edited
https://github.com/llvm/llvm-project/pull/71140
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https://github.com/sunshaoce created
https://github.com/llvm/llvm-project/pull/71140
BF16 implementation based on @joshua-arch1's https://reviews.llvm.org/D152498
Fixed the incorrect f16 type introduced in
https://github.com/llvm/llvm-project/pull/68296
-
Co-authored-by: Jun Sha (Josh
@@ -813,6 +813,14 @@ def HasVendorXSfcie :
Predicate<"Subtarget->hasVendorXSfcie()">,
AssemblerPredicate<(all_of FeatureVendorXSfcie),
"'XSfcie' (SiFive Custom Instruction Extension
SCIE.)">;
+def FeatureVendorXSfvfwmaccqqq
+
@@ -103,3 +103,15 @@ let SupportOverloading = false in {
defm sf_vc_v_fvw : RVVVCIXBuiltinSet<["si"], "UwKzUwUvFe", [-1, 0, 2, 3],
UseGPR=0>;
}
}
+
+multiclass RVVVFWMACCBuiltinSet> suffixes_prototypes> {
+ let OverloadedName = NAME,
+ Name = NAME,
+ HasMaske
@@ -0,0 +1,307 @@
+//==- RISCVSchedXiangShanNanHu.td - XiangShan-NanHu Scheduling Definitions
--*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License
sunshaoce wrote:
LGTM. If no one else has any objections, I think we can merge it.
https://github.com/llvm/llvm-project/pull/68295
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@@ -178,6 +178,19 @@ multiclass CustomSiFiveVCIX;
}
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+class CustomSiFiveVMACC funct6, RISCVVFormat opv, string opcodestr>
+: RVInstVCCustom2 {
+ let vm = 1;
+ let funct6_lo2 = funct6{1-0};
+}
+}
+
+multiclass CustomSi
sunshaoce wrote:
`clang/test/Preprocessor/riscv-target-features.c` need to be modified.
https://github.com/llvm/llvm-project/pull/68295
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@@ -103,3 +103,27 @@ let SupportOverloading = false in {
defm sf_vc_v_fvw : RVVVCIXBuiltinSet<["si"], "UwKzUwUvFe", [-1, 0, 2, 3],
UseGPR=0>;
}
}
+
+multiclass RVVVQMACCBuiltinSet> suffixes_prototypes> {
+ let OverloadedName = NAME,
+ Name = NAME,
+ HasMasked
@@ -178,6 +178,19 @@ multiclass CustomSiFiveVCIX;
}
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+class CustomSiFiveVMACC funct6, RISCVVFormat opv, string opcodestr>
+: RVInstVCCustom2 {
+ let vm = 1;
+ let funct6_lo2 = funct6{1-0};
+}
+}
+
+multiclass CustomSi
@@ -0,0 +1,57 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding
--mattr=+v,+xsfvqmaccqoq,+xsfvqmaccdod %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-
@@ -630,7 +630,7 @@ TEST(getTargetFeatureForExtension,
RetrieveTargetFeatureFromOneExt) {
TEST(RiscvExtensionsHelp, CheckExtensions) {
std::string ExpectedOutput =
-R"(All available -march extensions for RISC-V
+ R"(All available -march extensions for RISC-V
--
" + sys::path::filename(Record.getInputFilename()),"
In-Reply-To:
https://github.com/sunshaoce closed
https://github.com/llvm/llvm-project/pull/65744
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" + sys::path::filename(Record.getInputFilename()),"
In-Reply-To:
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/65744
>From 8fd7007fa437a0eefb66015861f76f65095c31bc Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Sat, 23 Sep 2023 11:38:33 +0800
Subject: [PATC
" + sys::path::filename(Record.getInputFilename()),"
In-Reply-To:
https://github.com/sunshaoce edited
https://github.com/llvm/llvm-project/pull/65744
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" + sys::path::filename(Record.getInputFilename()),"
In-Reply-To:
sunshaoce wrote:
Addressed. Thanks! Now it is
```
/*===- TableGen'erated file -*- C++ -*-===*\
|**|
|* ValueTypes Sou
" + sys::path::filename(Record.getInputFilename()),"
In-Reply-To:
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/65744
>From 23d0b738bf40ea44e159f4f8d7355d4d6bc0688d Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Sat, 23 Sep 2023 11:38:33 +0800
Subject: [PATC
sunshaoce wrote:
I am not sure how to keep only the `llvm-project//Filename` path except by
hard-coding. Or how to keep only the base file name? This could limit it to
within 80 characters.
https://github.com/llvm/llvm-project/pull/65744
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sunshaoce wrote:
> ⚠️ C/C++ code formatter, clang-format found issues in your code. ⚠️
>
> You can test this locally with the following command:
> ```shell
> git-clang-format --diff b8b4ee6b450766796b162b4811a6b3f723d07268
> d07486764071679c8cbcd5e7c4905eb41b4770b3 --
> clang/utils/TableGen/Cl
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/65744
>From 23d0b738bf40ea44e159f4f8d7355d4d6bc0688d Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Sat, 23 Sep 2023 11:38:33 +0800
Subject: [PATCH 1/2] [llvm][tblgen] Add `SourcePath` for
`emitSourceFileHeader`
Author: Shao-Ce SUN
Date: 2023-04-28T09:53:25+08:00
New Revision: 876df74dd47196a9ca3b4fff21ffb5441491a0a0
URL:
https://github.com/llvm/llvm-project/commit/876df74dd47196a9ca3b4fff21ffb5441491a0a0
DIFF:
https://github.com/llvm/llvm-project/commit/876df74dd47196a9ca3b4fff21ffb5441491a0a0.diff
L
Author: Shao-Ce SUN
Date: 2023-03-15T19:39:13+08:00
New Revision: 36278b735fa193c954bf38c82ca81a5608bc5187
URL:
https://github.com/llvm/llvm-project/commit/36278b735fa193c954bf38c82ca81a5608bc5187
DIFF:
https://github.com/llvm/llvm-project/commit/36278b735fa193c954bf38c82ca81a5608bc5187.diff
L
Author: Shao-Ce SUN
Date: 2023-03-12T01:11:42+08:00
New Revision: b1fdcd5fbc09f9f3e1c8a8b954aa8f9067401b31
URL:
https://github.com/llvm/llvm-project/commit/b1fdcd5fbc09f9f3e1c8a8b954aa8f9067401b31
DIFF:
https://github.com/llvm/llvm-project/commit/b1fdcd5fbc09f9f3e1c8a8b954aa8f9067401b31.diff
L
Author: Shao-Ce SUN
Date: 2023-03-12T00:06:09+08:00
New Revision: 56cc0bbe41fd41fb0766062ca0975eba64e92447
URL:
https://github.com/llvm/llvm-project/commit/56cc0bbe41fd41fb0766062ca0975eba64e92447
DIFF:
https://github.com/llvm/llvm-project/commit/56cc0bbe41fd41fb0766062ca0975eba64e92447.diff
L
Author: Shao-Ce SUN
Date: 2023-03-11T23:23:21+08:00
New Revision: 171794de533b400edb47f0e6df4375a7ae052fc8
URL:
https://github.com/llvm/llvm-project/commit/171794de533b400edb47f0e6df4375a7ae052fc8
DIFF:
https://github.com/llvm/llvm-project/commit/171794de533b400edb47f0e6df4375a7ae052fc8.diff
L
Author: Shao-Ce SUN
Date: 2022-08-22T12:06:30+08:00
New Revision: 7167a4207ee2c07cb192da1788f919332f83b456
URL:
https://github.com/llvm/llvm-project/commit/7167a4207ee2c07cb192da1788f919332f83b456
DIFF:
https://github.com/llvm/llvm-project/commit/7167a4207ee2c07cb192da1788f919332f83b456.diff
L
Author: Shao-Ce SUN
Date: 2022-06-15T22:25:22+08:00
New Revision: e180cc5ff1a133c533e68bb92024d2455d5e6978
URL:
https://github.com/llvm/llvm-project/commit/e180cc5ff1a133c533e68bb92024d2455d5e6978
DIFF:
https://github.com/llvm/llvm-project/commit/e180cc5ff1a133c533e68bb92024d2455d5e6978.diff
L
Author: Shao-Ce SUN
Date: 2022-03-05T13:57:18+08:00
New Revision: fa9c8bab0c7a7aed423191baa8a980533ae5602a
URL:
https://github.com/llvm/llvm-project/commit/fa9c8bab0c7a7aed423191baa8a980533ae5602a
DIFF:
https://github.com/llvm/llvm-project/commit/fa9c8bab0c7a7aed423191baa8a980533ae5602a.diff
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Author: Shao-Ce SUN
Date: 2022-02-24T19:12:34+08:00
New Revision: a8b4b9104c8f7ab5edb8651a900e61279e8bf931
URL:
https://github.com/llvm/llvm-project/commit/a8b4b9104c8f7ab5edb8651a900e61279e8bf931
DIFF:
https://github.com/llvm/llvm-project/commit/a8b4b9104c8f7ab5edb8651a900e61279e8bf931.diff
L
Author: Shao-Ce SUN
Date: 2022-02-16T11:57:49+08:00
New Revision: 9cc49c1951dcc4db594bf1f90755e16f89efd1ca
URL:
https://github.com/llvm/llvm-project/commit/9cc49c1951dcc4db594bf1f90755e16f89efd1ca
DIFF:
https://github.com/llvm/llvm-project/commit/9cc49c1951dcc4db594bf1f90755e16f89efd1ca.diff
L
Author: Shao-Ce SUN
Date: 2022-01-05T14:49:03+08:00
New Revision: 62b59c59a6d9bab0c45808dcb96cf09047b9cba1
URL:
https://github.com/llvm/llvm-project/commit/62b59c59a6d9bab0c45808dcb96cf09047b9cba1
DIFF:
https://github.com/llvm/llvm-project/commit/62b59c59a6d9bab0c45808dcb96cf09047b9cba1.diff
L
Author: Shao-Ce SUN
Date: 2021-12-27T14:16:08+08:00
New Revision: ec501f15a8b8ace2b283732740d6d65d40d82e09
URL:
https://github.com/llvm/llvm-project/commit/ec501f15a8b8ace2b283732740d6d65d40d82e09
DIFF:
https://github.com/llvm/llvm-project/commit/ec501f15a8b8ace2b283732740d6d65d40d82e09.diff
L
Author: Shao-Ce SUN
Date: 2021-11-06T01:41:02+08:00
New Revision: 5c3d7184b43575e4cbf1da2fa6ba88485eaca4e3
URL:
https://github.com/llvm/llvm-project/commit/5c3d7184b43575e4cbf1da2fa6ba88485eaca4e3
DIFF:
https://github.com/llvm/llvm-project/commit/5c3d7184b43575e4cbf1da2fa6ba88485eaca4e3.diff
L
Author: Shao-Ce Sun
Date: 2021-09-14T08:55:22+08:00
New Revision: d4f25d0046fc9d1a42d9974e75cfba14ff3d535e
URL:
https://github.com/llvm/llvm-project/commit/d4f25d0046fc9d1a42d9974e75cfba14ff3d535e
DIFF:
https://github.com/llvm/llvm-project/commit/d4f25d0046fc9d1a42d9974e75cfba14ff3d535e.diff
L
Author: Shao-Ce Sun
Date: 2021-02-25T21:25:43+08:00
New Revision: ad14ccc8c22e1480db7bfc1a176311e6f572c588
URL:
https://github.com/llvm/llvm-project/commit/ad14ccc8c22e1480db7bfc1a176311e6f572c588
DIFF:
https://github.com/llvm/llvm-project/commit/ad14ccc8c22e1480db7bfc1a176311e6f572c588.diff
L
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