https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/94564
>From 363e29385277c049bc91a86e76ff6f6ae70ceaa9 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN <sunsha...@outlook.com>
Date: Thu, 6 Jun 2024 12:05:33 +0800
Subject: [PATCH 1/5] [RISCV] Add processor definition for Spacemit-K1
---
clang/test/Driver/riscv-cpus.c | 12 ++++++++++
clang/test/Misc/target-invalid-cpu-note.c | 4 ++--
llvm/lib/Target/RISCV/RISCVProcessors.td | 29 +++++++++++++++++++++++
3 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba3..32d7910ab4daa 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,6 +31,18 @@
// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature"
"+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
// MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-k1 | FileCheck
-check-prefix=MCPU-SPACEMIT-K1 %s
+// MCPU-SPACEMIT-K1: "-nostdsysteminc" "-target-cpu" "spacemit-k1"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+c" "-target-feature" "+v"
"-target-feature" "+zicond" "-target-feature" "+zicsr"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zifencei" "-target-feature"
"+zmmul" "-target-feature" "+zfh"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zfhmin" "-target-feature" "+zba"
"-target-feature" "+zbb" "-target-feature" "+zbc"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zbkb" "-target-feature" "+zbkc"
"-target-feature" "+zbs" "-target-feature" "+zve32f"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zve32x" "-target-feature"
"+zve64d" "-target-feature" "+zve64f" "-target-feature" "+zve64x"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvfh" "-target-feature"
"+zvfhmin"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvl128b" "-target-feature"
"+zvl256b" "-target-feature" "+zvl32b" "-target-feature" "+zvl64b"
+// MCPU-SPACEMIT-K1-SAME: "-target-abi" "lp64d"
+
// We cannot check much for -mcpu=native, but it should be replaced by a valid
CPU string.
// RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
// RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index 6558fd753d1d1..04e92360fe665 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1,
xiangshan-nanhu{{$}}
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu,
generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1,
xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6ebf9f1eb0452..08602e9d06cc9 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -381,3 +381,32 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_K1 : RISCVProcessorModel<"spacemit-k1",
+ NoSchedModel,
+ [Feature64Bit,
+ FeatureStdExtI,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtV,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbc,
+ FeatureStdExtZbs,
+ FeatureStdExtZbkb,
+ FeatureStdExtZbkc,
+ FeatureStdExtZfh,
+ FeatureStdExtZfhmin,
+ FeatureStdExtZicond,
+ FeatureStdExtZicsr,
+ FeatureStdExtZifencei,
+ FeatureStdExtZmmul,
+ FeatureStdExtZvfh,
+ FeatureStdExtZvfhmin,
+ FeatureStdExtZvl32b,
+ FeatureStdExtZvl64b,
+ FeatureStdExtZvl128b,
+ FeatureStdExtZvl256b]>;
>From 4c1dccc2f927b1a8e77ea34d7b9afa27fb731ffc Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN <sunsha...@outlook.com>
Date: Thu, 6 Jun 2024 13:25:48 +0800
Subject: [PATCH 2/5] fixup! Update RISCVProcessors.td
---
clang/test/Driver/riscv-cpus.c | 19 +++++++++++--------
llvm/lib/Target/RISCV/RISCVProcessors.td | 24 +++---------------------
2 files changed, 14 insertions(+), 29 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 32d7910ab4daa..3a3313e7565d2 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -33,14 +33,17 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-k1 | FileCheck
-check-prefix=MCPU-SPACEMIT-K1 %s
// MCPU-SPACEMIT-K1: "-nostdsysteminc" "-target-cpu" "spacemit-k1"
-// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d"
-// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+c" "-target-feature" "+v"
"-target-feature" "+zicond" "-target-feature" "+zicsr"
-// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zifencei" "-target-feature"
"+zmmul" "-target-feature" "+zfh"
-// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zfhmin" "-target-feature" "+zba"
"-target-feature" "+zbb" "-target-feature" "+zbc"
-// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zbkb" "-target-feature" "+zbkc"
"-target-feature" "+zbs" "-target-feature" "+zve32f"
-// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zve32x" "-target-feature"
"+zve64d" "-target-feature" "+zve64f" "-target-feature" "+zve64x"
-// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvfh" "-target-feature"
"+zvfhmin"
-// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvl128b" "-target-feature"
"+zvl256b" "-target-feature" "+zvl32b" "-target-feature" "+zvl64b"
+// MCPU-SPACEMIT-K1: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c"
+// MCPU-SPACEMIT-K1: "-target-feature" "+v" "-target-feature" "+zic64b"
"-target-feature" "+zicbom" "-target-feature" "+zicbop"
+// MCPU-SPACEMIT-K1: "-target-feature" "+zicboz" "-target-feature" "+ziccamoa"
"-target-feature" "+ziccif" "-target-feature" "+zicclsm"
+// MCPU-SPACEMIT-K1: "-target-feature" "+ziccrse" "-target-feature" "+zicntr"
"-target-feature" "+zicsr" "-target-feature" "+zifencei"
+// MCPU-SPACEMIT-K1: "-target-feature" "+zihintpause" "-target-feature"
"+zihpm" "-target-feature" "+za64rs" "-target-feature" "+zfhmin"
+// MCPU-SPACEMIT-K1: "-target-feature" "+zba" "-target-feature" "+zbb"
"-target-feature" "+zbs" "-target-feature" "+zkt"
+// MCPU-SPACEMIT-K1: "-target-feature" "+zve32f" "-target-feature" "+zve32x"
"-target-feature" "+zve64d" "-target-feature" "+zve64f"
+// MCPU-SPACEMIT-K1: "-target-feature" "+zve64x" "-target-feature" "+zvfh"
"-target-feature" "+zvfhmin" "-target-feature" "+zvl128b"
+// MCPU-SPACEMIT-K1: "-target-feature" "+zvl256b" "-target-feature" "+zvl32b"
"-target-feature" "+zvl64b" "-target-feature" "+ssccptr"
+// MCPU-SPACEMIT-K1: "-target-feature" "+sscounterenw" "-target-feature"
"+sstvala" "-target-feature" "+sstvecd" "-target-feature" "+svade"
+// MCPU-SPACEMIT-K1: "-target-feature" "+svbare" "-target-feature" "+svinval"
"-target-feature" "+svpbmt"
// MCPU-SPACEMIT-K1-SAME: "-target-abi" "lp64d"
// We cannot check much for -mcpu=native, but it should be replaced by a valid
CPU string.
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 08602e9d06cc9..aa4ad9edc6b03 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -384,29 +384,11 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
def SPACEMIT_K1 : RISCVProcessorModel<"spacemit-k1",
NoSchedModel,
- [Feature64Bit,
- FeatureStdExtI,
- FeatureStdExtM,
- FeatureStdExtA,
- FeatureStdExtF,
- FeatureStdExtD,
- FeatureStdExtC,
- FeatureStdExtV,
- FeatureStdExtZba,
- FeatureStdExtZbb,
- FeatureStdExtZbc,
- FeatureStdExtZbs,
- FeatureStdExtZbkb,
- FeatureStdExtZbkc,
- FeatureStdExtZfh,
- FeatureStdExtZfhmin,
- FeatureStdExtZicond,
- FeatureStdExtZicsr,
- FeatureStdExtZifencei,
- FeatureStdExtZmmul,
+ !listconcat(RVA22S64Features,
+ [FeatureStdExtV,
FeatureStdExtZvfh,
FeatureStdExtZvfhmin,
FeatureStdExtZvl32b,
FeatureStdExtZvl64b,
FeatureStdExtZvl128b,
- FeatureStdExtZvl256b]>;
+ FeatureStdExtZvl256b])>;
>From 620f8cca54551760191b46ace613375c1fca3549 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN <sunsha...@outlook.com>
Date: Thu, 6 Jun 2024 14:00:32 +0800
Subject: [PATCH 3/5] fixup! Use name spacemit-x60
---
clang/test/Driver/riscv-cpus.c | 28 +++++++++++------------
clang/test/Misc/target-invalid-cpu-note.c | 4 ++--
llvm/lib/Target/RISCV/RISCVProcessors.td | 20 ++++++++--------
3 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 3a3313e7565d2..001c4ffa2b7a8 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,20 +31,20 @@
// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature"
"+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
// MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
-// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-k1 | FileCheck
-check-prefix=MCPU-SPACEMIT-K1 %s
-// MCPU-SPACEMIT-K1: "-nostdsysteminc" "-target-cpu" "spacemit-k1"
-// MCPU-SPACEMIT-K1: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c"
-// MCPU-SPACEMIT-K1: "-target-feature" "+v" "-target-feature" "+zic64b"
"-target-feature" "+zicbom" "-target-feature" "+zicbop"
-// MCPU-SPACEMIT-K1: "-target-feature" "+zicboz" "-target-feature" "+ziccamoa"
"-target-feature" "+ziccif" "-target-feature" "+zicclsm"
-// MCPU-SPACEMIT-K1: "-target-feature" "+ziccrse" "-target-feature" "+zicntr"
"-target-feature" "+zicsr" "-target-feature" "+zifencei"
-// MCPU-SPACEMIT-K1: "-target-feature" "+zihintpause" "-target-feature"
"+zihpm" "-target-feature" "+za64rs" "-target-feature" "+zfhmin"
-// MCPU-SPACEMIT-K1: "-target-feature" "+zba" "-target-feature" "+zbb"
"-target-feature" "+zbs" "-target-feature" "+zkt"
-// MCPU-SPACEMIT-K1: "-target-feature" "+zve32f" "-target-feature" "+zve32x"
"-target-feature" "+zve64d" "-target-feature" "+zve64f"
-// MCPU-SPACEMIT-K1: "-target-feature" "+zve64x" "-target-feature" "+zvfh"
"-target-feature" "+zvfhmin" "-target-feature" "+zvl128b"
-// MCPU-SPACEMIT-K1: "-target-feature" "+zvl256b" "-target-feature" "+zvl32b"
"-target-feature" "+zvl64b" "-target-feature" "+ssccptr"
-// MCPU-SPACEMIT-K1: "-target-feature" "+sscounterenw" "-target-feature"
"+sstvala" "-target-feature" "+sstvecd" "-target-feature" "+svade"
-// MCPU-SPACEMIT-K1: "-target-feature" "+svbare" "-target-feature" "+svinval"
"-target-feature" "+svpbmt"
-// MCPU-SPACEMIT-K1-SAME: "-target-abi" "lp64d"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-x60 | FileCheck
-check-prefix=MCPU-SPACEMIT-X60 %s
+// MCPU-SPACEMIT-X60: "-nostdsysteminc" "-target-cpu" "spacemit-x60"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+v" "-target-feature" "+zic64b"
"-target-feature" "+zicbom" "-target-feature" "+zicbop"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicboz" "-target-feature"
"+ziccamoa" "-target-feature" "+ziccif" "-target-feature" "+zicclsm"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccrse" "-target-feature"
"+zicntr" "-target-feature" "+zicsr" "-target-feature" "+zifencei"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zihintpause" "-target-feature"
"+zihpm" "-target-feature" "+za64rs" "-target-feature" "+zfhmin"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"
"-target-feature" "+zbs" "-target-feature" "+zkt"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve32f" "-target-feature"
"+zve32x" "-target-feature" "+zve64d" "-target-feature" "+zve64f"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64x" "-target-feature"
"+zvfh" "-target-feature" "+zvfhmin" "-target-feature" "+zvl128b"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl256b" "-target-feature"
"+zvl32b" "-target-feature" "+zvl64b" "-target-feature" "+ssccptr"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sscounterenw" "-target-feature"
"+sstvala" "-target-feature" "+sstvecd" "-target-feature" "+svade"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svbare" "-target-feature"
"+svinval" "-target-feature" "+svpbmt"
+// MCPU-SPACEMIT-X60-SAME: "-target-abi" "lp64d"
// We cannot check much for -mcpu=native, but it should be replaced by a valid
CPU string.
// RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index 04e92360fe665..85fb5f102bee8 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1,
xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, spacemit-x60, veyron-v1,
xiangshan-nanhu{{$}}
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1,
xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, veyron-v1,
xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index aa4ad9edc6b03..a11458daf50de 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -382,13 +382,13 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
-def SPACEMIT_K1 : RISCVProcessorModel<"spacemit-k1",
- NoSchedModel,
- !listconcat(RVA22S64Features,
- [FeatureStdExtV,
- FeatureStdExtZvfh,
- FeatureStdExtZvfhmin,
- FeatureStdExtZvl32b,
- FeatureStdExtZvl64b,
- FeatureStdExtZvl128b,
- FeatureStdExtZvl256b])>;
+def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
+ NoSchedModel,
+ !listconcat(RVA22S64Features,
+ [FeatureStdExtV,
+ FeatureStdExtZvfh,
+ FeatureStdExtZvfhmin,
+ FeatureStdExtZvl32b,
+ FeatureStdExtZvl64b,
+ FeatureStdExtZvl128b,
+ FeatureStdExtZvl256b])>;
>From d0a6664c6d6dd5fec150a3158dcd3e5e992a318c Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN <sunsha...@outlook.com>
Date: Thu, 6 Jun 2024 18:00:24 +0800
Subject: [PATCH 4/5] fixup! Add missing extensions
---
clang/test/Driver/riscv-cpus.c | 25 ++++++++++++++----------
llvm/lib/Target/RISCV/RISCVProcessors.td | 5 +++++
2 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 001c4ffa2b7a8..de4263d418e3c 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -33,16 +33,21 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-x60 | FileCheck
-check-prefix=MCPU-SPACEMIT-X60 %s
// MCPU-SPACEMIT-X60: "-nostdsysteminc" "-target-cpu" "spacemit-x60"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+v" "-target-feature" "+zic64b"
"-target-feature" "+zicbom" "-target-feature" "+zicbop"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicboz" "-target-feature"
"+ziccamoa" "-target-feature" "+ziccif" "-target-feature" "+zicclsm"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccrse" "-target-feature"
"+zicntr" "-target-feature" "+zicsr" "-target-feature" "+zifencei"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zihintpause" "-target-feature"
"+zihpm" "-target-feature" "+za64rs" "-target-feature" "+zfhmin"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"
"-target-feature" "+zbs" "-target-feature" "+zkt"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve32f" "-target-feature"
"+zve32x" "-target-feature" "+zve64d" "-target-feature" "+zve64f"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64x" "-target-feature"
"+zvfh" "-target-feature" "+zvfhmin" "-target-feature" "+zvl128b"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl256b" "-target-feature"
"+zvl32b" "-target-feature" "+zvl64b" "-target-feature" "+ssccptr"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sscounterenw" "-target-feature"
"+sstvala" "-target-feature" "+sstvecd" "-target-feature" "+svade"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+c" "-target-feature" "+v"
"-target-feature" "+zic64b" "-target-feature" "+zicbom"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicbop" "-target-feature"
"+zicboz" "-target-feature" "+ziccamoa"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccif" "-target-feature"
"+zicclsm" "-target-feature" "+ziccrse"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicntr" "-target-feature"
"+zicond" "-target-feature" "+zicsr"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zifencei" "-target-feature"
"+zihintpause" "-target-feature" "+zihpm"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zmmul" "-target-feature"
"+za64rs" "-target-feature" "+zfh"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zfhmin" "-target-feature"
"+zba" "-target-feature" "+zbb"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbc" "-target-feature" "+zbkc"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbs" "-target-feature" "+zkt"
"-target-feature" "+zve32f"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve32x" "-target-feature"
"+zve64d" "-target-feature" "+zve64f"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64x" "-target-feature"
"+zvfh" "-target-feature" "+zvfhmin"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl128b" "-target-feature"
"+zvl256b" "-target-feature" "+zvl32b"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl64b" "-target-feature"
"+ssccptr" "-target-feature" "+sscounterenw"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstvala" "-target-feature"
"+sstvecd" "-target-feature" "+svade"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svbare" "-target-feature"
"+svinval" "-target-feature" "+svpbmt"
// MCPU-SPACEMIT-X60-SAME: "-target-abi" "lp64d"
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index a11458daf50de..f8896d0d2c93a 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -386,6 +386,11 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
NoSchedModel,
!listconcat(RVA22S64Features,
[FeatureStdExtV,
+ FeatureStdExtZbc,
+ FeatureStdExtZbkc,
+ FeatureStdExtZfh,
+ FeatureStdExtZicond,
+ FeatureStdExtZmmul,
FeatureStdExtZvfh,
FeatureStdExtZvfhmin,
FeatureStdExtZvl32b,
>From eb0d50dc5def0f6474475268e00a8f5511dcdefe Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN <sunsha...@outlook.com>
Date: Fri, 7 Jun 2024 14:03:14 +0800
Subject: [PATCH 5/5] fixup! Add svnapot ext
---
clang/test/Driver/riscv-cpus.c | 19 ++++++++++---------
llvm/lib/Target/RISCV/RISCVProcessors.td | 1 +
2 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index de4263d418e3c..fcd374de43600 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -34,21 +34,22 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-x60 | FileCheck
-check-prefix=MCPU-SPACEMIT-X60 %s
// MCPU-SPACEMIT-X60: "-nostdsysteminc" "-target-cpu" "spacemit-x60"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+c" "-target-feature" "+v"
"-target-feature" "+zic64b" "-target-feature" "+zicbom"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicbop" "-target-feature"
"+zicboz" "-target-feature" "+ziccamoa"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccif" "-target-feature"
"+zicclsm" "-target-feature" "+ziccrse"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicntr" "-target-feature"
"+zicond" "-target-feature" "+zicsr"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zifencei" "-target-feature"
"+zihintpause" "-target-feature" "+zihpm"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zmmul" "-target-feature"
"+za64rs" "-target-feature" "+zfh"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zfhmin" "-target-feature"
"+zba" "-target-feature" "+zbb"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbc" "-target-feature" "+zbkc"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+c" "-target-feature" "+v"
"-target-feature" "+zic64b"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicbom" "-target-feature"
"+zicbop" "-target-feature" "+zicboz"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccamoa" "-target-feature"
"+ziccif" "-target-feature" "+zicclsm"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccrse" "-target-feature"
"+zicntr" "-target-feature" "+zicond"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicsr" "-target-feature"
"+zifencei" "-target-feature" "+zihintpause"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zihpm" "-target-feature"
"+zmmul" "-target-feature" "+za64rs"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zfh" "-target-feature"
"+zfhmin" "-target-feature" "+zba"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbb" "-target-feature" "+zbc"
"-target-feature" "+zbkc"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbs" "-target-feature" "+zkt"
"-target-feature" "+zve32f"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve32x" "-target-feature"
"+zve64d" "-target-feature" "+zve64f"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64x" "-target-feature"
"+zvfh" "-target-feature" "+zvfhmin"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl128b" "-target-feature"
"+zvl256b" "-target-feature" "+zvl32b"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl64b" "-target-feature"
"+ssccptr" "-target-feature" "+sscounterenw"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstvala" "-target-feature"
"+sstvecd" "-target-feature" "+svade"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svbare" "-target-feature"
"+svinval" "-target-feature" "+svpbmt"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svbare" "-target-feature"
"+svinval" "-target-feature" "+svnapot"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svpbmt"
// MCPU-SPACEMIT-X60-SAME: "-target-abi" "lp64d"
// We cannot check much for -mcpu=native, but it should be replaced by a valid
CPU string.
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index f8896d0d2c93a..c917de1f00eb1 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -386,6 +386,7 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
NoSchedModel,
!listconcat(RVA22S64Features,
[FeatureStdExtV,
+ FeatureStdExtSvnapot,
FeatureStdExtZbc,
FeatureStdExtZbkc,
FeatureStdExtZfh,
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
