[RFC: drm server] limitations of MiG for ioctls

Hi, I am currently attempting to implement a drm server to provide a way to use libdrm with multiboot framebuffer exposed by new device(mbinfo). I am running into a problem that I am unable to implement a compatible ioctl api because of the layout of the structures. I would prefer to reuse the s

Re: [RFC: drm server] limitations of MiG for ioctls

Hi, On 11/5/24 6:16 PM, Yuqian Yang wrote: > In conclusion, there is no way to do things like using a pointer to pass > data pointed by it in Mach. I can understand this is rooted in Mach > design. This does create problems of mimicking API in Linux to reuse a > lot of high-level things. At least

Re: T60 poweroff command hang at halting Hurd...

Please read the mailing list. I just fixed this bug and it was merged. Thanks, Damien Sent from Proton Mail mobile Original Message On 11 Nov 2024, 1:13 pm, Zhaoming Luo < zhming...@163.com> wrote: On 11/10/24 11:29 PM, jbra...@dismail.de wrote: > November 9, 2024 at 10:10 PM,

[PATCH 1/2 hurd] acpi, libmachdev: Add _forever variant of trivfs server loop

The acpi server needs to survive after the shutdown notification, so it can serve S_acpi_sleep() RPC to actually shut down the machine. Therefore we need to keep the server alive and not respond to the trivfs goaway request. --- acpi/main.c| 4 ++-- libmachdev/machdev.h | 1

[PATCH 2/2 hurd] shutdown: Try mach device acpi before /servers/acpi

Since libmachdev cannot currently serve netfs as well as trivfs on a path, we need to allow connecting to the bootstrapped acpi server to shut down the machine. --- shutdown/shutdown.c | 22 +- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/shutdown/shutdown.c b

[PATCH 0/2 hurd] Fix shutdown mechanism via ACPI

Hi, This addresses the bug that shutdown does not work correctly since ACPI server was introduced: Firstly, the acpi server needs to not exit when notified of shutdown, so that it can serve the S_acpi_sleep() RPC to halt the machine. Second, a workaround for netfs not running on libmachdev path;

[PATCH gnumach] device/intr: Account for interrupts that could not be delivered

When an irq handler dies, we are decrementing the n_unacked count and calling __enable_irq() the right number of times, but we need to decrement the total interrupt count by the number that were lost and also clear that number. This fixes a hang when a shared irq handler quits and leaves some unac

[PATCH hurd] acpi: Link with irqhelp

--- acpi/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/acpi/Makefile b/acpi/Makefile index ceccb351e..6e91e980f 100644 --- a/acpi/Makefile +++ b/acpi/Makefile @@ -27,7 +27,7 @@ SRCS = main.c netfs_impl.c acpi.c \ MIGSRCS= OBJS = $(patsub

[PATCH hurd] sutils: Add smp tool for running a process on slave processors

Until we make gnumach fully parallel, we need a way to execute on slave processor set on smp-enabled gnumach. For example: $ /sbin/smp /bin/bash $ will launch a shell that executes commands only within slave pset, consisting of all processors except processor 0. We can thus test

[PATCH v2 hurd] sutils: Add smp tool to run process on slave processors

Until we make gnumach fully parallel, we need a way to execute on slave processor set on smp-enabled gnumach. For example: $ /sbin/smp /bin/bash $ will launch a shell that executes commands only within slave pset, consisting of all processors except processor 0. We can thus test

[PATCH gnumach] fpu: Fix for cpus that have no fxsave instruction

Fallthrough was incorrectly using fxsave() instead of xsave() or xsaveopt(). TESTED: on AMD fam15h: no longer throws "No coprocessor" exception. --- i386/i386/fpu.c | 4 1 file changed, 4 insertions(+) diff --git a/i386/i386/fpu.c b/i386/i386/fpu.c index 3d146f71..203de993 100644 --- a/i386

[PATCH 6/6 gnumach] i386/apic: Fix condition on non-BSP

The condition was intended for non-BSP processors to disable timer, but apic_id != 0 means it could affect BSP if its apic id is non-zero. Fixes this bug. --- i386/i386/apic.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/i386/i386/apic.c b/i386/i386/apic.c index 41b335

[PATCH 2/6 gnumach] i386/cpuboot: Dont use CPU_NUMBER_NO_STACK() early

Since we just set up the gs segment, we can use CPU_NUMBER instead of CPU_NUMBER_NO_STACK. --- i386/i386/cpuboot.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/i386/i386/cpuboot.S b/i386/i386/cpuboot.S index 9ac86845..09855864 100644 --- a/i386/i386/cpuboot.S +++ b/i386/i386

[PATCH 5/6 gnumach] smp: Use logical destination not physical apic id

Since modern x86 cpus only support 4 bits of destination field in ICR, we could only address up to 16 processors, assuming their physical APIC ID was < 0x10. Some processors eg AMD fam15h have physical apic ids starting at 0x10 but only support 4 bits. So these lapics are unaddressable using physi

[PATCH 4/6 gnumach] pmap: Separate temporary_mapping from set_page_dir

Prepare for smp parallel init where we want to call these two functions on different cpus at different times. --- i386/i386/mp_desc.c | 1 + i386/i386at/model_dep.c | 1 + i386/intel/pmap.c | 2 -- 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/i386/i386/mp_desc.c b/i386

[PATCH 1/6 gnumach] i386/cpuboot: Simplify for legibility

The current segmentation already adds -KERNELBASE. But only when accessing the memory. Don't forget to reload gdt. --- i386/i386/cpuboot.S | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/i386/i386/cpuboot.S b/i386/i386/cpuboot.S index 7e6c4770..9ac86845 100644 --- a

[PATCH 3/6 gnumach] i386/cpuboot: Write gs selector correctly

To make selectors work reliably, we need to write zero to it before writing its final value. --- i386/i386/cpuboot.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/i386/i386/cpuboot.S b/i386/i386/cpuboot.S index 09855864..f549a2bc 100644 --- a/i386/i386/cpuboot.S +++ b/i386/i386/cpuboot.S @

[PATCH 0/6 gnumach] Preparation for parallel SMP init

Hi, This patchset consists of 6 patches that have been tested **not** to break both smp and non-smp systems, but get us closer to having smp working fully. The rationale for going with parallel init for smp is that APICs are not individually addressible for more than 8 cpus (in logical mode) or

[PATCH v2 1/1 libacpica] acpi_init: Get pci root port handle \_SB.PCI0 directly

This mostly fixes the numbering of IRQs when requested. This now works on an old AMD board with broken _CRS. It requests the possible irqs from _PRS and generates a valid _SRS request to set the one from the end of the list. v2: It also no longer errors on a valid _CRS. --- debian/patches/acpi-i

[PATCH 2/2 libacpica] acpi_init: Get pci root port handle \_SB.PCI0 directly

This mostly fixes the numbering of IRQs when requested. This now works on an old AMD board with broken _CRS. It requests the possible irqs from _PRS and generates a valid _SRS request to set the one from the end of the list. Note that acpi translator can only be used with gnumach that has been com

[PATCH 0/2 libacpica] Mostly fix acpi_get_irq_number()

This allows rumpdisk to probe correctly on machines with broken LNKx._CRS methods by selecting a valid irq from _PRS possible resources and calling the _SRS method to set the irq. Somehow this fix is not working on some intel machines, but makes rump_init() get further than before during probe.

[PATCH 1/2 libacpica] acpi_init: Match resources on function 0xffff

This ensures the resources are correct when matching. Resources are always all ones in the function field as they apply to all functions of a device. --- debian/patches/acpi-init-files.diff | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/debian/patches/acpi-init-files

Re: [PATCH hurd] rumpdisk: Try to reduce memory usage

On 12/29/24 8:56 AM, Samuel Thibault wrote: > Damien Zammit via Bug reports for the GNU Hurd, le sam. 28 déc. 2024 06:39:04 > +, a ecrit: >> + setenv ("RUMP_MEMLIMIT", "16m", 1); > Did you test this a lot? > > We'd probably want to disable rump-

[PATCH v2 hurd] acpi: Better error handling on S_acpi_get_pci_irq

Return positive error code when return value indicates error. --- acpi/acpi-ops.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/acpi/acpi-ops.c b/acpi/acpi-ops.c index 47f7e3d2..16d96e71 100644 --- a/acpi/acpi-ops.c +++ b/acpi/acpi-ops.c @@ -84,7 +84,7 @@ S_acpi_get_pci_irq

[PATCH v2 hurd] pci-arbiter: Fix long standing bug with PCI access

Proxied memory was not rounded up to page size, causing error with vm_map'ing the underlying memory. WARNING: Assumes pci memory resources are at least page aligned. If not, this will expose part of next resource to userspace. --- pci-arbiter/netfs_impl.c | 8 +++- 1 file changed, 7 inserti

[PATCH gnumach] i386/irq: Add missing enumeration for high interrupts

Because we support up to 64 irqs with 2 IOAPICs. --- i386/i386/irq.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/i386/i386/irq.c b/i386/i386/irq.c index 3c2f1748..91318f67 100644 --- a/i386/i386/irq.c +++ b/i386/i386/irq.c @@ -65,7 +65,9 @@ __enable_irq (irq_t irq_nr)

[PATCH hurd] acpi: Better error handling on S_acpi_get_pci_irq

This internal function acpi_get_irq_number() returns negative for error, otherwise returns valid IRQ. --- acpi/acpi-ops.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/acpi/acpi-ops.c b/acpi/acpi-ops.c index 1aaec10c..16d96e71 100644 --- a/acpi/acpi-ops.c +++ b/acpi

[PATCH hurd] rumpdisk: Try to reduce memory usage

--- rumpdisk/main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/rumpdisk/main.c b/rumpdisk/main.c index ca166274..ca9deea1 100644 --- a/rumpdisk/main.c +++ b/rumpdisk/main.c @@ -123,6 +123,8 @@ main (int argc, char **argv) setenv ("RUMP_NCPU", "1", 1); setenv ("RUMP_VERBOSE", "1"

[PATCH hurd] rumpdisk: Deallocate buffers in write during failure paths

--- rumpdisk/block-rump.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/rumpdisk/block-rump.c b/rumpdisk/block-rump.c index cd7af494..8a3a404a 100644 --- a/rumpdisk/block-rump.c +++ b/rumpdisk/block-rump.c @@ -373,6 +373,7 @@ rumpdisk_device_write (void *d, mach_port_t reply_port,

[PATCH hurd] pci-arbiter: Fix long standing bug with PCI access

Proxied memory was not rounded up to page size, causing error with vm_map'ing the underlying memory. WARNING: Could be security risk if assumption is incorrect: Assumes start of all pci memory resources are at least page aligned. --- pci-arbiter/netfs_impl.c | 11 ++- 1 file changed, 10

Re: Upgrade rumpkernel package to rump 10.99.12

droid Original Message On 4/2/25 11:01 am, Almudena Garcia wrote: > This is awesome!! How can I test rumpusbdisk? > > El lun, 3 feb 2025 a las 21:32, Samuel Thibault () > escribió: > >> Hello, >> >> Damien Zammit via Bug reports for the GNU Hurd, le

[PATCH 1/5 gnumach] i386/apic: Fix logical id numbering

The number is actually a mask bit per cpu. --- i386/i386/apic.c | 2 +- i386/i386/apic.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/i386/i386/apic.c b/i386/i386/apic.c index 7ec8c49b..e0941c6a 100644 --- a/i386/i386/apic.c +++ b/i386/i386/apic.c @@ -337,7 +337,7 @@ lapi

[PATCH 2/5 gnumach] smp: Remove early GS access

Since the gdt for apboot is located at a shared location in memory, we cannot patch the gdt values per cpu during parallel smp init, or havoc entails. --- i386/i386/cpuboot.S | 75 + i386/i386/mp_desc.c | 6 ++-- 2 files changed, 11 insertions(+), 70 de

[PATCH 0/5 gnumach] smp: Parallel SMP init

Hi, I figured out what was broken in my previous attempt at this: The APs were calling splhigh() in the debug printing code, which caused an unnecessary GS segment access. This should now support all x86 cpus with any core counts. Every 8 processors are grouped into the same IPI group, so on oc

[PATCH 5/5 gnumach] smp: Parallel SMP init

Now that things are in place, we switch to parallel init. The key to this change is that the INIT/STARTUP sequence is done in one step, and all cpus wake up at the same time. Synchronisation is done to complete each cpu setup individually. --- i386/i386/mp_desc.c | 51 +++--

[PATCH 3/5 gnumach] smp: Delay setting spl_init flag until after smp bringup

If this is not done, the spl code is called by kmsg_putchar on APs during printing of bringup debug, causing the only unnecessary early access of GS. --- i386/i386/mp_desc.c | 3 ++- i386/i386at/model_dep.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/i386/i386/mp_de

[PATCH 4/5 gnumach] smp: Make sure BSP is cpu 0 when starting other cpus

This is basically a no-op but ensures we are doing smp bringup correctly. --- i386/i386/mp_desc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/i386/i386/mp_desc.c b/i386/i386/mp_desc.c index 7595eb1e..295fccc7 100644 --- a/i386/i386/mp_desc.c +++ b/i386/i386/mp_desc.c @@

[PATCH v2 2/2 gnumach] smp: Parallel SMP init

Now that things are in place, we switch to parallel init. The key to this change is that the INIT/STARTUP sequence is done in one step, and all cpus wake up at the same time. Synchronisation is done to complete each cpu setup individually. --- i386/i386/mp_desc.c | 51 +++--

[PATCH v2 1/2 gnumach] cpuboot: Fix percpu apboot_gdt for early gs

This allocates a constant space for percpu gdts and copies the first entry to the nth entry on each cpu, then patches its own copy of the gdt so it can function independently. --- i386/i386/cpuboot.S | 63 ++--- 1 file changed, 53 insertions(+), 10 deletions

[PATCH v2 0/2 gnumach] Parallel SMP init with early gs access

Hi, These two patches complete smp parallel init by preserving early gs access, and makes the cpus all wake concurrently. Care has been taken so memory is not trampled on by other cpus during startup. Thanks, Damien

[PATCH gnumach] acpi_parse_apic: Check CAPABLE bit field on lapic MADT flag

Previously, we were ignoring cpus that were not enabled but online-capable. --- i386/i386at/acpi_parse_apic.c | 2 +- i386/i386at/acpi_parse_apic.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/i386/i386at/acpi_parse_apic.c b/i386/i386at/acpi_parse_apic.c index 24470426..ae

Re: [PATCH v2 2/2 gnumach] smp: Parallel SMP init

h not matching the width of the APIC id.  Does anyone know how this works? Thanks, Damien On 12/17/24 11:05 PM, Damien Zammit via Bug reports for the GNU Hurd wrote: > Now that things are in place, we switch to parallel init. > The key to this change is that the INIT/STARTUP sequence > is do

[PATCH v2 gnumach] fpu: Fix for cpus that have no fxsave instruction

Fallthrough was incorrectly using fxsave() instead of xsave() or xsaveopt(). TESTED: on AMD fam15h: no longer throws "No coprocessor" exception. --- i386/i386/fpu.c | 18 +- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/i386/i386/fpu.c b/i386/i386/fpu.c index 3d146

[PATCH gnumach] mp_desc: Add assert for AP having non-zero cpu number

Non-master processors cannot have cpu_number() == 0. The synchronisation fails hard if the cpu number is wrong. Alert the condition if this is the case. (On AMD fam15h, this assert currently fails, but I haven't been able to boot it with smp yet either). --- i386/i386/mp_desc.c | 3 +++ 1 file c

[PATCH v4 2/3 gnumach] smp: Use deassert for startup IPI not assert

Fixes ESR==0x8 error on AMD fam15h. Fixed timings. Cannot locate documentation on correct mode for STARTUP IPI, but this patch works on AMD hw and qemu. --- i386/i386/smp.c | 62 +++-- 1 file changed, 40 insertions(+), 22 deletions(-) diff --git a/i386

[PATCH v4 1/3 gnumach] smp: Parallel SMP init

Now that things are in place, we switch to parallel init. The key to this change is that the INIT/STARTUP sequence is done in one step, and all cpus wake up at the same time. Synchronisation is done via waiting for individual flags stored in separate memory locations. --- i386/i386/apic.h| 4

[PATCH v4 3/3 gnumach] apic: Add extended feature registers for local apic unit

Add workaround for broken systems that advertise 8 bit APIC ids but only match IPIs on 4 bits of the APIC id. --- i386/i386/apic.c | 28 +++- i386/i386/apic.h | 15 ++- i386/i386/cpu_number.h| 3 +++ i386/i386/cpuboot.S

[PATCH v4 0/3 gnumach] SMP on AMD and qemu

Hi, I addressed the comments in v3. This is v4. I was unable to locate documentation for correct STARTUP IPI mode, but I tested this series on both AMD fam15h and qemu and it boots. Damien

[PATCH hurd] rumpusbdisk: Link completely to scsipi library

The usb stack also uses SCSI emulation for usb mass storage. --- rumpdisk/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rumpdisk/Makefile b/rumpdisk/Makefile index e7f53511..cbe93845 100644 --- a/rumpdisk/Makefile +++ b/rumpdisk/Makefile @@ -17,7 +17,7 @@ RUMPLIB

Upgrade rumpkernel package to rump 10.99.12

Hi, I would like to suggest the following upgrade of rump to be on par with my "develop" branch[1]. The patches would need to be fetched from my branch directly because there is a very large changeset in the NetBSD upstream update commit. The main thing is upgrading rump from 9.99.x to 10.99.x

Re: [PATCH v3 1/4 gnumach] cpuboot: Fix percpu apboot_gdt for early gs

On 12/22/24 11:35 AM, Samuel Thibault wrote: > This is quite verbose. Could you check that the attached patch on top of > it still works? > > Samuel Your patch works and is much more readable. Thanks, Damien

[PATCH v3 3/4 gnumach] smp: Use deassert for startup IPI not assert

Fixes ESR==0x8 error on AMD fam15h. Fixed timings. --- i386/i386/smp.c | 62 +++-- 1 file changed, 40 insertions(+), 22 deletions(-) diff --git a/i386/i386/smp.c b/i386/i386/smp.c index befa0510..e3e4cc82 100644 --- a/i386/i386/smp.c +++ b/i386/i386/smp

[PATCH v3 4/4 gnumach] apic: Add extended feature registers for local apic unit

Add workaround for broken systems that advertise 8 bit APIC ids but only match IPIs on 4 bits of the APIC id. --- i386/i386/apic.c | 28 +++- i386/i386/apic.h | 15 ++- i386/i386/cpu_number.h| 3 +++ i386/i386/cpuboot.S

[PATCH v3 2/4 gnumach] smp: Parallel SMP init

Now that things are in place, we switch to parallel init. The key to this change is that the INIT/STARTUP sequence is done in one step, and all cpus wake up at the same time. Synchronisation is done to complete each cpu setup individually. --- i386/i386/mp_desc.c | 51 +++--

[PATCH v3 1/4 gnumach] cpuboot: Fix percpu apboot_gdt for early gs

This allocates a constant space for percpu gdts and copies the first entry to the nth entry on each cpu, then patches its own copy of the gdt so it can function independently. --- i386/i386/cpuboot.S | 63 ++--- 1 file changed, 53 insertions(+), 10 deletions

[PATCH v3 0/4 gnumach] SMP now works on AMD processor

Hi, The first two patches are exactly v2, but I have added two more that make SMP functional on my AMD fam15h processor. Thanks, Damien

Re: [RFC PATCH v3] Integrate HPET so the functions used for getting time can have a higher accuracy

You probably want to disable it entirely so it doesn't need to execute a branch condition every time it reads the timer, ie with #ifdef. This code path would be critical for timing. Damien Sent from Proton Mail Android Original Message On 23/3/25 9:13 pm, Zhaoming Luo wrote:

Re: Using rump function rump_sys_mount()

That's why I suggest use a simple main() and makefile. Then you link them explicitly. Rump is linked statically I believe. It is supposed to support dynamic linkage but I don't think I got it to work that way yet. Damien Sent from Proton Mail Android Original Message On 21

Re: The log of booting Thinkpad T60 with rumpdisk

"lspci -nn" shows the ids and names. Then you can search the PCI device id in the rump ahci source. Damien Sent from Proton Mail Android Original Message On 29/4/25 7:21 pm, Zhaoming Luo wrote: > On Tue, Apr 29, 2025 at 09:51:25AM +0200, Samuel Thibault wrote: > > > > Wh

Re: [RFC PATCH gnumach] kern: Integrate HPET so the functions used for getting time can have a higher accuracy

I think we are assuming any machine with ACPI has HPET. This is true since ~2005. Damien Sent from Proton Mail Android Original Message On 23/3/25 7:03 pm, Samuel Thibault wrote: > Zhaoming Luo, le dim. 23 mars 2025 13:29:47 +0800, a ecrit: > > On Sun, Mar 23, 2025 at 12:

Re: GNU HURD's Clean Code – Let's Bring More Developers

Hi, I don't speak for gnu but one thing that comes to mind is that there is less code in general in the operating system because it's a microkernel model, so even drivers for hardware are not part of the core and run in userspace. I am also guilty of not adding enough documentation for the featu

Re: [PATCH mach v4 1/1] Integrate HPET so the functions used for getting time can have a higher accuracy

I'm glad you got it working, Michael. (Maybe we need to update the docs to use -M q35 option?) How does it crash? Do you get a backtrace? What does it actually do during a crash? Can you try with a kdb enabled gnumach? Damien Sent from Proton Mail Android Original Message O

Re: [PATCH mach v4 1/1] Integrate HPET so the functions used for getting time can have a higher accuracy

You might need to run qemu with -smp 1 even though your gnumach is not SMP enabled, so that the acpi tables and apic works properly. I haven't tried UP with --enable-apic and no smp flag in qemu, I should try that to confirm. Damien Sent from Proton Mail Android Original Message ---

Re: [PATCH mach v4 1/1] Integrate HPET so the functions used for getting time can have a higher accuracy

Michael, I tried without -smp 1 flag and it still works here with UP (--enable-apic --disable-linux-groups). My qemu command looks like: qemu-system-i386 -M q35,accel=kvm -m 4096 -net user,hostfwd=tcp::-:22 -net nic -display curses -hda /dev/sdd Are you sure you are giving it enough memor