Hi,
I figured out what was broken in my previous attempt at this: The APs were calling splhigh() in the debug printing code, which caused an unnecessary GS segment access. This should now support all x86 cpus with any core counts. Every 8 processors are grouped into the same IPI group, so on occasion you will get more than the one processor interrupted than the one you wanted, but this is the only way to do it with APICs. Mysteriously, this still fails on AMD fam15h. I think the INIT/STARTUP sequence may need delay timings revised for actual hardware, but it all works in qemu just fine with no more hard smp boot hangs. Damien
