[PATCH v5 2/2 gnumach] percpu area using gs segment

This speeds up smp again, by storing the struct processor in a percpu area and avoiding an expensive cpu_number every call of current_processor(), as well as getting the cpu_number by an offset into the percpu area. Untested on 64 bit and work remains to use other percpu arrays. TESTED: (NCPUS=8)

[PATCH] percpu: active_stack with gs

--- i386/i386/cswitch.S | 12 ++-- i386/i386/i386asm.sym | 1 + i386/i386/locore.S| 2 +- i386/i386/percpu.h| 2 +- kern/startup.c| 2 +- kern/thread.c | 4 +--- kern/thread.h | 5 + x86_64/cswitch.S | 10 -- x86_64/locore.S |

[PATCH] x86_64: Change active_threads to use gs like i386

--- x86_64/cswitch.S | 2 +- x86_64/locore.S | 7 +++ 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/x86_64/cswitch.S b/x86_64/cswitch.S index 1f2e8e9d..29dae62c 100644 --- a/x86_64/cswitch.S +++ b/x86_64/cswitch.S @@ -85,7 +85,7 @@ ENTRY(Switch_context)

[PATCH gnumach] kdb: Add "show all runqs" debug command

--- ddb/db_command.c | 1 + ddb/db_print.c| 27 +++ ddb/db_print.h| 6 ++ kern/sched_prim.h | 1 + 4 files changed, 35 insertions(+) diff --git a/ddb/db_command.c b/ddb/db_command.c index d21386e6..2fae61b0 100644 --- a/ddb/db_command.c +++ b/ddb/db_command

[PATCH gnumach] kern/sched_prim: Simplify by not dispatching to idle cpu directly

This speeds up smp to approximately full speed of uniprocessor! Unfortunately, there is a general protection fault when booting. It seems to get a corrupt null stack pointer when returning with iret. --- kern/sched_prim.c | 82 ++- 1 file changed, 2 ins

[PATCH 0/4 gnumach] smp - getting closer

With this patchset, your chances of getting a shell with smp is about 1/3. Unfortunately, there is occasionally kernel traps when either booting, or using the system, depending if you reach a login shell or not. I was able to boot with -smp 3 and run "stress -c 3" for about 1 minute. Then I ran "

[PATCH 3/4 gnumach] Allow disabling of MACH_PCSAMPLE and disable by default

This fixes a page fault when the sampling occurs in MP. Perhaps it is not MP safe yet. --- configfrag.ac| 2 +- kern/pc_sample.c | 32 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/configfrag.ac b/configfrag.ac index 3c3ba3aa..290a1596 10064

[PATCH 4/4 gnumach] kern/sched_prim: Simplify by not dispatching to idle cpu directly

This speeds up smp to approximately full speed of uniprocessor! --- kern/sched_prim.c | 82 ++- 1 file changed, 2 insertions(+), 80 deletions(-) diff --git a/kern/sched_prim.c b/kern/sched_prim.c index 5ee0521a..cdb2ba27 100644 --- a/kern/sched_prim.c

[PATCH 2/4 gnumach] ioapic: Add simple locking for non-atomic accesses

--- i386/i386at/ioapic.c | 9 + 1 file changed, 9 insertions(+) diff --git a/i386/i386at/ioapic.c b/i386/i386at/ioapic.c index 57d18789..dcc91eff 100644 --- a/i386/i386at/ioapic.c +++ b/i386/i386at/ioapic.c @@ -32,6 +32,7 @@ #include #include #include +#include static int has_ir

[PATCH 1/4 gnumach] ioapic: Detect version of IOAPIC for correct EOI handling

--- i386/i386at/ioapic.c | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/i386/i386at/ioapic.c b/i386/i386at/ioapic.c index 218f9a51..57d18789 100644 --- a/i386/i386at/ioapic.c +++ b/i386/i386at/ioapic.c @@ -33,7 +33,7 @@ #include #include -static int has_i

[PATCH gnumach] kd: Handle masking of keyboard interrupt in the driver

--- i386/i386at/kd.h| 1 + i386/i386at/kd_event.c | 7 +++ i386/i386at/model_dep.c | 2 -- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/i386/i386at/kd.h b/i386/i386at/kd.h index 3ee707b5..5bfabce2 100644 --- a/i386/i386at/kd.h +++ b/i386/i386at/kd.h @@ -546,6 +546,7

[PATCH gnumach] com/lpr: Handle masking of interrupts in the driver

--- i386/i386at/autoconf.c | 6 ++ i386/i386at/model_dep.c | 8 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/i386/i386at/autoconf.c b/i386/i386at/autoconf.c index ef813d92..5c69988f 100644 --- a/i386/i386at/autoconf.c +++ b/i386/i386at/autoconf.c @@ -29,6 +29,11 @@

[PATCH gnumach] interrupt: Mask, eoi, unmask

--- i386/i386at/interrupt.S | 19 --- x86_64/interrupt.S | 19 +++ 2 files changed, 31 insertions(+), 7 deletions(-) diff --git a/i386/i386at/interrupt.S b/i386/i386at/interrupt.S index 8ae6b97c..ec2fc656 100644 --- a/i386/i386at/interrupt.S +++ b/i386/i386at/

Re: [PATCH gnumach] interrupt: Mask, eoi, unmask

Hi, On 1/10/23 20:13, Samuel Thibault wrote: > Sometimes the "why" of a commit is obvious, so it doesn't need to be > explained, but here it's really not and thus it definitely needs to > be. We have had various pings-pongs in the past about whether to EOI > before/after the interrupt, masking or

Re: [PATCH gnumach] interrupt: Mask, eoi, unmask

On 2/10/23 10:56, Samuel Thibault wrote: > So in the end, I'd tend to think that it's up to queue_intr to do the > unmasking, like it does now, while spl is still high and thus we don't > risk nesting. That way it's the in-kernel intr handler that knows > whether to mask/unmask or not. I.e. it'd be

[PATCH gnumach] Fix interrupt handling

Logic for interrupts: - interrupt.S raises spl (thus IF cleared) - interrupt.S EOI - interrupt.S calls the handler - for pure in-kernel handlers, they do whatever they want with IF cleared. - when a userland handler is registers, queue_intr masks the irq. - interrupt.S lowers spl with s

Re: Initial POWER9 port of GNU Mach

Hi, On 17/10/23 3:10 am, Tobias Alexandra Platen wrote: > On Mon, 2023-10-16 at 02:39 +0000, Damien Zammit wrote: >> I dont think that is correct. I often use -kernel flag with qemu to >> boot gnumach on i386. >> I think it supports multiboot so you may need to add some st

Re: 64bit startup

Please check the locore.S on 64 bit. I think the int stack checks may not be pointing to the right location. I remember making some changes a long time ago without updating 64 bit because i had no way to test. Damien Sent from ProtonMail mobile Original Message On 27 Oct 2023

[PATCH gnumach] x86_64/locore.S: Fix int stack checks when NCPUS > 1

--- x86_64/locore.S | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/x86_64/locore.S b/x86_64/locore.S index f0d1298d..2db0d49b 100644 --- a/x86_64/locore.S +++ b/x86_64/locore.S @@ -692,13 +692,14 @@ _kret_iret: trap_from_kernel: #ifMACH_KDB || MACH_TTD

[PATCH gnumach] console: Fix baud rate on com ports, use 115200 default baud, 8 data bits

TESTED: By booting gnumach off an HP T620 with console=com0 and receiving 115200 8N1 console on another machine connected via the serial port in minicom. Without this patch, part of the console is garbled by mismatching com params (9600 7N1). --- i386/i386at/com.c | 27 +++--

Progress on AMD x86 with gnumach

Hi, I am trying to port gnumach to HP T620 which is an AMD FAM16h board running my port of coreboot. With --disable-apic --enable-cpus=1 the board boots to a shell (but NIC locks up). Under GNU/Linux, using command line options "noapic nolapic", the same thing happens and the NIC locks up eve

[PATCH 0/2 gnumach] ACPI v2.0 support

This enables gnumach to additionally parse the XSDT table if the version of ACPI is detected to be greater than 1. TESTED: Should not break existing ACPI v1.0 support. Almost boots on HP T620 but crashes further downstream of ACPI table detection (to be fixed in follow up patches).

[PATCH 1/2 gnumach] ioapic: Remove IMCR toggle

Since we are not using legacy MP tables but intending to use ACPI to configure interrupt routing, we can assume all boards have virtual wire mode, thus do not require setting of IMCR register. (This may fix crashes on machines that do not have IMCR registers). --- i386/i386at/ioapic.c | 6 --

[PATCH 2/2 gnumach] ACPI: Support XSDT (ACPI >= v2.0)

--- i386/i386at/acpi_parse_apic.c | 203 -- i386/i386at/acpi_parse_apic.h | 18 ++- i386/i386at/model_dep.c | 8 +- 3 files changed, 169 insertions(+), 60 deletions(-) diff --git a/i386/i386at/acpi_parse_apic.c b/i386/i386at/acpi_parse_apic.c index 9cd861e

Re: [PATCH 0/2 gnumach] ACPI v2.0 support

Hi, On 1/25/24 3:41 AM, Almudena Garcia wrote: > Maybe the next crash is in APIC step. Check if it's using xAPIC or x2APIC, > and force xAPIC if necessary I checked it is definitely using xAPIC mode, I also patched it to set the right MSR bit. But the cpu still crashes when interrupts are enab

[PATCH gnumach] apic: Set up LAPICs in xAPIC mode

Clear flag in msr for xAPIC mode. --- i386/i386/apic.h | 3 ++- i386/i386/cpuboot.S | 3 ++- i386/i386at/boothdr.S | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/i386/i386/apic.h b/i386/i386/apic.h index e870dcf8..9f908159 100644 --- a/i386/i386/apic.h +++ b/i386/i

[PATCH] Support up to two IOAPICs with up to 32 GSIs on each

Previously, only IOAPIC[0] was supported. Now this supports up to two IOAPICs. --- i386/i386/apic.c | 13 + i386/i386/apic.h | 6 ++- i386/i386/locore.S| 43 + i386/i386at/acpi_parse_apic.c | 3 ++ i386/i386at/int_init.c| 6 ++-

[PATCH gnumach] smp: Remove hardcoded AP_BOOT_ADDR

This took some time to figure out. Involves hand-crafted 16 bit assembly instructions [1] because GNU AS does not fully understand real-mode x86. [1] Intel Architecture Software Developer's Manual, Volume 2: Instruction Set Reference Manual --- i386/i386/cpuboot.S | 32 ++

Re: [PATCH gnumach] smp: Remove hardcoded AP_BOOT_ADDR

Hi Samuel, On 1/29/24 9:20 PM, Samuel Thibault wrote: > Damien Zammit, le lun. 29 janv. 2024 10:07:30 +, a ecrit: >> -ljmp$BOOT_CS, $M(0f) >> +xorl%eax, %eax >> +mov %cs, %ax >> +shll$4, %eax >> +addl$M(0f), %eax >

[PATCH v2 gnumach] apic: Set up LAPICs in xAPIC mode

Clear flag in msr for xAPIC mode. --- i386/i386/apic.h | 3 ++- i386/i386/cpuboot.S | 4 ++-- i386/i386at/boothdr.S | 3 ++- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/i386/i386/apic.h b/i386/i386/apic.h index b8fff2af..e410e9c6 100644 --- a/i386/i386/apic.h +++ b/i386/

[PATCH v2 gnumach] ACPI: Support XSDT (ACPI >= v2.0)

This enables gnumach to additionally parse the XSDT table if the revision of ACPI is 2. NB: I removed a few checksum checks in acpi tables where there is no checksum present in the table. TESTED: Still works on qemu (ACPI v1.0) TESTED: Works on a x86 board with XSDT (ACPI v2.0) --- i386/i386at/

[PATCH v2 gnumach] smp: Remove hardcoded AP_BOOT_ADDR

This took some time to figure out. Involves a hand-crafted 16 bit assembly instruction [1] because it requires an immediate for the memory address of far jump. This required self-modifying code to inject the next instruction, therefore I added a near jump to clear the instruction cache queue in ca

[PATCH v3 gnumach] ACPI: Support XSDT (ACPI >= v2.0)

This enables gnumach to additionally parse the XSDT table if the revision of ACPI is 2. TESTED: Still works on qemu (ACPI v1.0) TESTED: Works on a x86 board with XSDT (ACPI v2.0) --- i386/i386at/acpi_parse_apic.c | 258 ++ i386/i386at/acpi_parse_apic.h | 18 ++- i

[PATCH gnumach] model_dep: Fix serial console with APIC enabled

Move cninit() further down so that IOAPIC has a chance to initialize before the com port interrupt is unmasked in the IOAPIC, fixing a fault and reboot. --- i386/i386at/model_dep.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/i386/i386at/model_dep.c b/i386/i386at/

[PATCH 1/2 gnumach] Add HPET timer for small accurate delays

Enables a 32 bit periodic HPET timer without generating interrupts. The purpose of this is to provide a convenient udelay/mdelay in mach since the pit one-shot mode is unreliable. TESTED: This works in qemu correctly TESTED: This works on an AMD board with ACPI v2.0 correctly --- i386/i386/apic.c

[PATCH 2/2 gnumach] smp: Use HPET instead of unreliable pit one-shot

--- i386/i386/smp.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/i386/i386/smp.c b/i386/i386/smp.c index fb43ecb6..87f59913 100644 --- a/i386/i386/smp.c +++ b/i386/i386/smp.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include

[PATCH 1/6 gnumach] Fix apic_send_ipi function clobbering read only fields

This was the root cause of failing to INIT. We were clobbering remote_read_status. And also, we need to reference the .r register when writing the ICR regs otherwise I think it writes all of the block. --- i386/i386/apic.c | 8 ++-- i386/i386/apic.h | 2 +- 2 files changed, 7 insertions(+), 3

[PATCH 0/6 gnumach] SMP on AMD hardware

Hi all, This patchset fixes a number of things wrong with smp and most of all fixes the root cause of an AP startup problem (Patch 1), which may also be affecting IPIs in general. In qemu with smp, I get a new panic after all modules are loaded: ../kern/slab.c:966: kmem_cache_alloc_from_slab: \

[PATCH 4/6 gnumach] Add HPET timer for small accurate delays

TESTED: This works in qemu correctly TESTED: This works on an AMD board with ACPI v2.0 correctly --- i386/i386/apic.c | 87 +++ i386/i386/apic.h | 4 ++ i386/i386at/acpi_parse_apic.c | 35 ++ i386/i386at/acpi_parse_apic.h | 23

[PATCH 6/6 gnumach] smp: Fix INIT/STARTUP IPI sequence

Outstanding: Find a way to allocate memory below 1MiB. Otherwise, this hardcodes 0x3000 as the starting eip. TESTED: works in qemu TESTED: works hardware with AMD cpu --- i386/i386/mp_desc.c | 15 -- i386/i386/smp.c | 114 +--- i386/i386/smp.h

[PATCH 3/6 gnumach] smp: Remove hardcoded AP_BOOT_ADDR

This took some time to figure out. Involves a hand-crafted 16 bit assembly instruction [1] because it requires an immediate for the memory address of far jump. This required self-modifying code to inject the next instruction, therefore I added a near jump to clear the instruction cache queue in ca

[PATCH 2/6 gnumach] separate lapic_enable from lapic_setup

This allows us to init the lapic without necessarily turning on the IOAPIC interrupts. --- i386/i386/apic.c | 15 +-- i386/i386/apic.h | 2 ++ i386/i386/mp_desc.c | 6 +++--- i386/i386at/ioapic.c | 1 + 4 files changed, 19 insertions(+), 5 deletions(-) diff --git a/i386/i3

[PATCH 5/6 gnumach] smp: Use HPET instead of pit one-shot that is unreliable

NB: Every x86 board that uses ACPI most likely has a HPET. We can roll back to PIT in the cases where its not present, but the PIT one shot code is definitely currently broken. --- i386/i386/smp.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/i386/i386/smp.c b/i386/i38

[PATCH v2 2/4 gnumach] Add HPET timer for small accurate delays

TESTED: This works in qemu correctly TESTED: This works on an AMD board with ACPI v2.0 correctly --- i386/i386/apic.c | 97 +++ i386/i386/apic.h | 5 ++ i386/i386at/acpi_parse_apic.c | 35 ++--- i386/i386at/acpi_parse_apic.h | 23 +

[PATCH v2 3/4 gnumach] smp: Use HPET instead of pit one-shot that is unreliable

NB: Assume every x86 board that uses ACPI has a HPET. We can roll back to PIT in the cases where its not present, but the PIT one shot code is currently broken. --- i386/i386/smp.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/i386/i386/smp.c b/i386/i386/smp.c index fb

[PATCH v2 1/4 gnumach] separate lapic_enable from lapic_setup

This allows us to init the lapic without necessarily turning on the IOAPIC interrupts. --- i386/i386/apic.c | 15 +-- i386/i386/apic.h | 2 ++ i386/i386/mp_desc.c | 12 +--- i386/i386at/ioapic.c | 1 + 4 files changed, 25 insertions(+), 5 deletions(-) diff --git a/i

[PATCH v2 0/4 gnumach] SMP on AMD

Hi, Here are the changes from previous review. I did not make changes to ensure pit fallback because the pit one-shot code is broken; there is no point making it fall back to a delay that does not work. I tried fixing the pit code, but it resulted in strange behaviour. We can assume every x86

[PATCH v2 4/4 gnumach] smp: Fix INIT/STARTUP IPI sequence

To be fixed: Find a way to allocate memory below 1MiB. Otherwise, this hardcodes 0x3000 as the starting eip. TESTED: works in qemu TESTED: works hardware with AMD cpu --- i386/i386/mp_desc.c | 15 +++-- i386/i386/smp.c | 126 +--- i386/i386/smp.h

[PATCH v3 0/4 gnumach] SMP on AMD

Hi, I addressed all the points in review 2. Here is version 3. It still boots! Thanks, Damien

[PATCH v3 1/4 gnumach] separate lapic_enable from lapic_setup

This initializes the lapic without turning on the IOAPIC interrupts during SMP init. --- i386/i386/apic.c | 15 +-- i386/i386/apic.h | 2 ++ i386/i386/mp_desc.c | 18 +++--- i386/i386at/ioapic.c | 1 + 4 files changed, 31 insertions(+), 5 deletions(-) diff --gi

[PATCH v3 3/4 gnumach] smp: Use HPET instead of pit one-shot that is unreliable

NB: Every x86 board that uses ACPI most likely has a HPET since 2005. We can roll back to PIT in the cases where its not present, but the PIT one shot code is definitely currently broken. --- i386/i386/smp.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/i386/i386/smp.c

[PATCH v3 2/4 gnumach] Add HPET timer for small accurate delays

TESTED: This works in qemu correctly TESTED: This works on an AMD board with ACPI v2.0 correctly --- i386/i386/apic.c | 89 +++ i386/i386/apic.h | 5 ++ i386/i386at/acpi_parse_apic.c | 35 ++ i386/i386at/acpi_parse_apic.h | 23

[PATCH v3 4/4 gnumach] smp: Fix INIT/STARTUP IPI sequence

TODO: Don't hardcode 0x3000 as the starting eip. TESTED: works in qemu TESTED: works hardware with AMD cpu --- i386/i386/mp_desc.c | 15 +++-- i386/i386/smp.c | 125 +--- i386/i386/smp.h | 5 +- i386/i386at/cram.h | 5 ++ i386/i386

Re: [PATCH v3 2/4 gnumach] Add HPET timer for small accurate delays

l Thibault wrote: > Applied, thanks! Could you check with your mailer how to prevent it from > using the quoted-printable encoding? git am often has troubles applying your > patches, and I have to fix the patch by hand, it's really unconvenient. > Samuel Damien Zammit, le mer. 0

Re: [PATCH v3 2/4 gnumach] Add HPET timer for small accurate delays

Hi, On 2/8/24 10:28 AM, Samuel Thibault wrote: > Could you check with your mailer how to prevent it from using the > quoted-printable encoding? git am often has troubles applying your > patches, and I have to fix the patch by hand, it's really inconvenient. For others' benefit, I think I fix

[PATCH gnumach] smp: Fix compile error with missing apboot_addr

--- i386/i386/model_dep.h | 5 + i386/i386/mp_desc.h | 5 - 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/i386/i386/model_dep.h b/i386/i386/model_dep.h index 095eec9b..5369e288 100644 --- a/i386/i386/model_dep.h +++ b/i386/i386/model_dep.h @@ -28,6 +28,11 @@ #include

[PATCH gnumach] smp: Rearrange IPI sending mechanism

Wait for ICR then just assert the signal. No de-assert. --- i386/i386/smp.c | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/i386/i386/smp.c b/i386/i386/smp.c index 05e9de67..a758eea3 100644 --- a/i386/i386/smp.c +++ b/i386/i386/smp.c @@ -54,17 +54,11 @@ static void smp

[PATCH gnumach] smp: Fix unable to enter kdb during boot

--- i386/i386at/kd.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/i386/i386at/kd.c b/i386/i386at/kd.c index 984d62e3..486dea67 100644 --- a/i386/i386at/kd.c +++ b/i386/i386at/kd.c @@ -458,6 +458,7 @@ kdopen( kdinit(); } tp->t_state |= TS_CARR_ON; + un

[PATCH gnumach] smp: Fix parenthesis around logic expression value

--- kern/thread.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kern/thread.c b/kern/thread.c index 38287581..de9d1982 100644 --- a/kern/thread.c +++ b/kern/thread.c @@ -1921,7 +1921,7 @@ Restart: * Reset policy and priorities if needed. */ #ifMACH

[PATCH gnumach] Enable MACH_HOST and fix non-addressable bitfields

--- configfrag.ac | 2 +- kern/task.h | 10 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/configfrag.ac b/configfrag.ac index f9285c9d..d059c7b9 100644 --- a/configfrag.ac +++ b/configfrag.ac @@ -71,7 +71,7 @@ AC_DEFINE([MACH_DEBUG], [1], [MACH_DEBUG]) AC_DEFINE([MA

[PATCH gnumach] smp: Create AP processor set and put all APs inside it

This has the effect of running with one cpu only with smp, but has the ability to enable APs in userspace with the right processor set RPCs. --- ddb/db_print.c | 4 +++- kern/machine.c | 7 ++- kern/processor.c | 30 +++--- kern/processor.h | 1 + 4 files changed

Re: [PATCH gnumach] Enable MACH_HOST and fix non-addressable bitfields

Hi, On 2/11/24 9:43 PM, Samuel Thibault wrote: > Damien Zammit, le dim. 11 févr. 2024 07:09:48 +, a ecrit: >> diff --git a/configfrag.ac b/configfrag.ac >> index f9285c9d..d059c7b9 100644 >> --- a/configfrag.ac >> +++ b/configfrag.ac >> @@ -71,7 +7

Re: [PATCH gnumach] Enable MACH_HOST and fix non-addressable bitfields

Hi, On 2/11/24 10:07 PM, Samuel Thibault wrote: > Damien Zammit, le dim. 11 févr. 2024 10:55:26 +, a ecrit: >>>> diff --git a/kern/task.h b/kern/task.h >>>> index dec3a530..27970620 100644 >>>> --- a/kern/task.h >>>> +++

[PATCH v2 gnumach] smp: Fix unable to enter kdb during boot

--- i386/i386at/kd.c | 1 + i386/i386at/kd_event.c | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/i386/i386at/kd.c b/i386/i386at/kd.c index 984d62e3..2bea3c8c 100644 --- a/i386/i386at/kd.c +++ b/i386/i386at/kd.c @@ -1127,6 +1127,7 @@ kdinit(void) k_comm |= K_CB

[PATCH v2 gnumach] smp: Rearrange IPI sending mechanism

Wait for ICR then just assert the signal. No need for deassert. This is how Linux and NetBSD does it. I couldn't find documentation on the correct method, however. --- i386/i386/smp.c | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/i386/i386/smp.c b/i386/i386/smp.c inde

[PATCH v2 gnumach] Enable MACH_HOST and fix non-addressable bitfields

This is only enabled when NCPUS > 1. Enables some older code paths that allows userspace to manage cpu resources via processor set RPCs. Size of struct task is preserved while making 4 bitfields addressable as 4 single byte fields. --- configfrag.ac | 8 ++-- kern/task.h | 10 +-

[PATCH v2 gnumach] smp: Create AP processor set and put all APs inside it

This has the effect of running with one cpu only with smp, but has the ability to enable APs in userspace with the right processor set RPCs. --- ddb/db_print.c | 10 +++--- kern/machine.c | 13 + kern/processor.c | 3 +++ kern/processor.h | 3 +++ 4 files changed, 26 insertio

[PATCH gnumach] smp: Set processor set to non-empty when adding a processor

This allows the slave_pset to be used for actual tasks with the processor_set RPCs. --- kern/processor.c | 1 + 1 file changed, 1 insertion(+) diff --git a/kern/processor.c b/kern/processor.c index f06b5d62..71bbb757 100644 --- a/kern/processor.c +++ b/kern/processor.c @@ -245,6 +245,7 @@ void ps

Test program for running task on slave_pset

Hi, This program requires master branch PLUS a one line patch I just mailed in for gnumach. Here is a simple test program to enable a new task to run on slave_pset processor set containing the rest of the processors in SMP kernel. You can compile it as a sutil in hurd/sutils: usage must be run

Re: [PATCH v2] Port GDB to Hurd x86_64.

Thank you Flavio, great job! This will be an essential part of the new system. Damien Sent from Proton Mail mobile Original Message On 16 Feb 2024, 12:18 pm, Samuel Thibault < samuel.thiba...@gnu.org> wrote: Seems now to work fine with libraries indeed, thanks! I have uploaded

[PATCH 3/3 gnumach] kern/gsync: Use vm_map_lookup with exit_map_locked as appropriate

This refactors gsync functions so that the read lock on vm map is only taken once and extended throughout appropriate calls. Co-Authored-By: Sergey Bugaev --- kern/gsync.c | 28 +++- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/kern/gsync.c b/kern/gsync

[PATCH 1/3 gnumach] vm_map: Fix deadlock in vm code

Authored-by: Sergey Bugaev --- vm/vm_map.c | 32 ++-- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/vm/vm_map.c b/vm/vm_map.c index f221c532..e4672260 100644 --- a/vm/vm_map.c +++ b/vm/vm_map.c @@ -1424,8 +1424,9 @@ vm_map_pageable_scan(struct vm_map

[PATCH 0/3 gnumach] vm_map and gsync changes

This patchset fixes two critical deadlocks when running with SMP: The first one is isolated to patch 1 (vm_map), the second is a combination of patch 2 and 3 (vm_map_lookup + gsync). When applied, these patches allow slave_pset to be entered and gnumach source code to be compiled on 7 cores witho

[PATCH 2/3 gnumach] vm_map_lookup: Add parameter for exiting with map locked

This adds a parameter called exit_map_locked to vm_map_lookup() that allows the function to return with the map locked. This is to prepare for fixing a bug with gsync where the map is locked twice by mistake. Co-Authored-By: Sergey Bugaev --- i386/intel/read_fault.c | 4 ++-- kern/gsync.c

[PATCH v2 0/3 gnumach] vm_map and gsync changes

Hi, I addressed the points in review of first round. I tested this patchset using Sergey's patch additionally but dropped it from this set so Sergey can mail in his version instead. It still compiles gnumach with 7 cores using slave_pset. Thanks, Damien

[PATCH v2 2/3 gnumach] vm_map_lookup: Add parameter for keeping map locked

This adds a parameter called keep_map_locked to vm_map_lookup() that allows the function to return with the map locked. This is to prepare for fixing a bug with gsync where the map is locked twice by mistake. Co-Authored-By: Sergey Bugaev --- i386/intel/read_fault.c | 4 ++-- kern/gsync.c

[PATCH v2 1/3 gnumach] vm_map: Add comment and assert for vm_map_delete

This will prevent calling vm_map_delete without the map locked unless ref_count is zero. --- vm/vm_map.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/vm/vm_map.c b/vm/vm_map.c index e454bb2a..f221c532 100644 --- a/vm/vm_map.c +++ b/vm/vm_map.c @@ -551,10 +551,12 @@ void vm_map_deallo

[PATCH v2 3/3 gnumach] kern/gsync: Use vm_map_lookup with keep_map_locked

This prevents a deadlock in smp where a read lock on the map is taken in gsync and then the map is locked again inside vm_map_lookup() but another thread had a pre-existing write lock, therefore the second read lock blocks. This is fixed by removing the initial gsync read lock on the map but keepi

[PATCH gnumach] kern/processor: Do not set default_pset.empty on bootstrap

This is not needed because cpu_up does this when it comes online, it calls pset_add_processor(). --- kern/processor.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/kern/processor.c b/kern/processor.c index 33733a59..0e42fa37 100644 --- a/kern/processor.c +++ b/kern/processor.c @@ -76,7 +76,

[PATCH gnumach] kern: Use _irq variant of lock and disable interrupts

During quantum adjustment, disable interrupts and call appropriate lock. --- kern/priority.c | 4 ++-- kern/processor.c | 2 +- kern/processor.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/kern/priority.c b/kern/priority.c index fe11d0d4..7f28b3d7 100644 --- a/kern/prio

[PATCH gnumach] kern: Use _nocheck variants of locks taken at splsched()

Fixes assertion errors when LDEBUG is compiled in. --- kern/machine.c| 6 -- kern/sched_prim.c | 38 -- 2 files changed, 28 insertions(+), 16 deletions(-) diff --git a/kern/machine.c b/kern/machine.c index f757d146..a350fad4 100644 --- a/kern/machine.c

[PATCH gnumach] pmap: Add assert_splsched calls to ensure at SPL7

--- i386/intel/pmap.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/i386/intel/pmap.c b/i386/intel/pmap.c index e43b06c1..cf075a43 100644 --- a/i386/intel/pmap.c +++ b/i386/intel/pmap.c @@ -3114,6 +3114,7 @@ void process_pmap_updates(pmap_t my_pmap) pmap_t pmap;

[PATCH v3 gnumach] smp: Rearrange IPI sending mechanism

Wait for ICR then just assert the signal. Linux and NetBSD does it this way, assume they know better. --- i386/i386/smp.c | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/i386/i386/smp.c b/i386/i386/smp.c index 05e9de67..a758eea3 100644 --- a/i386/i386/smp.c +++ b/i386/i3

[PATCH v2 gnumach] vm_map: Add comment and assert for vm_map_delete

This will prevent calling vm_map_delete without the map locked unless ref_count is zero. --- vm/vm_map.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/vm/vm_map.c b/vm/vm_map.c index c237afbe..7db76b7b 100644 --- a/vm/vm_map.c +++ b/vm/vm_map.c @@ -551,10 +551,12 @@ void vm_map_deallo

Re: [PATCH v3 gnumach] smp: Rearrange IPI sending mechanism

Hi Almu, On 2/24/24 12:24 AM, Almudena Garcia wrote: > I set the code as this way because it's the standard of Intel's guides. > > The guide explain that although most machines turn on the cpu with an unique > SIPI, some machines could require a second SIPI. Even some older machines > could nee

[PATCH v7 0/2 hurd] Add irqhelp and clean up ddekit

Hi, I figured out that a semaphore is needed in ddekit to wait until the thread_init(priv) is called. This was initially confusing because I thought a semaphore was needed in the irqhelp library, but it is not required there. TESTED: copying a large file from hurd to linux and ifup/ifdown a few

[PATCH v7 2/2 hurd] ddekit: Use libirqhelp for interrupt registration

Use the new irqhelp library in ddekit and clean up. --- libddekit/Makefile| 2 +- libddekit/interrupt.c | 208 ++ 2 files changed, 28 insertions(+), 182 deletions(-) diff --git a/libddekit/Makefile b/libddekit/Makefile index 88a0c8909..c74ec1128 1006

[PATCH v7 1/2 hurd] libirqhelp: Add library

Add a helper library for attaching interrupt handlers in userspace. --- Makefile | 1 + libirqhelp/Makefile | 28 libirqhelp/irqhelp.c | 362 +++ libirqhelp/irqhelp.h | 49 ++ 4 files changed, 440 insertions(+) create mode 100644

[PATCH 0/1 hurd] ext2fs - new translator entries in xattrs

Hi, I have prepared this patch for inclusion into hurd, however we may need to think of the best migration strategy: Do we allow a soft migration where translator entries are kept as is, but new ones are migrated only upon creation. Or do we write a script that will migrate all translator entrie

[PATCH 1/1 hurd] ext2fs: New default: use xattrs to store translator records

Replaces experimental option --x-xattr-translator-records with --no-xattr-translator-records to allow rolling back to previous behaviour. NB: - Legacy records still work with either setting. - Adding a new record removes a legacy one. --- ext2fs/ext2fs.c | 18 +- ext2fs/inode.

[PATCH v8 1/2 hurd] libirqhelp: Add library

Add a helper library for attaching interrupt handlers in userspace. --- Makefile | 1 + libirqhelp/Makefile | 28 libirqhelp/irqhelp.c | 359 +++ libirqhelp/irqhelp.h | 49 ++ 4 files changed, 437 insertions(+) create mode 100644

[PATCH v8 0/2 hurd] Add irqhelp and clean up ddekit

Hi, I think we need to allow the irq handler to be called one more time, because we don't know if there is a pending interrupt until we need to handle one. Once we enable the irq one more time, it is necessary to handle the last interrupt before quitting the handler. I tested this behaviour and

[PATCH v8 2/2 hurd] ddekit: Use libirqhelp for interrupt registration

Use the new irqhelp library in ddekit and clean up. --- libddekit/Makefile| 2 +- libddekit/interrupt.c | 208 ++ 2 files changed, 28 insertions(+), 182 deletions(-) diff --git a/libddekit/Makefile b/libddekit/Makefile index 88a0c8909..c74ec1128 1006

[PATCH v9 0/2 hurd] Add irqhelp and clean up ddekit

Hi, So having discussed this, we allow the irq thread to be called one more time, but not actually call the user irq handler if the shutdown flag is set. We acknowledge the interrupt has been handled, however. I tested this behaviour and it works on netdde.static to ifup and ifdown, and send a la

[PATCH v9 2/2 hurd] ddekit: Use libirqhelp for interrupt registration

Use the new irqhelp library in ddekit and clean up. --- libddekit/Makefile| 2 +- libddekit/interrupt.c | 208 ++ 2 files changed, 28 insertions(+), 182 deletions(-) diff --git a/libddekit/Makefile b/libddekit/Makefile index 88a0c8909..c74ec1128 1006

[PATCH v9 1/2 hurd] libirqhelp: Add library

Add a helper library for attaching interrupt handlers in userspace. --- Makefile | 1 + libirqhelp/Makefile | 28 libirqhelp/irqhelp.c | 360 +++ libirqhelp/irqhelp.h | 49 ++ 4 files changed, 438 insertions(+) create mode 100644

[PATCH web] faq: Add doc about recent SMP support and how to test

--- faq/smp.mdwn | 31 ++- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/faq/smp.mdwn b/faq/smp.mdwn index c0133b80..ee0bf53f 100644 --- a/faq/smp.mdwn +++ b/faq/smp.mdwn @@ -13,21 +13,34 @@ License|/fdl]]."]]"""]] [[!meta title="Does GNU/Hurd suppor

Re: [PATCH v9 0/2 hurd] Add irqhelp and clean up ddekit

Hi, On 3/10/24 6:46 AM, Samuel Thibault wrote: > Damien Zammit, le sam. 09 mars 2024 01:18:37 +, a ecrit: >> So having discussed this, we allow the irq thread to be called one more time, >> but not actually call the user irq handler if the shutdown flag is set. >&g

[PATCH v10 0/2 hurd] Add irqhelp library and clean up ddekit

Hi, This patchset adds a new library irqhelp for assisting the attachment of irq handlers in userspace. The previous problem was that return(NULL) was crashing netdde while pthread_exit(NULL) works for exiting the irq thread cleanly. The mach_msg_server thread now shuts down cleanly by setting

[PATCH v10 1/2 hurd] libirqhelp: Add library

Add a helper library for attaching interrupt handlers in userspace. --- Makefile | 1 + libirqhelp/Makefile | 28 libirqhelp/irqhelp.c | 359 +++ libirqhelp/irqhelp.h | 49 ++ 4 files changed, 437 insertions(+) create mode 100644

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