Clear flag in msr for xAPIC mode.
---
i386/i386/apic.h | 3 ++-
i386/i386/cpuboot.S | 3 ++-
i386/i386at/boothdr.S | 3 ++-
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/i386/i386/apic.h b/i386/i386/apic.h
index e870dcf8..9f908159 100644
--- a/i386/i386/apic.h
+++ b/i386/i386/apic.h
@@ -298,7 +298,8 @@ extern int cpu_id_lut[];
#define APIC_MSR 0x1b
#define APIC_MSR_BSP 0x100 /* Processor is a BSP */
-#define APIC_MSR_ENABLE 0x800
+#define APIC_MSR_X2APIC 0x400 /* LAPIC is in x2APIC mode */
+#define APIC_MSR_ENABLE 0x800 /* LAPIC is enabled */
/* Set or clear a bit in a 255-bit APIC mask register.
These registers are spread through eight 32-bit registers. */
diff --git a/i386/i386/cpuboot.S b/i386/i386/cpuboot.S
index c85c4ddb..6c3cfcb3 100644
--- a/i386/i386/cpuboot.S
+++ b/i386/i386/cpuboot.S
@@ -175,13 +175,14 @@ _apboot:
mov apboot_idt_ptr, %ebx
lidt (%ebx)
- /* Enable local apic */
+ /* Enable local apic in xAPIC mode */
xorl %eax, %eax
xorl %edx, %edx
movl $APIC_MSR, %ecx
rdmsr
orl $APIC_MSR_ENABLE, %eax
andl $(~APIC_MSR_BSP), %eax
+ andl $(~APIC_MSR_X2APIC), %eax
movl $APIC_MSR, %ecx
wrmsr
diff --git a/i386/i386at/boothdr.S b/i386/i386at/boothdr.S
index 6696d966..daaf57db 100644
--- a/i386/i386at/boothdr.S
+++ b/i386/i386at/boothdr.S
@@ -67,13 +67,14 @@ boot_entry:
movl $solid_intstack+INTSTACK_SIZE-4, %esp
andl $0xfffffff0,%esp
- /* Enable local apic */
+ /* Enable local apic in xAPIC mode */
xorl %eax, %eax
xorl %edx, %edx
movl $APIC_MSR, %ecx
rdmsr
orl $APIC_MSR_ENABLE, %eax
orl $APIC_MSR_BSP, %eax
+ andl $(~APIC_MSR_X2APIC), %eax
movl $APIC_MSR, %ecx
wrmsr
--
2.43.0
