https://sourceware.org/bugzilla/show_bug.cgi?id=25599
--- Comment #16 from dave.anglin at bell dot net ---
Thanks for adjusting the comment.
It seems the person that wrote the GNU ld code was aware of the ambiguity. I
suspect
there will be a need to implement the brl instruction in gcc for GNU L
https://sourceware.org/bugzilla/show_bug.cgi?id=25599
--- Comment #15 from Alan Modra ---
Thanks for delving into this, as you can see I've updated the comment and made
the testcase accept either slot 1 or 2 for PCREL60B.
Interestingly, GNU ld seems to accept either slot 1 or 2 for PCREL60B. At
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--- Comment #14 from cvs-commit at gcc dot gnu.org ---
The master branch has been updated by Alan Modra :
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=d71893802fe424e3123ced8c6ed158958487f716
commit d71893802fe424e3123ced8c6ed1
https://sourceware.org/bugzilla/show_bug.cgi?id=25599
--- Comment #13 from dave.anglin at bell dot net ---
On 2021-05-21 12:15 p.m., jvb at cyberscience dot com wrote:
> I will test movl, break.x and nop.x. They have operands of 64, 62 and 62 bits,
> with very different layout to brl, so PCREL60 w
https://sourceware.org/bugzilla/show_bug.cgi?id=25599
--- Comment #12 from dave.anglin at bell dot net ---
On 2021-05-21 12:15 p.m., jvb at cyberscience dot com wrote:
> Specifying a slot value for a 2 slot instruction + immediate is clearly
> ambiguous without further clarification. HP interprets
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--- Comment #11 from John Buddery ---
I will test movl, break.x and nop.x. They have operands of 64, 62 and 62 bits,
with very different layout to brl, so PCREL60 won't apply. One potential
candidate is PCREL64 against a movl, I'll see if I ca
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--- Comment #10 from dave.anglin at bell dot net ---
I think the test is wrong. The brl instruction is comprised of two
instruction slots (L+X). For brl, the
imm39 field and a 2-bit Ignored field occupy the L instruction slot. The
actual br
https://sourceware.org/bugzilla/show_bug.cgi?id=25599
--- Comment #9 from John Buddery ---
Thanks very much for the analysis - I agree, this is about slot numbers not
offsets and the comment is inaccurate.
I too found the HP behaviour odd, when considering the instruction as using
slots 1 and 2.
https://sourceware.org/bugzilla/show_bug.cgi?id=25599
--- Comment #8 from Alan Modra ---
This patch caused a failure in the gas testsuite.
ia64-hpux +FAIL: ia64 mlx reloc
Investigating how this testsuite failure should be fixed, I took a look at the
ia64 abi and found that the bottom two bits o
https://sourceware.org/bugzilla/show_bug.cgi?id=25599
John David Anglin changed:
What|Removed |Added
Resolution|--- |FIXED
Status|UNCONFIR
https://sourceware.org/bugzilla/show_bug.cgi?id=25599
--- Comment #6 from cvs-commit at gcc dot gnu.org ---
The master branch has been updated by John David Anglin
:
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=ee22a1a31d3432bb40b67229f75ae7c2a271e38e
commit ee22a1a31d3432bb40b672
https://sourceware.org/bugzilla/show_bug.cgi?id=25599
--- Comment #5 from dave.anglin at bell dot net ---
Hi John,
Please send change to binutils list with install request. CC Jim Wilson and
myself. Jim is the
expert on ia64 assembly code.
There are some GNU style issues with the change as wri
https://sourceware.org/bugzilla/show_bug.cgi?id=25599
John Buddery changed:
What|Removed |Added
CC||jvb at cyberscience dot com
--- Commen
https://sourceware.org/bugzilla/show_bug.cgi?id=25599
--- Comment #3 from Peter Bisroev ---
Hi Nick,
Hi John,
I apologize for a very delayed response gentlemen. But I completely agree with
what John has said in his previous comment. Just to expand on his answer for
point (3), from my current und
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John David Anglin changed:
What|Removed |Added
CC||danglin at gcc dot gnu.org
--- Co
https://sourceware.org/bugzilla/show_bug.cgi?id=25599
Nick Clifton changed:
What|Removed |Added
CC||nickc at redhat dot com
--- Comment #1
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oliver.hanser at broadcom dot com changed:
What|Removed |Added
CC||oliver.hanser at br
https://sourceware.org/bugzilla/show_bug.cgi?id=25599
__vic changed:
What|Removed |Added
CC||d.v.a at ngs dot ru
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