https://sourceware.org/bugzilla/show_bug.cgi?id=25599
--- Comment #11 from John Buddery <jvb at cyberscience dot com> --- I will test movl, break.x and nop.x. They have operands of 64, 62 and 62 bits, with very different layout to brl, so PCREL60 won't apply. One potential candidate is PCREL64 against a movl, I'll see if I can generate and test this and anything else I can find (it will be next week though). I see your point about the test - we could be checking for PCREL relocations for an L+X instruction class, rather than PCREL60 relocations. Although the P calculation is bundle based, the r_offset uses 2 bits for the slot, as stated above. It's the r_offset we're adjusting. The info I've been using is on pages 4-6 to 4-8 of the relocation reference you provided a link for. Specifying a slot value for a 2 slot instruction + immediate is clearly ambiguous without further clarification. HP interprets it one way, other platforms differently. I'd say neither is really right or wrong, it's unfortunate that there are differences but we're stuck with it now. -- You are receiving this mail because: You are on the CC list for the bug.
