> Date: Tue, 11 Jan 2022 20:13:59 +0900
> From: SASANO Takayoshi
>
> Hello.
>
> > I have a few more suggestions below. I think the other bits were
> > fine, but can you post the full diff with the fixes suggested below to
> > be sure?
>
> okay, I refelected your suggestion and attach the full
Hello.
> I have a few more suggestions below. I think the other bits were
> fine, but can you post the full diff with the fixes suggested below to
> be sure?
okay, I refelected your suggestion and attach the full diff.
Regards,
--
SASANO Takayoshi (JG1UAA)
Index: dev/fdt/com_fdt.c
==
> Date: Sun, 09 Jan 2022 06:16:12 +0900
> From: SASANO Takayoshi
>
> Hello,
>
> > The com_read_reg() function returns a uint8_t, which means that only
> > the lower 8 bits of the CPR register are returned. So what you need
> > here is something like
> >
> > cpr = bus_space_read_4
Hello,
> The com_read_reg() function returns a uint8_t, which means that only
> the lower 8 bits of the CPR register are returned. So what you need
> here is something like
>
> cpr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, com_cpr << 2);
> sc->sc_fifolen = CPR_FIFO_M
> Date: Sat, 8 Jan 2022 18:23:28 +0100 (CET)
> From: Mark Kettenis
>
> > Date: Mon, 20 Dec 2021 20:14:31 +0900
> > From: SASANO Takayoshi
> >
> > Hello,
> >
> > > Can you send out a diff with just the com(4) changes?
> >
> > Sure, attached after signature.
> > Best regards,
>
> Sorry for the
> Date: Mon, 20 Dec 2021 20:14:31 +0900
> From: SASANO Takayoshi
>
> Hello,
>
> > Can you send out a diff with just the com(4) changes?
>
> Sure, attached after signature.
> Best regards,
Sorry for the late reply. I keep getting distracted. But there is a
bit of problem with this diff:
> In
On Tue, Dec 21, 2021 at 08:30:38PM +0900, SASANO Takayoshi wrote:
Hi,
I tested on rk3399 (Pine64 RockPro64):
com0 at mainbus0: DesignWare APB UART, no fifo
com1 at mainbus0: DesignWare APB UART, no fifo
com1: console
I could talk to the system over the serial console.
Anything else to test?
Hi,
> I tested on rk3399 (Pine64 RockPro64):
>
> com0 at mainbus0: DesignWare APB UART, no fifo
> com1 at mainbus0: DesignWare APB UART, no fifo
> com1: console
>
> I could talk to the system over the serial console.
>
> Anything else to test?
Thank you for testing. I think it is okay that se
On Mon, Dec 20, 2021 at 08:14:31PM +0900, SASANO Takayoshi wrote:
Hello,
Can you send out a diff with just the com(4) changes?
Sure, attached after signature.
I tested on rk3399 (Pine64 RockPro64):
com0 at mainbus0: DesignWare APB UART, no fifo
com1 at mainbus0: DesignWare APB UART, no fif
Hello,
> Can you send out a diff with just the com(4) changes?
Sure, attached after signature.
Best regards,
postscript:
I got Orange Pi Zero2 (Allwinner H616). It looks same remedy requird.
--
SASANO Takayoshi (JG1UAA)
Index: dev/fdt/com_fdt.c
==
> Date: Thu, 2 Dec 2021 21:17:14 +0100 (CET)
> From: Mark Kettenis
>
> > Date: Sat, 27 Nov 2021 06:22:34 +0900
> > From: SASANO Takayoshi
> >
> > Hello,
> >
> > I am still trying to run OpenBSD on Orange Pi One Plus(Allwinner H6).
> > At least following fixes are needed.
> >
> > - add AXP805
Hi,
> - Asserting PHY's reset signal is the remedy, but no definition in DTB
>
> Orange Pi One Plus assigns GPIO-PD14 for resetting PHY chip,
> but there is no definition in Device Tree. If it is defined,
> if_dwxe does not handle the signal (if_dwge, if_fec can handle this).
> Currently there is
Hi,
I found this problem caused by ARM Trusted Firmware (ATF).
>> Even if these fix are applied, dwxe cannot find ethernet PHY (RT8211).
>> Orange Pi One Plus' Schematics and DTB defines PHY address as 0x01,
>> but actually probed at 0x00 (MII broadcast) and 0x07.
>> We have to modify DTB or take
> Date: Sat, 27 Nov 2021 06:22:34 +0900
> From: SASANO Takayoshi
>
> Hello,
>
> I am still trying to run OpenBSD on Orange Pi One Plus(Allwinner H6).
> At least following fixes are needed.
>
> - add AXP805 support to axppmic
> - add DW-UART FIFO fix to com
> (previously posted at
> https://
14 matches
Mail list logo
