> Date: Sat, 8 Jan 2022 18:23:28 +0100 (CET)
> From: Mark Kettenis <mark.kette...@xs4all.nl>
>
> > Date: Mon, 20 Dec 2021 20:14:31 +0900
> > From: SASANO Takayoshi <u...@mx5.nisiq.net>
> >
> > Hello,
> >
> > > Can you send out a diff with just the com(4) changes?
> >
> > Sure, attached after signature.
> > Best regards,
>
> Sorry for the late reply. I keep getting distracted. But there is a
> bit of problem with this diff:
>
> > Index: dev/ic/com.c
> > ===================================================================
> > RCS file: /cvs/src/sys/dev/ic/com.c,v
> > retrieving revision 1.174
> > diff -u -p -u -p -r1.174 com.c
> > --- dev/ic/com.c 6 May 2021 20:35:21 -0000 1.174
> > +++ dev/ic/com.c 20 Dec 2021 11:06:09 -0000
> > @@ -1300,7 +1300,7 @@ void
> > com_attach_subr(struct com_softc *sc)
> > {
> > int probe = 0;
> > - u_int8_t lcr;
> > + u_int8_t lcr, fifo;
> >
> > sc->sc_ier = 0;
> > /* disable interrupts */
> > @@ -1480,6 +1480,25 @@ com_attach_subr(struct com_softc *sc)
> > SET(sc->sc_hwflags, COM_HW_FIFO);
> > sc->sc_fifolen = 256;
> > break;
> > + case COM_UART_DW_APB:
> > + printf(": DesignWare APB UART, ");
> > + SET(sc->sc_hwflags, COM_HW_FIFO);
> > + sc->sc_fifolen = CPR_FIFO_MODE(com_read_reg(sc, com_cpr)) * 16;
>
> The com_read_reg() function returns a uint8_t, which means that only
> the lower 8 bits of the CPR register are returned. So what you need
> here is something like
>
> cpr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, com_cpr << 2);
> sc->sc_fifolen = CPR_FIFO_MODE(cpr) * 16;
>
> With that change, the Rockchip RK3399 UART reports a 64-byte FIFO,
> which matches the datasheet for that SoC.
>
> What happens on the H6 and H616 with that code? Does it also report a
> non-zero FIFO size? In that case we probably should change the code a
> bit.
On the A64, the CPR is actually 0. So we have to handle that case I
suppose. So the code can stay mostly the same.
