From: Victor Zhao
[ Upstream commit 9a4ab400f1fad0e6e8686b8f5fc5376383860ce8 ]
Use second jump table in sriov for live migration or mulitple VF
support so different VF can load different version of MEC as long
as they support sjt
Signed-off-by: Victor Zhao
Reviewed-by: Yang Wang
Signed-off-by
From: Prike Liang
[ Upstream commit 5c3de6b02d38eb9386edf50490e050bb44398e40 ]
The SVM DMA device map direction should be set the same as
the DMA unmap setting, otherwise the DMA core will report
the following warning.
Before finialize this solution, there're some discussion on
the DMA mapping
From: Prike Liang
[ Upstream commit 5c3de6b02d38eb9386edf50490e050bb44398e40 ]
The SVM DMA device map direction should be set the same as
the DMA unmap setting, otherwise the DMA core will report
the following warning.
Before finialize this solution, there're some discussion on
the DMA mapping
From: Prike Liang
[ Upstream commit 5c3de6b02d38eb9386edf50490e050bb44398e40 ]
The SVM DMA device map direction should be set the same as
the DMA unmap setting, otherwise the DMA core will report
the following warning.
Before finialize this solution, there're some discussion on
the DMA mapping
From: Prike Liang
[ Upstream commit 5c3de6b02d38eb9386edf50490e050bb44398e40 ]
The SVM DMA device map direction should be set the same as
the DMA unmap setting, otherwise the DMA core will report
the following warning.
Before finialize this solution, there're some discussion on
the DMA mapping
On 12/20/2024 4:08 PM, Christian König wrote:
Hi Arun,
Am 20.12.24 um 11:34 schrieb Paneer Selvam, Arunpravin:
Hi Christian,
On 12/19/2024 4:11 PM, Christian König wrote:
Am 19.12.24 um 11:38 schrieb Arunpravin Paneer Selvam:
Fix out-of-bounds issue in userq fence create when
accessin
This is getting long, so tl;dr:
- Pitch alignment *by itself* is manageable.
- Adding constraints in modifiers quickly leads to combinatorial
explosion.
- drm_fourcc.h explicitly says "it's incorrect to encode pitch
alignment in a modifier", for all the reasons Daniel raised. That
need
On 12/19/2024 03:22 AM, Alex Deucher wrote:
On Wed, Dec 18, 2024 at 2:18 PM Josh Poimboeuf wrote:
On Wed, Dec 18, 2024 at 10:36:00PM +0800, Huacai Chen wrote:
Hi, Tiezhu,
On Tue, Dec 17, 2024 at 9:50 AM Tiezhu Yang wrote:
When compiling with Clang on LoongArch, there exists the following
On Fri, Dec 20, 2024 at 11:31:00AM +0100, Peter Zijlstra wrote:
> Also, curse the DRM Makefiles, you can't do:
>
> make drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.s
Small tip: You can get the path of the target by building
drivers/gpu/drm/amd/amdgpu/ and finding it in the output. In this
>
> * Modifiers must uniquely encode buffer layout. In other words, a buffer
> must
> * match only a single modifier.
>
That sentence is misleading and impossible to meet. Specifications are
sometimes changed to reflect the overwhelming reality. Multiple modifiers
can represent identical layouts
Hi André,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on drm-intel/for-linux-next
drm-intel/for-linux-next-fixes drm-tip/drm-tip v6.13-rc3 next-20241220]
[If your patch is applied to the wrong git tree, kindly drop us a
On Fri, Dec 20, 2024 at 01:02:18PM +0800, Tiezhu Yang wrote:
> 2. For x86
>
> I tested with LLVM 19.1.6 and the latest mainline LLVM, the test result
> is same with LoongArch.
Debian's clang-19 is 19.1.5.
> (1) objdump info with LLVM release version 19.1.6:
Please always use -r, that's ever so
Hi Christian,
On 12/19/2024 4:11 PM, Christian König wrote:
Am 19.12.24 um 11:38 schrieb Arunpravin Paneer Selvam:
Fix out-of-bounds issue in userq fence create when
accessing the userq xa structure. Added a lock to
protect the race condition.
v2:(Christian)
- Acquire xa lock only for th
Hi Matthew,
On 12/16/2024 11:52 PM, Matthew Auld wrote:
On 16/12/2024 13:07, Arunpravin Paneer Selvam wrote:
- Added a testcase to verify the multiroot force merge fini.
- Added a new field in_use to track the mm freed status.
Signed-off-by: Arunpravin Paneer Selvam
Signed-off-by: Lin.Cao
Hi Arun,
Am 20.12.24 um 11:34 schrieb Paneer Selvam, Arunpravin:
Hi Christian,
On 12/19/2024 4:11 PM, Christian König wrote:
Am 19.12.24 um 11:38 schrieb Arunpravin Paneer Selvam:
Fix out-of-bounds issue in userq fence create when
accessing the userq xa structure. Added a lock to
protect t
Hi André,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on v6.13-rc3 next-20241220]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as
On Thu, Dec 19, 2024 at 05:09:33PM +0100, Michel Dänzer wrote:
> On 2024-12-19 10:02, Daniel Stone wrote:
> >
> > How this would be used in practice is also way too underdocumented. We
> > need to document that exact-round-up 64b is more restrictive than
> > any-multiple-of 64b is more restrictive
On Fri, Dec 20, 2024 at 09:24:59AM -0500, Marek Olšák wrote:
> >
> > * Modifiers must uniquely encode buffer layout. In other words, a buffer
> > must
> > * match only a single modifier.
> >
>
> That sentence is misleading and impossible to meet. Specifications are
> sometimes changed to reflect
From: George Shen
[Why]
Some features, such as HBlank expansion/reduction, needs to know how
much HBlank is required to support basic audio.
[How]
Add interface to link to calculate required HBlank size for a given
link + timing combination to support basic audio (i.e. 2-channel 48KHz).
Reviewe
From: Dillon Varone
[WHY&HOW]
- Remove legacy update clocks sequence
- FCLK P-State allow message is not required
Reviewed-by: Alvin Lee
Signed-off-by: Dillon Varone
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 240 ++
From: George Shen
[Why]
DPCD register RECEIVE_PORT0_CAP contains HBlank expansion/reduction
capabilities of a DP device. These capabilities are required to enable
HBlank expansion/reduction logic.
[How]
Read raw RECEIVE_PORT0_CAP register values and store parsed fields.
Reviewed-by: Wenjing Liu
From: George Shen
[Why]
For DP HBlank expansion/reduction, the HBlank parameters of the original
EDID timing needs to be notified to the sink in order for the timing to
be reduced back to the original HBlank size.
[How]
Add parameter in dc_crtc_timing to track the increased HBlank.
Reviewed-by:
From: Roman Li
- Improvements for DP, Replay/PSR, DML, SPL, DCN32, DCN35, DCN401
- Extended logging for DSC, VABC and stream crc
- Optimization for cursor position updates
Aric Cyr (1):
drm/amd/display: Optimize cursor position updates
Aurabindo Pillai (1):
drm/amd/display: Add guards ar
From: Wayne Lin
[Why & How]
Have to support multiple CRC windows setting to dmub. Add new dmub forward
functions for supporting/forwarding multiple crc windows setting to dmub.
Reviewed-by: HaoPing Liu
Signed-off-by: Wayne Lin
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
drivers/gp
From: Wayne Lin
[Why & How]
Since now we can set multiple crc windows for secure display, add a new input
parameter for dc_stream_get_crc to indicate to fetch crc from which crc
engine.
Reviewed-by: HaoPing Liu
Signed-off-by: Wayne Lin
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
.
From: Samson Tam
[Why & How]
Use helper functions for checking formats
Apply cositing offset in rotation case
Reviewed-by: Navid Assadian
Signed-off-by: Samson Tam
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 88 ++---
1
From: George Shen
[Why]
Current DCN32 calculation doesn't consider RGB 6bpc for the DP case.
This results in an invalid output bpp being calculated when DSC is not
enabled in the configuration, failing the mode validation.
[How]
Add special case to handle 6bpc RGB in the output bpp calculation.
From: Karthi Kandasamy
[WHY]
The `dc_tiling_info` union previously did not have a field to
specify the active GFX format, assuming only one format would
be used per DCN version. from DCN4+, support for switching
between different GFX formats is introduced, requiring a way
to track which format is
From: Martin Leung
This version brings along the following:
- Add Interface to Dump DSC Caps from dm
- Add DP required HBlank size calc to link interface
- Add 6bpc RGB case for dcn32 output bpp calculations
- Add VC for VESA Aux Backlight Control
- Add support for setting multiple CRC windows in
From: Tom Chung
[Why]
The enum DC_PSR_VERSION_SU_1 of psr_version is 1 and
DC_PSR_VERSION_UNSUPPORTED is 0x.
The original code may has chance trigger the amdgpu_dm_psr_enable()
while psr version is set to DC_PSR_VERSION_UNSUPPORTED.
[How]
Modify the condition to psr->psr_version == DC_P
From: Brandon Syu
[why]
initialize the power state for dc use,
but dc_set_power_state it not called at D3.
It would cause can't recognize last power state
[how]
remove initialize the power state for dc use, it is not necessary.
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Brandon Syu
Signe
From: Aric Cyr
[why]
Updating the cursor enablement register can be a slow operation and accumulates
when high polling rate cursors cause frequent updates asynchronously to the
cursor position.
[how]
Since the cursor enable bit is cached there is no need to update the
enablement register if ther
From: Tom Chung
[Why]
Replay and PSR will cause some video corruption while VRR is enabled.
[How]
1. Disable the Replay and PSR while VRR is enabled.
2. Change the amdgpu_dm_crtc_vrr_active() parameter to const.
Because the function will only read data from dm_crtc_state.
Reviewed-by: Sun pe
From: "Dennis.Chan"
[why]
Add new Visual confirm color for Replay Low Hz.
Reviewed-by: Robin Chen
Signed-off-by: Dennis.Chan
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 11 ++--
.../dc/link/protocols/link_dp_irq_handler.c | 2 +
.
From: Fangzhi Zuo
No common dsc params found between encoder and decoder is one
of the reason that could prevent dsc from properly enabled.
Dump the params to a specific timing to help locate possible
invalid dsc params in either encoder or decoder side.
Reviewed-by: Aurabindo Pillai
Signed-of
From: George Shen
[Why]
Certain small HBlank timings may not have a large enough HBlank to
support audio when low bpp DSC is enabled. HBlank expansion by the
source can solve this problem, but requires the branch/sink to support
HBlank reduction.
[How]
Update DPMS sequence to call DM to perform
From: Karthi Kandasamy
[Why]
To ensure DML validation receives the correct tiling information,
such as swizzle mode or array mode, based on the active GFX format
[How]
- For new GFX format passed swizzle_mode to DML.
- For legacy GFX format passed array_mode to DML.
- Dynamically determined the
From: Roman Li
[Why]
Wrapper functions for dcn_bw_ceil2() and dcn_bw_floor2()
should check for granularity is non zero to avoid assert and
divide-by-zero error in dcn_bw_ functions.
[How]
Add check for granularity 0.
Cc: Mario Limonciello
Cc: sta...@vger.kernel.org
Reviewed-by: Alvin Lee
Sign
From: Peichen Huang
[WHY]
We like to have pretrain for dpia link so that dp and dp tunneling
have aligned behavior. The Main difficult for dpia pretrain is that
encoder can not get corresponded dpia port when link detection
in current implementation.
[HOW]
1. create enable/disable dpia output fu
From: Samson Tam
[Why & How]
init_adj offset is applied when cosited not interstitial
Adjust cositing offset in SPL
Reviewed-by: Jun Lei
Signed-off-by: Samson Tam
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
.../amd/display/dc/resource/dcn401/dcn401_resource.c | 2 +-
drivers/gpu
From: Wayne Lin
[Why & How]
We already extend our dm, dc and dmub to support setting of multiple CRC
instances, now extend the capability to return back the ROI/CRC pair result
from psp by specifying activated ROI instances.
Reviewed-by: HaoPing Liu
Signed-off-by: Wayne Lin
Signed-off-by: Roma
From: Yihan Zhu
[WHY & HOW]
No check for HUBP/DPP power gating when DSC instance is still running. Avoid
HUBP/DPP to
power gate when corresponding DSC block is still running in the power gating
calculation.
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: Duncan Ma
Signed-off-by: Yihan Zhu
Sig
From: Yihan Zhu
[WHY & HOW]
Driver disable will deallocate framebuffer to reset IPS state, this will cause
IPS start with
INIT state to blindly power gate ONO region to break power sequence. All the
gating blocks
should be powered up when releasing hw to ensure all the power optimizations
are
From: Aurabindo Pillai
MAX/MIN macros maybe defined already, hence add a guard around them to
prevent errors that complain about redefinition like:
drivers/gpu/drm/amd/amdgpu/../dal-dev/modules/hdcp/hdcp_ddc.c:31: error: "MIN"
redefined [-Werror]
31 | #define MIN(a, b) ((a) < (b) ? (a) : (b)
From: Wayne Lin
[Why & How]
We actually have the capability to calculate independent CRC for 2 crc window
at the same time. Extend dm with the capability by having array to
configure/maintain multiple crc windows. Add the flexibility but use 1st CRC
instance only for now. Can change to use the 2n
From: Iswara Nagulendran
[WHY]
There is no way to distinguish
the static backlight control type
being used and the VABC support
without the use of a debugger or
reading DPCD registers.
[HOW]
Add Visual Confirm support
for VESA Aux-based Backlight Control.
Reviewed-by: Harry Vanzylldejong
Signe
From: Natanel Roizenman
[Why]
Comparisons were made between unsigned char and unsigned int.
[How]
Corrected by changing variable types.
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Natanel Roizenman
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
.../dml2/dml21/src/dml2_dpmm/dml2_
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