Re: [PATCH] drm/amdgpu/vcn: drop gfxoff control for VCN2+

Acked-by: Christian König Am 07.06.21 um 23:32 schrieb Zhang, Boyuan: [AMD Official Use Only] Patch is Reviewed-by: Boyuan Zhang Thanks, Boyuan -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: June 7, 2021 4:29 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexa

Re: [PATCH] drm/amd/display: Fix overlay validation by considering cursors

On 2021-06-07 8:45 p.m., Sean Paul wrote: > > > On Mon, Jun 7, 2021 at 2:37 PM Harry Wentland > wrote: > > On 2021-06-07 2:19 p.m., Sean Paul wrote: > > On Tue, May 18, 2021 at 2:58 PM Rodrigo Siqueira > > mailto:rodrigo.sique...@amd.com>> wrote: >

[PATCH V3 1/5] drm/amd/pm: drop the incomplete fix for Navi14 runpm issue

As the fix by adding PPSMC_MSG_PrepareMp1ForUnload is proved to be incomplete. Another fix(see link below) has been sent out. Link: https://lore.kernel.org/linux-pci/20210602021255.939090-1-evan.q...@amd.com/ Change-Id: I2a39688cdf9009885594663cd9ec99d4cfca0088 Signed-off-by: Evan Quan --- driv

[PATCH V3 4/5] drm/amd/pm: update the cached dpm feature status

For some ASICs, the real dpm feature disablement job is handled by PMFW during baco reset and custom pptable loading. Cached dpm feature status need to be updated to pair that. Change-Id: I9e37d80e13599833301c04711b097fb37c2e41f9 Signed-off-by: Evan Quan --- V1->V2: - correct the setting for ba

[PATCH V3 2/5] drm/amd/pm: correct the runpm handling for BACO supported ASIC

Via the fSMC_MSG_ArmD3 message, PMFW can properly act on the Dstate change. Driver involvement for determining the timing for BACO enter/exit is not needed. Change-Id: Id9ab5e308ff1873888d0acd822c71b0a303fbb01 Signed-off-by: Evan Quan --- V1->V2: - limit the changes for Navi1x and Sienna_Cichli

[PATCH V3 5/5] drm/amd/pm: correct the dpm features disablement for Navi1x

For BACO scenario, PMFW will handle the dpm features disablement and interaction with RLC properly. Driver involvement is unnecessary and error prone. Change-Id: I19363fc08568be4b7d3f2ec6eba21ccf8fff6c37 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ++- 1 file chang

[PATCH V3 3/5] drm/amdgpu: make audio dev's D-state transition PMFW-aware

To correctly kick into BACO state, the audio dev's D-state transition(D0->D3) needs to be PMFW-aware. So, if the audio dev entered D3 state prior to our driver, we need to bring it back to D0 state and make sure there will be a D-state transition on runpm suspend. Change-Id: I136e196be7633e95883a7

RE: [PATCH 4/5] drm/amdgpu: add psp ta microcode init for aldebaran sriov vf

[AMD Official Use Only] Series is Reviewed-by: Hawking Zhang Regards, Hawking -Original Message- From: amd-gfx On Behalf Of Zhigang Luo Sent: Tuesday, June 8, 2021 03:23 To: amd-gfx@lists.freedesktop.org Cc: Luo, Zhigang Subject: [PATCH 4/5] drm/amdgpu: add psp ta microcode init for a

Re: [Mesa-dev] XDC 2021: Registration & Call for Proposals now open!

Kind reminder. Deadline is Sunday, 4 July 2021 :-) Sam On Thu, 2021-05-20 at 10:01 +, Szwichtenberg, Radoslaw wrote: > Hello! >   > Registration & Call for Proposals are now open for XDC 2021, which > will > take place on September 15-17, 2021. This year we will repeat as > virtual event. >  

RE: [PATCH V3 1/5] drm/amd/pm: drop the incomplete fix for Navi14 runpm issue

[AMD Official Use Only] Series is Reviewed-by: Lijo Lazar -Original Message- From: Quan, Evan Sent: Tuesday, June 8, 2021 10:04 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Lazar, Lijo ; Quan, Evan Subject: [PATCH V3 1/5] drm/amd/pm: drop the incomplete fix for Navi

RE: [PATCH v5 7/9] drm/amd/pm: Add vangogh throttler translation

[Public] Didn't realize 16-bits will max out so fast. For THM_GFX - "SMU_THROTTLER_TEMP_GPU_BIT" looks appropriate. SOC domain will need a new one. As temp throttling reasons are more, you may shift the "OTHERS" by 8-bits if required. Thanks, Lijo -Original Message- From: Sider, Grah

Re: [PATCH v2 1/1] drm/amdkfd: use allowed domain for vmbo validation

Am 08.06.21 um 13:27 schrieb Nirmoy Das: Fixes handling when page tables are in system memory. v2: remove unwanted variable. change amdgpu_amdkfd_validate instead of amdgpu_amdkfd_bo_validate. Signed-off-by: Nirmoy Das --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 15 ---

[PATCH 1/1] drm/amdkfd: use allowed domain for vmbo validation

Remove fixed domain and use BO's allowed domain for PT/PD BO validation. Signed-off-by: Nirmoy Das --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/am

Re: [PATCH 1/1] drm/amdkfd: use allowed domain for vmbo validation

Am 08.06.21 um 11:32 schrieb Nirmoy Das: Remove fixed domain and use BO's allowed domain for PT/PD BO validation. "Fixes handling when page tables are in system memory". And I think you can now remove the validate structure as well. Christian. Signed-off-by: Nirmoy Das --- drivers/gpu/d

Re: [PATCH 1/1] drm/amdkfd: use allowed domain for vmbo validation

On 6/8/2021 11:37 AM, Christian König wrote: Am 08.06.21 um 11:32 schrieb Nirmoy Das: Remove fixed domain and use BO's allowed domain for PT/PD BO validation. "Fixes handling when page tables are in system memory". And I think you can now remove the validate structure as well. Do you mean

[PATCH 1/1] drm/amdgpu: fix shadow bo skip condition

Create shadow BOs only for no-compute VM context and only for dGPU. The existing if-condition would create shadow bo for compute context on dGPU which not what we wanted. Signed-off-by: Nirmoy Das --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) d

Re: [RFC PATCH v2 1/8] ext4/xfs: add page refcount helper

On Tue, Jun 08, 2021 at 12:29:04AM +, Liam Howlett wrote: > * Alex Sierra [210607 16:43]: > > From: Ralph Campbell > > > > There are several places where ZONE_DEVICE struct pages assume a reference > > count == 1 means the page is idle and free. Instead of open coding this, > > add a helper

Re: [RFC PATCH v2 0/8] Support DEVICE_GENERIC memory in migrate_vma_*

On Mon, Jun 07, 2021 at 03:42:18PM -0500, Alex Sierra wrote: > v1: > https://lore.kernel.org/linux-mm/20210529064022.gb15...@lst.de/T/ Please copy and paste the rationale into followup patch series instead of sending a link: AMD is building a system architecture for the Frontier supercomputer wit

Re: [PATCH] drm/radeon: Always call radeon_suspend_kms() in radeon_pci_shutdown()

On Mon, Jun 7, 2021 at 10:26 PM Tiezhu Yang wrote: > > On 06/07/2021 09:42 PM, Alex Deucher wrote: > > On Mon, Jun 7, 2021 at 8:30 AM Christian König > > wrote: > >> Am 07.06.21 um 14:27 schrieb Tiezhu Yang: > >>> radeon_suspend_kms() puts the hw in the suspend state (all asics), > >>> it should

Re: [PATCH 1/1] drm/amdgpu: fix shadow bo skip condition

Am 08.06.21 um 12:06 schrieb Nirmoy Das: Create shadow BOs only for no-compute VM context and only for dGPU. The existing if-condition would create shadow bo for compute context on dGPU which not what we wanted. Signed-off-by: Nirmoy Das Reviewed-by: Christian König --- drivers/gpu/drm/a

Re: [PATCH 1/1] drm/amdkfd: use allowed domain for vmbo validation

Am 08.06.21 um 11:58 schrieb Das, Nirmoy: On 6/8/2021 11:37 AM, Christian König wrote: Am 08.06.21 um 11:32 schrieb Nirmoy Das: Remove fixed domain and use BO's allowed domain for PT/PD BO validation. "Fixes handling when page tables are in system memory". And I think you can now remove t

RE: [PATCH] drm/amd/pm: fix warning reported by kernel test robot

Reviewed-by: Huang Rui -Original Message- From: Hou, Xiaomeng (Matthew) Sent: Monday, June 7, 2021 8:46 PM To: amd-gfx@lists.freedesktop.org Cc: Huang, Ray ; Wang, Kevin(Yang) ; Hou, Xiaomeng (Matthew) Subject: [PATCH] drm/amd/pm: fix warning reported by kernel test robot Kernel test

[PATCH v2 1/1] drm/amdkfd: use allowed domain for vmbo validation

Fixes handling when page tables are in system memory. v2: remove unwanted variable. change amdgpu_amdkfd_validate instead of amdgpu_amdkfd_bo_validate. Signed-off-by: Nirmoy Das --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 15 --- 1 file changed, 4 insertions(+), 11 de

Re: [PATCH v2 1/1] drm/amdkfd: use allowed domain for vmbo validation

On 6/8/2021 1:42 PM, Christian König wrote: Am 08.06.21 um 13:27 schrieb Nirmoy Das: Fixes handling when page tables are in system memory. v2: remove unwanted variable. change amdgpu_amdkfd_validate instead of amdgpu_amdkfd_bo_validate. Signed-off-by: Nirmoy Das ---   drivers/gpu/drm/

[PATCH v3 1/1] drm/amdkfd: use allowed domain for vmbo validation

Fixes handling when page tables are in system memory. v3: remove struct amdgpu_vm_parser. v2: remove unwanted variable. change amdgpu_amdkfd_validate instead of amdgpu_amdkfd_bo_validate. Signed-off-by: Nirmoy Das --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 21 --- 1

Re: [PATCH v3 1/1] drm/amdkfd: use allowed domain for vmbo validation

Am 08.06.21 um 15:06 schrieb Nirmoy Das: Fixes handling when page tables are in system memory. v3: remove struct amdgpu_vm_parser. v2: remove unwanted variable. change amdgpu_amdkfd_validate instead of amdgpu_amdkfd_bo_validate. Signed-off-by: Nirmoy Das Reviewed-by: Christian König bu

Re: [PATCH 4/4] drm/i915/display: Add handling for new "active bpc" property

Am 07.06.21 um 22:33 schrieb Werner Sembach: Am 07.06.21 um 08:47 schrieb Werner Sembach: Am 04.06.21 um 19:30 schrieb Ville Syrjälä: On Fri, Jun 04, 2021 at 07:17:23PM +0200, Werner Sembach wrote: This commits implements the "active bpc" drm property for the Intel GPU driver. Signed-off-b

[PATCH 0/7] Add "activ bpc" and "active color format" drm property

I started work on my proposal for better color handling in Linux display drivers: https://lkml.org/lkml/2021/5/12/764 In this 2nd revision the first two read-only properties are now implemented for amdgpu and i915. I post it here to collect collect some additional feedback, if someone sees an impr

[PATCH v2 3/7] drm/amd/display: Add handling for new "active bpc" property

This commit implements the "active bpc" drm property for the AMD GPU driver. Signed-off-by: Werner Sembach --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 +- .../display/amdgpu_dm/amdgpu_dm_mst_types.c| 4 +++- 2 files changed, 20 insertions(+), 2 deletions(-) diff

[PATCH v2 1/7] drm/amd/display: Add missing cases convert_dc_color_depth_into_bpc

convert_dc_color_depth_into_bpc() that converts the enum dc_color_depth to an integer had the casses for COLOR_DEPTH_999 and COLOR_DEPTH_11 missing. Signed-off-by: Werner Sembach --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 1 file changed, 4 insertions(+) diff --git a/dri

[PATCH v2 2/7] drm/uAPI: Add "active bpc" as feedback channel for "max bpc" drm property

Add a new general drm property "active bpc" which can be used by graphic drivers to report the applied bit depth per pixel back to userspace. While "max bpc" can be used to change the color depth, there was no way to check which one actually got used. While in theory the driver chooses the best/hi

[PATCH v2 4/7] drm/i915/display: Add handling for new "active bpc" property

This commits implements the "active bpc" drm property for the Intel GPU driver. Signed-off-by: Werner Sembach --- drivers/gpu/drm/i915/display/intel_display.c | 14 ++ drivers/gpu/drm/i915/display/intel_dp.c | 8 ++-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +++-

[PATCH v2 6/7] drm/amd/display: Add handling for new "active color format" property

This commit implements the "active color format" drm property for the AMD GPU driver. Signed-off-by: Werner Sembach --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 27 +-- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 1 + 2 files changed, 26 insertions(+), 2 deletions(-)

[PATCH v2 5/7] drm/uAPI: Add "active color format" drm property as feedback for userspace

Add a new general drm property "active color format" which can be used by graphic drivers to report the used color format back to userspace. There was no way to check which color format got actually used on a given monitor. To surely predict this, one must know the exact capabilities of the monito

[PATCH v2 7/7] drm/i915/display: Add handling for new "active color format" property

This commit implements the "active color format" drm property for the Intel GPU driver. Signed-off-by: Werner Sembach --- drivers/gpu/drm/i915/display/intel_display.c | 20 +++- drivers/gpu/drm/i915/display/intel_dp.c | 2 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c |

Re: [PATCH] drm/amd/display: Fix error code on failure to set brightness

On 2021-06-08 12:32 a.m., Anand K Mistry wrote: > The backlight_ops.update_status function is required to return a > negative error code on failure. Returning a positive code may be > interpreted as a success. This is true for the 'brightness' sysfs file, > which passes through a non-zero value as

RE: [PATCH 00/30] DC Patches June, 7, 2021

[Public] Hi all,   This week this patchset was tested on the following systems: HP Envy 360, with Ryzen 5 4500U, with the following display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA) AMD Ry

回复: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV

Reviewed-by: Horace Chen 发件人: Koenig, Christian 发送时间: 2021年6月8日 3:41 收件人: Khaire, Rohit ; amd-gfx@lists.freedesktop.org ; Kuehling, Felix ; Deucher, Alexander ; Zhang, Hawking ; Deng, Emily ; Liu, Monk ; Zhou, Peng Ju ; Chen, Horace 抄送: Ming, Davis 主题: Re:

[PATCH v6 2/9] drm/amd/pm: Add ASIC independent throttle bits

Add new defines for thermal throttle status bits which are ASIC independent. This bit field will be visible to userspace via gpu_metrics alongside the previous ASIC dependent bit fields. Seperated into four types: power throttlers (16 bits), current throttlers (16 bits), temperature (24 bits), othe

[PATCH v6 5/9] drm/amd/pm: Add navi1x throttler translation

Perform dependent to independent throttle status translation for navi1x. Signed-off-by: Graham Sider --- .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 34 +++ 1 file changed, 34 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/p

[PATCH v6 4/9] drm/amd/pm: Add arcturus throttler translation

Perform dependent to independent throttle status translation for arcturus. Signed-off-by: Graham Sider --- .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 33 --- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/d

[PATCH v6 3/9] drm/amd/pm: Add common throttler translation func

Defines smu_cmn_get_indep_throttler_status which performs ASIC independent translation given a corresponding lookup table. Signed-off-by: Graham Sider --- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 13 + drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 4 2 files changed, 17 insertions(+

[PATCH v6 8/9] drm/amd/pm: Add renoir throttler translation

Perform dependent to independent throttle status translation for renoir. Signed-off-by: Graham Sider --- .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 29 +++ 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drive

[PATCH v6 1/9] drm/amd/pm: Add u64 throttler status field to gpu_metrics

This patch set adds support for a new ASIC independant u64 throttler status field (indep_throttle_status). Piggybacks off the gpu_metrics_v1_3 bump and similarly bumps gpu_metrics_v2 version (to v2_2) to add field. Signed-off-by: Graham Sider --- .../gpu/drm/amd/include/kgd_pp_interface.h| 5

[PATCH v6 9/9] drm/amd/pm: Add aldebaran throttler translation

Perform dependent to independent throttle status translation for aldebaran. Signed-off-by: Graham Sider --- .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 27 +++ 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b

[PATCH v6 6/9] drm/amd/pm: Add sienna cichlid throttler translation

Perform dependent to independent throttle status translation for sienna cichlid. Signed-off-by: Graham Sider --- .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 34 --- 1 file changed, 29 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichli

[PATCH v6 7/9] drm/amd/pm: Add vangogh throttler translation

Perform dependent to independent throttle status translation for vangogh. Signed-off-by: Graham Sider --- .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 38 ++- 1 file changed, 29 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/dri

Re: [PATCH v2 1/1] drm/amdkfd: use allowed domain for vmbo validation

Hi Nirmoy, Why keep a unused parameter: +static int amdgpu_amdkfd_validate_vm_bo(void *_unused. When I looked the codes, the only logic change is the validate page table bo in allowed_domain instead of vram domain. Can you explain why validate page table bo in vram domain cause a problem? When

RE: [PATCH V2] drm/amd/pm: correct the power limits reporting on OOB supported

[AMD Official Use Only] Reviewed-By: Harish Kasiviswanathan -Original Message- From: Quan, Evan Sent: Monday, June 7, 2021 10:09 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Lazar, Lijo ; Kasiviswanathan, Harish ; Quan, Evan Subject: [PATCH V2] drm/amd/pm: correct t

[PATCH] drm/amd/display: Fix build break

1. Remove duplicate OTG_PIXEL_RATE_CNTL from dccg_registers 2. Fixes: 18827ee0cc28 ("drm/amd/display: Refactor visual confirm") Signed-off-by: Anson Jacob --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 1 - drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 3 +-- 2 files changed, 1 in

Re: [PATCH] drm/amd/display: Fix build break

[Public] Reviewed-by: Alex Deucher From: amd-gfx on behalf of Anson Jacob Sent: Tuesday, June 8, 2021 11:36 AM To: amd-gfx@lists.freedesktop.org Cc: Brol, Eryk ; Li, Sun peng (Leo) ; Wentland, Harry ; Zhuo, Qingqing ; Siqueira, Rodrigo ; Li, Roman ; Jacob,

Re: [PATCH v2 1/1] drm/amdkfd: use allowed domain for vmbo validation

On 6/8/2021 5:28 PM, Zeng, Oak wrote: Hi Nirmoy, Why keep a unused parameter: +static int amdgpu_amdkfd_validate_vm_bo(void *_unused. We pass this func to amdgpu_vm_validate_pt_bos() which requires two args: int (*validate)(void *p, struct amdgpu_bo *bo) When I looked the codes, the on

Re: [PATCH v3 1/1] drm/amdkfd: use allowed domain for vmbo validation

Am 2021-06-08 um 9:08 a.m. schrieb Christian König: > Am 08.06.21 um 15:06 schrieb Nirmoy Das: >> Fixes handling when page tables are in system memory. >> >> v3: remove struct amdgpu_vm_parser. >> v2: remove unwanted variable. >> change amdgpu_amdkfd_validate instead of amdgpu_amdkfd_bo_valida

Re: [PATCH] drm/amd/display: Fix overlay validation by considering cursors

On 2021-06-08 3:47 a.m., Michel Dänzer wrote: > On 2021-06-07 8:45 p.m., Sean Paul wrote: >> >> >> On Mon, Jun 7, 2021 at 2:37 PM Harry Wentland > > wrote: >> >> On 2021-06-07 2:19 p.m., Sean Paul wrote: >> > On Tue, May 18, 2021 at 2:58 PM Rodrigo Siqueira

Re: [PATCH] drm/amd/display: Fix overlay validation by considering cursors

On Tue, Jun 8, 2021 at 3:07 PM Harry Wentland wrote: > > > > On 2021-06-08 3:47 a.m., Michel Dänzer wrote: > > On 2021-06-07 8:45 p.m., Sean Paul wrote: > >> > >> > >> On Mon, Jun 7, 2021 at 2:37 PM Harry Wentland >> > wrote: > >> > >> On 2021-06-07 2:19 p.m., S

[PATCH 12/40] drm/amdgpu: Remember to wait 10ms for write buffer flush v2

From: Andrey Grodzovsky EEPROM spec requests this. v2: Only to be done for write data transactions. Signed-off-by: Andrey Grodzovsky Signed-off-by: Alex Deucher Reviewed-by: Luben Tuikov --- drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c | 15 +++ 1 file changed, 15 insertions(+) d

[PATCH 07/40] drm/amdgpu/ras: switch fru eeprom handling to use generic helper (v2)

From: Alex Deucher Use the new helper rather than doing i2c transfers directly. v2: fix typo Signed-off-by: Alex Deucher Reviewed-by: Luben Tuikov --- .../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c| 22 +-- 1 file changed, 6 insertions(+), 16 deletions(-) diff --git a/driver

[PATCH 17/40] drm/amdgpu/pm: ADD I2C quirk adapter table

From: Andrey Grodzovsky To be used by kernel clients of the adapter. Cc: Jean Delvare Cc: Alexander Deucher Cc: Andrey Grodzovsky Cc: Lijo Lazar Cc: Stanley Yang Cc: Hawking Zhang Signed-off-by: Andrey Grodzovsky Suggested-by: Lazar Lijo Signed-off-by: Luben Tuikov Reviewed-by: Luben Tu

[PATCH 16/40] drm/amd/pm: SMU I2C: Return number of messages processed

From: Andrey Grodzovsky Fix from number of processed bytes to number of processed I2C messages. Cc: Jean Delvare Cc: Alexander Deucher Cc: Andrey Grodzovsky Cc: Lijo Lazar Cc: Stanley Yang Cc: Hawking Zhang Signed-off-by: Andrey Grodzovsky Signed-off-by: Luben Tuikov Reviewed-by: Luben T

[PATCH 11/40] drm/amdgpu: only set restart on first cmd of the smu i2c transaction

From: Alex Deucher Not sure how the firmware interprets these. Signed-off-by: Alex Deucher Reviewed-by: Luben Tuikov --- drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 2 +- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 2 +- drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_ci

[PATCH 14/40] drm/amdgpu: Drop i > 0 restriction for issuing RESTART

From: Andrey Grodzovsky Cc: Jean Delvare Cc: Alexander Deucher Cc: Andrey Grodzovsky Cc: Lijo Lazar Cc: Stanley Yang Cc: Hawking Zhang Signed-off-by: Andrey Grodzovsky Signed-off-by: Luben Tuikov Reviewed-by: Luben Tuikov --- drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 2 +

[PATCH 18/40] drm/amdgpu: Fix Vega20 I2C to be agnostic (v2)

Teach Vega20 I2C to be agnostic. Allow addressing different devices while the master holds the bus. Set STOP as per the controller's specification. v2: Qualify generating ReSTART before the 1st byte of the message, when set by the caller, as those functions are separated, as caught by

[PATCH 09/40] drm/amdgpu: add I2C_CLASS_HWMON to SMU i2c buses

From: Alex Deucher Not sure that this really matters that much, but these could have various other hwmon chips on them. Signed-off-by: Alex Deucher Reviewed-by: Luben Tuikov --- drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 2 +- drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

[PATCH 00/40] I2C fixes

I2C fixes from various people. Some RAS touch-ups too. A rebased tree can also be found here: https://gitlab.freedesktop.org/ltuikov/linux/-/commits/i2c-rework-luben Aaron Rice (1): drm/amdgpu: rework smu11 i2c for generic operation Alex Deucher (10): drm/amdgpu: add a mutex for the smu11 i

[PATCH 10/40] drm/amdgpu: rework smu11 i2c for generic operation

From: Aaron Rice Handle things besides EEPROMS. Signed-off-by: Aaron Rice Signed-off-by: Alex Deucher Reviewed-by: Luben Tuikov --- drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 47 +- 1 file changed, 9 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgp

[PATCH 21/40] drm/amdgpu: I2C EEPROM full memory addressing

* "eeprom_addr" is now 32-bit wide. * Remove "slave_addr" from the I2C EEPROM driver interface. The I2C EEPROM Device Type Identifier is fixed at 1010b, and the rest of the bits of the Device Address Byte/Device Select Code, are memory address bits, where the first three of those bits are

[PATCH 06/40] drm/amdgpu/ras: switch ras eeprom handling to use generic helper

From: Alex Deucher Use the new helper rather than doing i2c transfers directly. Signed-off-by: Alex Deucher Reviewed-by: Luben Tuikov --- .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 86 ++- 1 file changed, 28 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/amd

[PATCH 13/40] dmr/amdgpu: Add RESTART handling also to smu_v11_0_i2c (VG20)

From: Andrey Grodzovsky Also generilize the code to accept and translate to HW bits any I2C relvent flags both for read and write. Cc: Jean Delvare Cc: Alexander Deucher Cc: Andrey Grodzovsky Cc: Lijo Lazar Cc: Stanley Yang Cc: Hawking Zhang Signed-off-by: Andrey Grodzovsky Signed-off-by:

[PATCH 20/40] drm/amdgpu: EEPROM respects I2C quirks

Consult the i2c_adapter.quirks table for the maximum read/write data length per bus transaction. Do not exceed this transaction limit. Cc: Jean Delvare Cc: Alexander Deucher Cc: Andrey Grodzovsky Cc: Lijo Lazar Cc: Stanley Yang Cc: Hawking Zhang Signed-off-by: Luben Tuikov --- drivers/gpu/

[PATCH 26/40] drm/amdgpu: Rename misspelled function

Instead of fixing the spelling in amdgpu_ras_eeprom_process_recods(), rename it to, amdgpu_ras_eeprom_xfer(), to look similar to other I2C and protocol transfer (read/write) functions. Also to keep the column span to within reason by using a shorter name. Change the "num" function parameter f

[PATCH 02/40] drm/amdgpu/pm: rework i2c xfers on sienna cichlid (v3)

From: Alex Deucher Make it generic so we can support more than just EEPROMs. v2: fix restart handling between transactions. v3: handle 7 to 8 bit addr conversion Signed-off-by: Alex Deucher Reviewed-by: Luben Tuikov --- .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 229 +-

[PATCH 03/40] drm/amdgpu/pm: rework i2c xfers on arcturus (v3)

From: Alex Deucher Make it generic so we can support more than just EEPROMs. v2: fix restart handling between transactions. v3: handle 7 to 8 bit addr conversion Signed-off-by: Alex Deucher Reviewed-by: Luben Tuikov --- .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 229 +-

[PATCH 22/40] drm/amdgpu: RAS and FRU now use 19-bit I2C address

Convert RAS and FRU code to use the 19-bit I2C memory address and remove all "slave_addr", as this is now absolved into the 19-bit address. Cc: Jean Delvare Cc: John Clements Cc: Alexander Deucher Cc: Andrey Grodzovsky Cc: Lijo Lazar Cc: Stanley Yang Cc: Hawking Zhang Signed-off-by: Luben T

[PATCH 08/40] drm/amdgpu: i2c subsystem uses 7 bit addresses

From: Alex Deucher Convert from 8 bit to 7 bit. Signed-off-by: Alex Deucher Reviewed-by: Luben Tuikov --- drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 10 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/driv

[PATCH 29/40] drm/amd/pm: Extend the I2C quirk table

Extend the I2C quirk table for SMU access controlled I2C adapters. Let the kernel I2C layer check that the messages all have the same address, and that their combined size doesn't exceed the maximum size of a SMU software I2C request. Suggested-by: Jean Delvare Cc: Jean Delvare Cc: Alexander Deu

[PATCH 05/40] drm/amdgpu: add new helper for handling EEPROM i2c transfers

From: Alex Deucher Encapsulates the i2c protocol handling so other parts of the driver can just tell it the offset and size of data to write. Signed-off-by: Alex Deucher Reviewed-by: Luben Tuikov --- drivers/gpu/drm/amd/amdgpu/Makefile| 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.

[PATCH 04/40] drm/amdgpu/pm: add smu i2c implementation for navi1x (v3)

From: Alex Deucher And handle more than just EEPROMs. v2: fix restart handling between transactions. v3: handle 7 to 8 bit addr conversion Signed-off-by: Alex Deucher Reviewed-by: Luben Tuikov --- .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 116 ++ 1 file changed, 116 ins

[PATCH 01/40] drm/amdgpu: add a mutex for the smu11 i2c bus (v2)

From: Alex Deucher So we lock software as well as hardware access to the bus. v2: fix mutex handling. Signed-off-by: Alex Deucher Reviewed-by: Luben Tuikov --- drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 19 +-- drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h| 1 + 2 files chan

[PATCH 19/40] drm/amdgpu: Fixes to the AMDGPU EEPROM driver

* When reading from the EEPROM device, there is no device limitation on the number of bytes read--they're simply sequenced out. Thus, read the whole data requested in one go. * When writing to the EEPROM device, there is a 256-byte page limit to write to before having to generate a STOP

[PATCH 15/40] drm/amdgpu: Send STOP for the last byte of msg only

From: Andrey Grodzovsky Let's just ignore the I2C_M_STOP hint from upper layer for SMU I2C code as there is no clean mapping between single per I2C message STOP flag at the kernel I2C layer and the SMU, per each byte STOP flag. We will just by default set it at the end of the SMU I2C message. Cc

[PATCH 25/40] drm/amdgpu: RAS: EEPROM --> RAS

In amdgpu_ras_eeprom.c--the interface from RAS to EEPROM, rename macros from EEPROM to RAS, to indicate that the quantities and objects are RAS specific, not EEPROM. We can decrease the RAS table, or put it in different offset of EEPROM as needed in the future. Remove EEPROM_ADDRESS_SIZE macro def

[PATCH 28/40] drm/amdgpu: EEPROM: add explicit read and write

Add explicit amdgpu_eeprom_read() and amdgpu_eeprom_write() for clarity. Cc: Jean Delvare Cc: Alexander Deucher Cc: Andrey Grodzovsky Cc: Lijo Lazar Cc: Stanley Yang Cc: Hawking Zhang Signed-off-by: Luben Tuikov --- drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h | 16 driv

[PATCH 37/40] drm/amdgpu: Optimizations to EEPROM RAS table I/O

Read and write the table in one go, then using a separate stage to decode or encode the data and reading/writing the table, as opposed to on the fly, which keeps the I2C bus busy. Use a single read/write to read/write the table or at most two if the number of records we're reading/writing wraps aro

[PATCH 39/40] drm/amdgpu: Fix koops when accessing RAS EEPROM

Debugfs RAS EEPROM files are available when the ASIC supports RAS, and when the debugfs is enabled, an also when "ras_enable" module parameter is set to 0. However in this case, we get a kernel oops when accessing some of the "ras_..." controls in debugfs. The reason for this is that struct amdgpu_

[PATCH 27/40] drm/amdgpu: RAS xfer to read/write

Wrap amdgpu_ras_eeprom_xfer(..., bool write), into amdgpu_ras_eeprom_read() and amdgpu_ras_eeprom_write(), as that makes reading and understanding the code clearer. Cc: Jean Delvare Cc: Alexander Deucher Cc: Andrey Grodzovsky Cc: Lijo Lazar Cc: Stanley Yang Cc: Hawking Zhang Signed-off-by: L

[PATCH 23/40] drm/amdgpu: Fix wrap-around bugs in RAS

Fix the size of the EEPROM from 256000 bytes to 262144 bytes (256 KiB). Fix a couple or wrap around bugs. If a valid value/address is 0 <= addr < size, the inverse of this inequality (barring negative values which make no sense here) is addr >= size. Fix this in the RAS code. Cc: Jean Delvare Cc

[PATCH 24/40] drm/amdgpu: I2C class is HWMON

Set the auto-discoverable class of I2C bus to HWMON. Remove SPD. Cc: Jean Delvare Cc: Alexander Deucher Cc: Andrey Grodzovsky Cc: Lijo Lazar Cc: Stanley Yang Cc: Hawking Zhang Signed-off-by: Luben Tuikov --- drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 2 +- drivers/gpu/drm/am

[PATCH 40/40] drm/amdgpu: Use a single loop

In smu_v11_0_i2c_transmit() use a single loop to transmit bytes, instead of two nested loops. Cc: Alexander Deucher Cc: Andrey Grodzovsky Signed-off-by: Luben Tuikov --- drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 72 ++ 1 file changed, 34 insertions(+), 38 deletions(-) d

[PATCH 35/40] drm/amdgpu: Simplify RAS EEPROM checksum calculations

Rename update_table_header() to write_table_header() as this function is actually writing it to EEPROM. Use kernel types; use u8 to carry around the checksum, in order to take advantage of arithmetic modulo 8-bits (256). Tidy up to 80 columns. When updating the checksum, just recalculate the who

[PATCH 36/40] drm/amdgpu: Use explicit cardinality for clarity

RAS_MAX_RECORD_NUM may mean the maximum record number, as in the maximum house number on your street, or it may mean the maximum number of records, as in the count of records, which is also a number. To make this distinction whether the number is ordinal (index) or cardinal (count), rename this mac

[PATCH 30/40] drm/amd/pm: Simplify managed I2C transfer functions

Now that we have an I2C quirk table for SMU-managed I2C controllers, the I2C core does the checks for us, so we don't need to do them, and so simplify the managed I2C transfer functions. Also, for Arcturus and Navi10, fix setting the command type from "cmd->CmdConfig" to "cmd->Cmd". The latter is

[PATCH 32/40] drm/amdgpu: Return result fix in RAS

The low level EEPROM write method, doesn't return 1, but the number of bytes written. Thus do not compare to 1, instead, compare to greater than 0 for success. Other cleanup: if the lower layers returned -errno, then return that, as opposed to overwriting the error code with one-fits-all -EINVAL.

[PATCH 33/40] drm/amd/pm: Fix a bug in i2c_xfer

"req" is now a pointer , i.e. it is no longer allocated on the stack, thus taking its reference and passing that is a bug. This commit fixes this bug. Cc: Alex Deucher Signed-off-by: Luben Tuikov --- drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 2 +- drivers/gpu/drm/amd/pm/swsmu/s

[PATCH 38/40] drm/amdgpu: RAS EEPROM table is now in debugfs

Add "ras_eeprom_size" file in debugfs, which reports the maximum size allocated to the RAS table in EEROM, as the number of bytes and the number of records it could store. For instance, $cat /sys/kernel/debug/dri/0/ras/ras_eeprom_size 262144 bytes or 10921 records $_ Add "ras_eeprom_table" file i

[PATCH 34/40] drm/amdgpu: Fix amdgpu_ras_eeprom_init()

No need to account for the 2 bytes of EEPROM address--this is now well abstracted away by the fixes the the lower layers. Cc: Andrey Grodzovsky Cc: Alexander Deucher Signed-off-by: Luben Tuikov --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletio

[PATCH 31/40] drm/amdgpu: Fix width of I2C address

The I2C address is kept as a 16-bit quantity in the kernel. The I2C_TAR::I2C_TAR field is 10-bit wide. Fix the width of the I2C address for Vega20 from 8 bits to 16 bits to accommodate the full spectrum of I2C address space. Cc: Jean Delvare Cc: Alexander Deucher Cc: Andrey Grodzovsky Cc: Lijo

[PATCH] drm: display: Remove duplicated argument in dcn31

Fix the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c: 3539:12-42: duplicated argument to && or || ./drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c: 5677:87-123: duplicated argument to && or || Signed-off-by: Wan Jiabing --- .../gp