Wrap amdgpu_ras_eeprom_xfer(..., bool write),
into amdgpu_ras_eeprom_read() and
amdgpu_ras_eeprom_write(), as that makes reading
and understanding the code clearer.
Cc: Jean Delvare <jdelv...@suse.de>
Cc: Alexander Deucher <alexander.deuc...@amd.com>
Cc: Andrey Grodzovsky <andrey.grodzov...@amd.com>
Cc: Lijo Lazar <lijo.la...@amd.com>
Cc: Stanley Yang <stanley.y...@amd.com>
Cc: Hawking Zhang <hawking.zh...@amd.com>
Signed-off-by: Luben Tuikov <luben.tui...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 9 ++++---
.../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 24 +++++++++++++++----
.../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h | 8 ++++---
3 files changed, 28 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index beaa1fee7f71f3..e3ad081eddd40b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1817,10 +1817,9 @@ int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
save_count = data->count - control->num_recs;
/* only new entries are saved */
if (save_count > 0) {
- if (amdgpu_ras_eeprom_xfer(control,
- &data->bps[control->num_recs],
- save_count,
- true)) {
+ if (amdgpu_ras_eeprom_write(control,
+ &data->bps[control->num_recs],
+ save_count)) {
dev_err(adev->dev, "Failed to save EEPROM table data!");
return -EIO;
}
@@ -1850,7 +1849,7 @@ static int amdgpu_ras_load_bad_pages(struct amdgpu_device
*adev)
if (!bps)
return -ENOMEM;
- if (amdgpu_ras_eeprom_xfer(control, bps, control->num_recs, false)) {
+ if (amdgpu_ras_eeprom_read(control, bps, control->num_recs)) {
dev_err(adev->dev, "Failed to load EEPROM table records!");
ret = -EIO;
goto out;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index 9e3fbc44b4bc4a..550a31953d2da1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
@@ -432,9 +432,9 @@ bool amdgpu_ras_eeprom_check_err_threshold(struct
amdgpu_device *adev)
return false;
}
-int amdgpu_ras_eeprom_xfer(struct amdgpu_ras_eeprom_control *control,
- struct eeprom_table_record *records,
- const u32 num, bool write)
+static int amdgpu_ras_eeprom_xfer(struct amdgpu_ras_eeprom_control *control,
+ struct eeprom_table_record *records,
+ const u32 num, bool write)
{
int i, ret = 0;
unsigned char *buffs, *buff;
@@ -554,6 +554,20 @@ int amdgpu_ras_eeprom_xfer(struct
amdgpu_ras_eeprom_control *control,
return ret == num ? 0 : -EIO;
}
+int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
+ struct eeprom_table_record *records,
+ const u32 num)
+{
+ return amdgpu_ras_eeprom_xfer(control, records, num, false);
+}
+
+int amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control,
+ struct eeprom_table_record *records,
+ const u32 num)
+{
+ return amdgpu_ras_eeprom_xfer(control, records, num, true);
+}
+
inline uint32_t amdgpu_ras_eeprom_get_record_max_length(void)
{
return RAS_MAX_RECORD_NUM;
@@ -574,13 +588,13 @@ void amdgpu_ras_eeprom_test(struct
amdgpu_ras_eeprom_control *control)
recs[i].retired_page = i;
}
- if (!amdgpu_ras_eeprom_xfer(control, recs, 1, true)) {
+ if (!amdgpu_ras_eeprom_write(control, recs, 1)) {
memset(recs, 0, sizeof(*recs) * 1);
control->next_addr = RAS_RECORD_START;
- if (!amdgpu_ras_eeprom_xfer(control, recs, 1, false)) {
+ if (!amdgpu_ras_eeprom_read(control, recs)) {
for (i = 0; i < 1; i++)
DRM_INFO("rec.address :0x%llx, rec.retired_page
:%llu",
recs[i].address, recs[i].retired_page);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
index 6a1bd527bce57a..fa9c509a8e2f2b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
@@ -82,9 +82,11 @@ int amdgpu_ras_eeprom_reset_table(struct
amdgpu_ras_eeprom_control *control);
bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev);
-int amdgpu_ras_eeprom_xfer(struct amdgpu_ras_eeprom_control *control,
- struct eeprom_table_record *records,
- const u32 num, bool write);
+int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
+ struct eeprom_table_record *records, const u32 num);
+
+int amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control,
+ struct eeprom_table_record *records, const u32 num);
inline uint32_t amdgpu_ras_eeprom_get_record_max_length(void);
--
2.32.0
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