From: Roman Li
[Why]
htmldocs build warning: "Function parameter or struct member 'fused_io'
not described in 'amdgpu_display_manager'".
[How]
Add missing description.
Fixes: af632d3f59e6 ("drm/amd/display: HDCP Locality check using DMUB Fused IO")
Reported-by: Stephen Rothwell
Signed-off-by:
From: Mario Limonciello
[Why]
dev_*() messages don't show that they are from a driver in drm
subsystem.
[How]
Change all dev_*() messages to drm_*() messages.
Reviewed-by: Alex Hung
Signed-off-by: Mario Limonciello
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.
From: Mario Limonciello
[Why]
When BIOS includes a lot of custom brightness data points, walking
the entire list can be time consuming. This is most noticed when
dragging a power slider. The "higher" values are "slower" to drag
around.
[How]
Move custom brightness calculation loop into a stati
From: Kevin Gao
[Why] DCN301 needs specific functionality
[How] Add it
Reviewed-by: Aurabindo Pillai
Reviewed-by: Agustin Gutierrez
Signed-off-by: Kevin Gao
Signed-off-by: Roman Li
---
.../display/dc/hubbub/dcn301/dcn301_hubbub.c | 34 ++-
.../display/dc/hubbub/dcn301/dcn30
From: Kevin Gao
[Why]
Due to very small clock register delta between DCN35 and DCN351, clock
spread is being checked on the wrong register for DCN351, causing the
display driver to believe that DPREFCLK downspread to be disabled when
in some stacks it is enabled. This causes the clock values for
From: Mario Limonciello
[Why]
HP Probook 445 and 465 has DP0 and DP1 swapped.
[How]
Add HP Probook 445 and 465 to DP0/DP1 swap quirk list.
Cc: sta...@vger.kernel.org
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3995
Reviewed-by: Alex Hung
Signed-off-by: Mario Limonciello
Signed-off-
From: Sherry Wang
[Why&How]
Fix the confusing entry/exit message name for IPS2
Reviewed-by: Duncan Ma
Signed-off-by: Sherry Wang
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/driv
From: Taimur Hassan
Summary:
* Add DCN301 specific hubbub init function
* Optimize custom brightness curve
* Correct SSC enable detection for DCN351
* Turn off eDP lcdvdd and backlight if not required
* Use DMUB Fused IO interface for HDCP
* Extend eDP-on-DP1 quirk list
Reviewed-by: Zaeem Moham
From: Ausef Yousof
[why&how]
It is possible for an update to acquire otg lock and begin programming
while the previous update has not completed and its values have not
latched. The correct way to go about this is to wait until the vupdate
pulses so we can be sure that previous updates have latche
From: Taimur Hassan
Aligning dmub_cmd header with dmu firmware release 0.1.5.0
Signed-off-by: Taimur Hassan
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc
From: Dillon Varone
This reverts commit 3ad2d94de0c72e31105cb8e607e7ca19f579bf4b.
Reason for revert: it causes stuttering in some usecases.
Reviewed-by: Aric Cyr
Signed-off-by: Dillon Varone
Signed-off-by: Roman Li
---
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 44 ---
From: Mario Limonciello
[Why]
A variety of the 3DLUT handling functions check
`debug.enable_mem_low_power.bits.cm` both in the caller and function.
This is unnecessary overhead.
[How]
For each of them reduce to just checking just in caller or function.
Reviewed-by: Alex Hung
Signed-off-by: Mar
From: Mario Limonciello
[Why]
HP Elitebook 645 has DP0 and DP1 swapped.
[How]
Add HP Elitebook 645 to DP0/DP1 swap quirk list.
Cc: sta...@vger.kernel.org
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3701
Reviewed-by: Alex Hung
Signed-off-by: Mario Limonciello
Signed-off-by: Roman Li
From: Ausef Yousof
fix was previously in 25.20 but was reverted out as it was accompanied
by other changes that caused regression.
[why&how]
Disabling dtb as the dto src during dpms off relies on in the same
instance being able to also alter the dto src bit to dpref (or not dtb
in general), but
From: Dominik Kaszewski
[Why]
HDCP locality check has strict timing requirements, currently broken
due to reliance on msleep which does not guarantee accuracy.
The PR moves the write-poll-read sequence into DMUB using new generic
Fused IO interface, where the timing accuracy is greatly improved.
From: Charlene Liu
[why]
A+N configuration, eDP on A-APU is off, extended display active.
Resume from s4, eDP's backlight is still on.
[how]
Turn off inactive eDP backlight and lcdvdd.
Reviewed-by: Charlene Liu
Reviewed-by: Aric Cyr
Signed-off-by: Charlene Liu
Signed-off-by: Jing Zhou
Signe
From: Mario Limonciello
[Why]
PSR support could vary from the panels connected to one GPU versus
another.
[How]
Move PSR support message into amdgpu_dm which has the scope of the
GPU and use that information.
Reviewed-by: Alex Hung
Signed-off-by: Mario Limonciello
Signed-off-by: Roman Li
---
From: Roman Li
Display Core version 3.2.328 summary:
* Add DCN301 specific hubbub init function
* Optimize custom brightness curve
* Correct SSC enable detection for DCN351
* Turn off eDP lcdvdd and backlight if not required
* Use DMUB Fused IO interface for HDCP
* Extend eDP-on-DP1 quirk list
From: Rodrigo Siqueira
Introduce the DCC and Tiling reset callback to all DCN versions that can
call it.
Reviewed-by: Alvin Lee
Signed-off-by: Rodrigo Siqueira
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/core/dc_surface.c| 13 ++---
.../gpu/drm/amd/display/dc/hwss/
From: Rodrigo Siqueira
This commit introduces a function helper for resetting DCN/DCE DCC and
tiling. Those functions are generic for their respective DCN/DCE, so
they were added to the oldest version of each architecture.
Reviewed-by: Alvin Lee
Signed-off-by: Rodrigo Siqueira
Signed-off-by: R
From: Nicholas Kazlauskas
[Why]
We should never apply a minimum dispclk value while in prepare_bandwidth
or while displays are active. This is always an optimization for when
all displays are disabled.
[How]
Defer dispclk optimization until safe_to_lower = true and display_count
reaches 0.
Sinc
From: Oleh Kuzhylnyi
[Why]
The informative structure needs to be extended by the total number of DPPs
required per each active plane.
The new informative field is going to be used as a statistical indicator.
[How]
The dml2_core_calcs_get_informative() routine must count a total number of DPPs.
From: Rodrigo Siqueira
Rename dc_plane_force_update_for_panic to
dc_plane_force_dcc_and_tiling_disable to describe the function operation
in the name. Also, this function might be used in other contexts, and a
more generic name can be helpful for this purpose.
Reviewed-by: Alvin Lee
Signed-off-
From: George Shen
[Why]
The latest DP spec requires the DP TX to read DPCD Fh through F0009h
when detecting LTTPR capabilities for the first time.
[How]
Update LTTPR cap retrieval to read up to F0009h (two more bytes than the
previous F0007h), and store the LTTPR ALPM capabilities.
Reviewed
From: Taimur Hassan
Summary:
* Add support for disconnected eDP streams
* Add log for MALL entry on DCN32x
* Add DCC/Tiling reset helper for DCN and DCE
* Guard against setting dispclk low when active
* Other minor fixes
Reviewed-by: Aurabindo Pillai
Signed-off-by: Taimur Hassan
Signed-off-by
From: Harry VanZyllDeJong
[Why]
eDP may not be connected to the GPU on driver start causing
fail enumeration.
[How]
Move the virtual signal type check before the eDP connector
signal check.
Reviewed-by: Wenjing Liu
Signed-off-by: Harry VanZyllDeJong
Signed-off-by: Roman Li
---
.../drm/amd/d
From: Aurabindo Pillai
[Why&How]
Add a dyndbg log entry to check whether the driver requested scanout
from MALL cache to PMFW via DMCUB
Reviewed-by: Zaeem Mohamed
Reviewed-by: Roman Li
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 2 ++
1 file
From: Peichen Huang
[WHY]
In current HPO DP2 implementation, driver would enable/disable DIG
encoder when configuring HPO DP2. Therefore, usb4 dp tunnelling should
not use the DIG encoder if the corresponded phy is used by a HPO DP2
stream.
[HOW]
A DP2 stream is treated as a dig stream.
Reviewe
From: Alex Hung
[WHAT & HOW]
Add a message so users know the stream will be used for seamless boot.
Reviewed-by: Mario Limonciello
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Alex Hung
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4 +++-
1 file changed, 3
From: Ilya Bakoulin
[Why/How]
Need to add support for full-range quantization for YCbCr in BT2020
color space.
Reviewed-by: Krunoslav Kovac
Signed-off-by: Ilya Bakoulin
Signed-off-by: Roman Li
Tested-by: Robert Mader
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++---
From: Harry Wentland
Don't try to operate on a drm_wb_connector as an amdgpu_dm_connector.
While dereferencing aconnector->base will "work" it's wrong and
might lead to unknown bad things. Just... don't.
Reviewed-by: Alex Hung
Signed-off-by: Harry Wentland
Signed-off-by: Roman Li
---
.../gpu
From: Rodrigo Siqueira
Introduce the DCC and Tiling reset callback to all DCE versions that can
call it.
Reviewed-by: Alvin Lee
Signed-off-by: Rodrigo Siqueira
Signed-off-by: Roman Li
---
.../gpu/drm/amd/display/dc/core/dc_surface.c | 18 ++
.../amd/display/dc/dce60/dce60_h
From: Roman Li
Summary:
* Add support for disconnected eDP streams
* Add log for MALL entry on DCN32x
* Add DCC/Tiling reset helper for DCN and DCE
* Guard against setting dispclk low when active
* Other minor fixes
Cc: Daniel Wheeler
Alex Hung (1):
drm/amd/display: Print seamless boot mess
From: Ovidiu Bunea
[why & how]
By default, DCN HW is in idle optimized state which does not allow access
to PHY registers. If BIOS powers up the DCN, it is fine because they will
power up everything. Only exit idle optimized state when not taking control
from VBIOS.
Fixes: 53f82eb16293 ("Revert
From: Leo Zeng
This reverts commit aaa44ed6cd8af2089d2bf6a2e66a0436fef9791f.
Reason to revert: idle power regression found in testing.
Reviewed-by: Dillon Varone
Signed-off-by: Leo Zeng
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 1 -
1 file changed, 1
From: Natanel Roizenman
[Why]
Comparisons were made between unsigned char and unsigned int.
[How]
Corrected by changing variable types.
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Natanel Roizenman
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
.../dml2/dml21/src/dml2_dpmm/dml2_
From: Iswara Nagulendran
[WHY]
There is no way to distinguish
the static backlight control type
being used and the VABC support
without the use of a debugger or
reading DPCD registers.
[HOW]
Add Visual Confirm support
for VESA Aux-based Backlight Control.
Reviewed-by: Harry Vanzylldejong
Signe
From: George Shen
[Why]
Current DCN32 calculation doesn't consider RGB 6bpc for the DP case.
This results in an invalid output bpp being calculated when DSC is not
enabled in the configuration, failing the mode validation.
[How]
Add special case to handle 6bpc RGB in the output bpp calculation.
From: Karthi Kandasamy
[WHY]
The `dc_tiling_info` union previously did not have a field to
specify the active GFX format, assuming only one format would
be used per DCN version. from DCN4+, support for switching
between different GFX formats is introduced, requiring a way
to track which format is
From: Martin Leung
This version brings along the following:
- Add Interface to Dump DSC Caps from dm
- Add DP required HBlank size calc to link interface
- Add 6bpc RGB case for dcn32 output bpp calculations
- Add VC for VESA Aux Backlight Control
- Add support for setting multiple CRC windows in
From: Samson Tam
[Why & How]
Use helper functions for checking formats
Apply cositing offset in rotation case
Reviewed-by: Navid Assadian
Signed-off-by: Samson Tam
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 88 ++---
1
From: Wayne Lin
[Why & How]
We already extend our dm, dc and dmub to support setting of multiple CRC
instances, now extend the capability to return back the ROI/CRC pair result
from psp by specifying activated ROI instances.
Reviewed-by: HaoPing Liu
Signed-off-by: Wayne Lin
Signed-off-by: Roma
From: Samson Tam
[Why & How]
init_adj offset is applied when cosited not interstitial
Adjust cositing offset in SPL
Reviewed-by: Jun Lei
Signed-off-by: Samson Tam
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
.../amd/display/dc/resource/dcn401/dcn401_resource.c | 2 +-
drivers/gpu
From: Roman Li
[Why]
Wrapper functions for dcn_bw_ceil2() and dcn_bw_floor2()
should check for granularity is non zero to avoid assert and
divide-by-zero error in dcn_bw_ functions.
[How]
Add check for granularity 0.
Cc: Mario Limonciello
Cc: sta...@vger.kernel.org
Reviewed-by: Alvin Lee
Sign
From: Karthi Kandasamy
[Why]
To ensure DML validation receives the correct tiling information,
such as swizzle mode or array mode, based on the active GFX format
[How]
- For new GFX format passed swizzle_mode to DML.
- For legacy GFX format passed array_mode to DML.
- Dynamically determined the
From: "Dennis.Chan"
[why]
Add new Visual confirm color for Replay Low Hz.
Reviewed-by: Robin Chen
Signed-off-by: Dennis.Chan
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 11 ++--
.../dc/link/protocols/link_dp_irq_handler.c | 2 +
.
From: Fangzhi Zuo
No common dsc params found between encoder and decoder is one
of the reason that could prevent dsc from properly enabled.
Dump the params to a specific timing to help locate possible
invalid dsc params in either encoder or decoder side.
Reviewed-by: Aurabindo Pillai
Signed-of
From: George Shen
[Why]
Certain small HBlank timings may not have a large enough HBlank to
support audio when low bpp DSC is enabled. HBlank expansion by the
source can solve this problem, but requires the branch/sink to support
HBlank reduction.
[How]
Update DPMS sequence to call DM to perform
From: Tom Chung
[Why]
Replay and PSR will cause some video corruption while VRR is enabled.
[How]
1. Disable the Replay and PSR while VRR is enabled.
2. Change the amdgpu_dm_crtc_vrr_active() parameter to const.
Because the function will only read data from dm_crtc_state.
Reviewed-by: Sun pe
From: Aric Cyr
[why]
Updating the cursor enablement register can be a slow operation and accumulates
when high polling rate cursors cause frequent updates asynchronously to the
cursor position.
[how]
Since the cursor enable bit is cached there is no need to update the
enablement register if ther
From: Brandon Syu
[why]
initialize the power state for dc use,
but dc_set_power_state it not called at D3.
It would cause can't recognize last power state
[how]
remove initialize the power state for dc use, it is not necessary.
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Brandon Syu
Signe
From: Tom Chung
[Why]
The enum DC_PSR_VERSION_SU_1 of psr_version is 1 and
DC_PSR_VERSION_UNSUPPORTED is 0x.
The original code may has chance trigger the amdgpu_dm_psr_enable()
while psr version is set to DC_PSR_VERSION_UNSUPPORTED.
[How]
Modify the condition to psr->psr_version == DC_P
From: Peichen Huang
[WHY]
We like to have pretrain for dpia link so that dp and dp tunneling
have aligned behavior. The Main difficult for dpia pretrain is that
encoder can not get corresponded dpia port when link detection
in current implementation.
[HOW]
1. create enable/disable dpia output fu
From: Wayne Lin
[Why & How]
We actually have the capability to calculate independent CRC for 2 crc window
at the same time. Extend dm with the capability by having array to
configure/maintain multiple crc windows. Add the flexibility but use 1st CRC
instance only for now. Can change to use the 2n
From: Aurabindo Pillai
MAX/MIN macros maybe defined already, hence add a guard around them to
prevent errors that complain about redefinition like:
drivers/gpu/drm/amd/amdgpu/../dal-dev/modules/hdcp/hdcp_ddc.c:31: error: "MIN"
redefined [-Werror]
31 | #define MIN(a, b) ((a) < (b) ? (a) : (b)
From: Wayne Lin
[Why & How]
Since now we can set multiple crc windows for secure display, add a new input
parameter for dc_stream_get_crc to indicate to fetch crc from which crc
engine.
Reviewed-by: HaoPing Liu
Signed-off-by: Wayne Lin
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
.
From: Wayne Lin
[Why & How]
Have to support multiple CRC windows setting to dmub. Add new dmub forward
functions for supporting/forwarding multiple crc windows setting to dmub.
Reviewed-by: HaoPing Liu
Signed-off-by: Wayne Lin
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
drivers/gp
From: Roman Li
- Improvements for DP, Replay/PSR, DML, SPL, DCN32, DCN35, DCN401
- Extended logging for DSC, VABC and stream crc
- Optimization for cursor position updates
Aric Cyr (1):
drm/amd/display: Optimize cursor position updates
Aurabindo Pillai (1):
drm/amd/display: Add guards ar
From: George Shen
[Why]
For DP HBlank expansion/reduction, the HBlank parameters of the original
EDID timing needs to be notified to the sink in order for the timing to
be reduced back to the original HBlank size.
[How]
Add parameter in dc_crtc_timing to track the increased HBlank.
Reviewed-by:
From: Dillon Varone
[WHY&HOW]
- Remove legacy update clocks sequence
- FCLK P-State allow message is not required
Reviewed-by: Alvin Lee
Signed-off-by: Dillon Varone
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 240 ++
From: George Shen
[Why]
Some features, such as HBlank expansion/reduction, needs to know how
much HBlank is required to support basic audio.
[How]
Add interface to link to calculate required HBlank size for a given
link + timing combination to support basic audio (i.e. 2-channel 48KHz).
Reviewe
From: George Shen
[Why]
DPCD register RECEIVE_PORT0_CAP contains HBlank expansion/reduction
capabilities of a DP device. These capabilities are required to enable
HBlank expansion/reduction logic.
[How]
Read raw RECEIVE_PORT0_CAP register values and store parsed fields.
Reviewed-by: Wenjing Liu
From: Yihan Zhu
[WHY & HOW]
Driver disable will deallocate framebuffer to reset IPS state, this will cause
IPS start with
INIT state to blindly power gate ONO region to break power sequence. All the
gating blocks
should be powered up when releasing hw to ensure all the power optimizations
are
From: Yihan Zhu
[WHY & HOW]
No check for HUBP/DPP power gating when DSC instance is still running. Avoid
HUBP/DPP to
power gate when corresponding DSC block is still running in the power gating
calculation.
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: Duncan Ma
Signed-off-by: Yihan Zhu
Sig
From: Samson Tam
[Why & How]
Disable dynamic ODM when sharpness is enabled
Reviewed-by: Alvin Lee
Signed-off-by: Samson Tam
Signed-off-by: Roman Li
---
.../gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git
a/drivers/gpu/drm/amd/di
From: Joshua Aberback
[Why]
We want to clean up unnecessary asserts, one of which is an assert in
resource_is_pipe_type that fires if a pipe has no stream and still has
pointers to other pipes ("dangling state"). This gets hit because pipes
are not properly cleaned up in reset_back_end_for_pipe.
From: Leo Chen
[Why]
A race condition occurs between cursor movement and vertical interrupt control
thread from OS, with both threads trying to exit IPS2.
Vertical interrupt control thread clears the prev driver allow signal while not
fully
finishing the IPS2 exit process.
[How]
We want to dete
From: Samson Tam
[Why]
Pass in sharpening policy through plane state from control side
[How]
Add sharpener support through dc_caps.
Add sharpen policy to plane state and move to spl_input.
Pass sharpen policy from plane state to SPL.
Reviewed-by: Aric Cyr
Signed-off-by: Samson Tam
Signed-off-
From: Alex Hung
[WHAT]
The function core_link_read_dpcd returns status which is not used at
all, making them useless assignments.
[HOW]
Print error messages if core_link_read_dpcd does not return DC_OK.
This fixes 2 UNUSED_VALUE issues reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Signe
From: Aric Cyr
- Add sharpening policy to plane state
- Clear pipe pointers on pipe reset
- Resolve correct MALL size for dcn401
- Read Sink emission rate capability
- IPX fixes
- Coverity fixes
Reviewed-by: Roman Li
Signed-off-by: Aric Cyr
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/dis
From: Ilya Bakoulin
[Why]
There is a known HW bug that causes the internal 3DLUT fetch signal to
be lost at VREADY, regardless of whether the OTG lock is being held or
not. A workaround is necessary to make sure that this internal signal
stays up after OTG unlock.
[How]
Set the 3DLUT_ENABLE bit
From: Robin Chen
[WHY]
To get sink emission rate information for future
supported refresh rate calculation.
Reviewed-by: ChunTao Tso
Signed-off-by: Robin Chen
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 3 ++-
.../dc/link/protocols/link_dp_capability.c|
From: Roman Li
[Why]
Currently idle worker thread that checks for HPD while system is in IPS2
only supports headless and static screen use-cases.
In other display-off scenarios hotplug may not work.
[How]
For display-off only allow idle optimization when no display is connected.
Reviewed-by: Su
From: "Leo (Hanghong) Ma"
[Why && How]
Previous change for Coverity has caused regression on visual confirm
so fix it by reverting the part that affects visual confirm.
Reviewed-by: Chris Park
Signed-off-by: Leo (Hanghong) Ma
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/dc_dmub
From: Alex Hung
[WHAT & HOW]
Print error messages when programming shaper lut or 3dlut fails.
This fixes 5 UNUSED_VALUE issues reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Alex Hung
Signed-off-by: Roman Li
---
.../gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 7 ++
From: Dillon Varone
[WHY]
Code for dcn401 to calculate available MALL size for display was shared
with dcn32 and did not provide the correct result for all ASICs.
[HOW]
Add dcn401 specific function to properly calculate the available MALL
for display.
Reviewed-by: Chris Park
Signed-off-by: Dil
From: Roman Li
[Why]
Idle worker thread waits HPD_DETECTION_TIME for HPD processing complete.
Some displays require longer time for that.
[How]
Increase HPD_DETECTION_TIME to 100ms.
Reviewed-by: Sun peng Li
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c |
From: Roman Li
This DC v.3.2.305 patchset brings improvements in multiple areas. In summary,
we have:
- Add sharpening policy to plane state
- Clear pipe pointers on pipe reset
- Resolve correct MALL size for dcn401
- Read Sink emission rate capability
- IPX fixes
- Coverity fixes
Cc: Daniel
From: Alex Hung
[WHAT & HOW]
drm_dp_dpcd_write() returns negative error on failure and thus returned
values need to be checked.
This fixes 3 UNUSED_VALUE issues reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Alex Hung
Signed-off-by: Roman Li
---
.../amd/display/amdgpu_dm
From: Alex Hung
[WHAT & HOW]
dpcd_get_tunneling_device_data calls core_link_read_dpcd which can
fail. The status from core_link_read_dpcd should be checked and error
messages is printed in case of failures.
This fixes 1 UNUSED_VALUE issue reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Sig
From: Alex Hung
[WHAT & HOW]
"split_pipe" are assigned to test_pipe and then immediately are updated
to other values. The same also applies to "status" as well.
Similarly, "id", "dwb" and "unused_dpps" are assigned but the functions
immediately return, and thus they have no effects.
As a result
From: Martin Leung
- Various DML 2.1 fixes
- Fix MST Regression
- Fix module unload
- Fix construct_phy with MXM connector
- Support UHBR10 link rate on eDP
- Revert updated DCCG wrappers
Signed-off-by: Martin Leung
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 fil
From: Fangzhi Zuo
A typo is fixed for "drm/amd/display: Fix MST BW calculation Regression"
Fixes: 4b6564cb120c ("drm/amd/display: Fix MST BW calculation Regression")
Reviewed-by: Roman Li
Signed-off-by: Fangzhi Zuo
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_
From: Austin Zheng
[Why and How]
DML2.1 reintegration for several fixes and updates to the DML
code.
Reviewed-by: Dillon Varone
Signed-off-by: Austin Zheng
Signed-off-by: Roman Li fams2_required =
display_cfg->stage3.fams2_required;
dml2_core_calcs_get_global_fams2_programm
From: Tim Huang
Flexible endpoints use DIGs from available inflexible endpoints,
so only the encoders of inflexible links need to be freed.
Otherwise, a double free issue may occur when unloading the
amdgpu module.
[ 279.190523] RIP: 0010:__slab_free+0x152/0x2f0
[ 279.190577] Call Trace:
[ 27
From: Ilya Bakoulin
[Why/How]
The call to construct_phy will fail in cases where connector type is
MXM, and the dc_link won't be properly created/initialized.
Reviewed-by: Wenjing Liu
Signed-off-by: Ilya Bakoulin
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/link/link_factory.c
From: Michael Strauss
[WHY]
Previous multi-display HPO fix moved where HPO I/O enable/disable is performed.
The codepath now taken to enable/disable HPO I/O is not used for compliance
test automation, meaning that if a compliance box being driven at a DP1 rate
requests retrain at UHBR, HPO I/O wi
From: Nicholas Susanto
Removing redundant condition.
Reviewed-by: Hansen Dsouza
Signed-off-by: Nicholas Susanto
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
From: Michael Strauss
[WHY]
eDP 2.0 is introducing support for UHBR link rates, however current eDP ILR
link optimization does not account for UHBR capabilities.
Either UHBR capabilities will be provided via the same 128b/132b rate DPCD caps
that are currently used on DP2.1, or Table 4-13 may be
From: Nicholas Susanto
[Why]
Causes hard hangs when resuming after display off on extended/duplicate
modes
[How]
Set the min dispclk to 50Mhz for DCN35
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Nicholas Susanto
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35
From: Nevenko Stupar
[Why & How]
DCN4 Cursor has separate degamma block and should always
do Cursor degamma for Cursor color modes.
Reviewed-by: Chris Park
Signed-off-by: Nevenko Stupar
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c | 5 ++---
1 file ch
From: Aurabindo Pillai
when removing the amdgpu module and reinserting it, a call trace is
triggered:
[ 334.230602] RIP: 0010:hubbub2_get_dchub_ref_freq+0xbb/0xe0 [amdgpu]
[ 334.230807] Code: 25 28 00 00 00 75 3c 48 8d 65 f0 5b 41 5c 5d 31 c0 31 d2
31 c9 31 f6 31 ff 45 31 c0 45 31 c9 45 31 d2
From: Sung Joon Kim
[why]
Supporting UHBR10 link rate on eDP leverages
the existing DP2.0 code but need to add some small
adjustments in code.
[how]
Acknowledge the given DPCD caps for UHBR10
link rate support and allow DP2.0 programming
sequence and link training for eDP.
Reviewed-by: Wenjing
From: Hansen Dsouza
[Why]
Revert updated DCCG wrappers due to regression
[How]
This reverts commit 28b190df7a8f43b39e13886d744742a74a2c162d.
Reviewed-by: Chris Park
Signed-off-by: Hansen Dsouza
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 4 ++--
1 fi
From: Roman Li
Cc: Daniel Wheeler
Aurabindo Pillai (1):
drm/amd/display: remove an extraneous call for checking dchub clock
Austin Zheng (1):
drm/amd/display: DML2.1 Reintegration for Various Fixes
Fangzhi Zuo (1):
drm/amd/display: Fix a typo in revert commit
Hansen Dsouza (1):
Rever
From: Roman Li
[Why]
htmldocs warning:
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h: warning:
Function parameter or struct member 'idle_workqueue' not described in
'amdgpu_display_manager'.
[How]
Add comment section for idle_workqueue with param description.
Reported-by: Stephen Rothwell
From: Roman Li
[Why]
Compilation errors while compiling without CONFIG_DRM_AMD_DC_FP:
"undefined reference to `dc_bandwidth_in_kbps_from_timing'"
[How]
Fix Makefile to move dsc files out of DC_FP guard.
Fixes: 50253f5d9ff4 ("drm/amd/display: Add misc DC changes for DCN401")
Signed-off-by: Roman
From: Aric Cyr
This version pairs with DMUB FW Release 0.0.218.0 for dcn314/315/316,
dcn35/351, dcn401
and brings along the following:
- Fix powerpc compilation
- Fix TBT+TypeC Daisy-chain lightup
- Fix ODM combine setup
- Fix OTC underflow on dcn35
- Fix DVI config for dcn401
- Add ips status
From: Alvin Lee
[Description]
There is a corner case where we're in an ODM config that
has recout.x != 0. In these scenarios we have to take into
account the extra offset in the ODM adjustment for cursor.
Reviewed-by: Aric Cyr
Acked-by: Roman Li
Signed-off-by: Alvin Lee
---
.../drm/amd/displ
From: Roman Li
[Why]
Reset the shared dmub firmware region on dmub hw init to start with
known state.
[How]
Memset the shared region to 0 in dmub_hw_init().
Suggested-by: Nicholas Kazlauskas
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/a
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