From: Natanel Roizenman
[Why]
Comparisons were made between unsigned char and unsigned int.
[How]
Corrected by changing variable types.
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Natanel Roizenman
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
.../dml2/dml21/src/dml2_dpmm/dml2_
From: Iswara Nagulendran
[WHY]
There is no way to distinguish
the static backlight control type
being used and the VABC support
without the use of a debugger or
reading DPCD registers.
[HOW]
Add Visual Confirm support
for VESA Aux-based Backlight Control.
Reviewed-by: Harry Vanzylldejong
Signe
From: George Shen
[Why]
Current DCN32 calculation doesn't consider RGB 6bpc for the DP case.
This results in an invalid output bpp being calculated when DSC is not
enabled in the configuration, failing the mode validation.
[How]
Add special case to handle 6bpc RGB in the output bpp calculation.
From: Karthi Kandasamy
[WHY]
The `dc_tiling_info` union previously did not have a field to
specify the active GFX format, assuming only one format would
be used per DCN version. from DCN4+, support for switching
between different GFX formats is introduced, requiring a way
to track which format is
From: Martin Leung
This version brings along the following:
- Add Interface to Dump DSC Caps from dm
- Add DP required HBlank size calc to link interface
- Add 6bpc RGB case for dcn32 output bpp calculations
- Add VC for VESA Aux Backlight Control
- Add support for setting multiple CRC windows in
From: Samson Tam
[Why & How]
Use helper functions for checking formats
Apply cositing offset in rotation case
Reviewed-by: Navid Assadian
Signed-off-by: Samson Tam
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 88 ++---
1
From: Wayne Lin
[Why & How]
We already extend our dm, dc and dmub to support setting of multiple CRC
instances, now extend the capability to return back the ROI/CRC pair result
from psp by specifying activated ROI instances.
Reviewed-by: HaoPing Liu
Signed-off-by: Wayne Lin
Signed-off-by: Roma
From: Samson Tam
[Why & How]
init_adj offset is applied when cosited not interstitial
Adjust cositing offset in SPL
Reviewed-by: Jun Lei
Signed-off-by: Samson Tam
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
.../amd/display/dc/resource/dcn401/dcn401_resource.c | 2 +-
drivers/gpu
From: Roman Li
[Why]
Wrapper functions for dcn_bw_ceil2() and dcn_bw_floor2()
should check for granularity is non zero to avoid assert and
divide-by-zero error in dcn_bw_ functions.
[How]
Add check for granularity 0.
Cc: Mario Limonciello
Cc: sta...@vger.kernel.org
Reviewed-by: Alvin Lee
Sign
From: Karthi Kandasamy
[Why]
To ensure DML validation receives the correct tiling information,
such as swizzle mode or array mode, based on the active GFX format
[How]
- For new GFX format passed swizzle_mode to DML.
- For legacy GFX format passed array_mode to DML.
- Dynamically determined the
From: "Dennis.Chan"
[why]
Add new Visual confirm color for Replay Low Hz.
Reviewed-by: Robin Chen
Signed-off-by: Dennis.Chan
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 11 ++--
.../dc/link/protocols/link_dp_irq_handler.c | 2 +
.
From: Fangzhi Zuo
No common dsc params found between encoder and decoder is one
of the reason that could prevent dsc from properly enabled.
Dump the params to a specific timing to help locate possible
invalid dsc params in either encoder or decoder side.
Reviewed-by: Aurabindo Pillai
Signed-of
From: George Shen
[Why]
Certain small HBlank timings may not have a large enough HBlank to
support audio when low bpp DSC is enabled. HBlank expansion by the
source can solve this problem, but requires the branch/sink to support
HBlank reduction.
[How]
Update DPMS sequence to call DM to perform
From: Tom Chung
[Why]
Replay and PSR will cause some video corruption while VRR is enabled.
[How]
1. Disable the Replay and PSR while VRR is enabled.
2. Change the amdgpu_dm_crtc_vrr_active() parameter to const.
Because the function will only read data from dm_crtc_state.
Reviewed-by: Sun pe
From: Aric Cyr
[why]
Updating the cursor enablement register can be a slow operation and accumulates
when high polling rate cursors cause frequent updates asynchronously to the
cursor position.
[how]
Since the cursor enable bit is cached there is no need to update the
enablement register if ther
From: Brandon Syu
[why]
initialize the power state for dc use,
but dc_set_power_state it not called at D3.
It would cause can't recognize last power state
[how]
remove initialize the power state for dc use, it is not necessary.
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Brandon Syu
Signe
From: Tom Chung
[Why]
The enum DC_PSR_VERSION_SU_1 of psr_version is 1 and
DC_PSR_VERSION_UNSUPPORTED is 0x.
The original code may has chance trigger the amdgpu_dm_psr_enable()
while psr version is set to DC_PSR_VERSION_UNSUPPORTED.
[How]
Modify the condition to psr->psr_version == DC_P
From: Peichen Huang
[WHY]
We like to have pretrain for dpia link so that dp and dp tunneling
have aligned behavior. The Main difficult for dpia pretrain is that
encoder can not get corresponded dpia port when link detection
in current implementation.
[HOW]
1. create enable/disable dpia output fu
From: Wayne Lin
[Why & How]
We actually have the capability to calculate independent CRC for 2 crc window
at the same time. Extend dm with the capability by having array to
configure/maintain multiple crc windows. Add the flexibility but use 1st CRC
instance only for now. Can change to use the 2n
From: Aurabindo Pillai
MAX/MIN macros maybe defined already, hence add a guard around them to
prevent errors that complain about redefinition like:
drivers/gpu/drm/amd/amdgpu/../dal-dev/modules/hdcp/hdcp_ddc.c:31: error: "MIN"
redefined [-Werror]
31 | #define MIN(a, b) ((a) < (b) ? (a) : (b)
From: Wayne Lin
[Why & How]
Since now we can set multiple crc windows for secure display, add a new input
parameter for dc_stream_get_crc to indicate to fetch crc from which crc
engine.
Reviewed-by: HaoPing Liu
Signed-off-by: Wayne Lin
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
.
From: Wayne Lin
[Why & How]
Have to support multiple CRC windows setting to dmub. Add new dmub forward
functions for supporting/forwarding multiple crc windows setting to dmub.
Reviewed-by: HaoPing Liu
Signed-off-by: Wayne Lin
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
drivers/gp
From: Roman Li
- Improvements for DP, Replay/PSR, DML, SPL, DCN32, DCN35, DCN401
- Extended logging for DSC, VABC and stream crc
- Optimization for cursor position updates
Aric Cyr (1):
drm/amd/display: Optimize cursor position updates
Aurabindo Pillai (1):
drm/amd/display: Add guards ar
From: George Shen
[Why]
For DP HBlank expansion/reduction, the HBlank parameters of the original
EDID timing needs to be notified to the sink in order for the timing to
be reduced back to the original HBlank size.
[How]
Add parameter in dc_crtc_timing to track the increased HBlank.
Reviewed-by:
From: Dillon Varone
[WHY&HOW]
- Remove legacy update clocks sequence
- FCLK P-State allow message is not required
Reviewed-by: Alvin Lee
Signed-off-by: Dillon Varone
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 240 ++
From: George Shen
[Why]
Some features, such as HBlank expansion/reduction, needs to know how
much HBlank is required to support basic audio.
[How]
Add interface to link to calculate required HBlank size for a given
link + timing combination to support basic audio (i.e. 2-channel 48KHz).
Reviewe
From: George Shen
[Why]
DPCD register RECEIVE_PORT0_CAP contains HBlank expansion/reduction
capabilities of a DP device. These capabilities are required to enable
HBlank expansion/reduction logic.
[How]
Read raw RECEIVE_PORT0_CAP register values and store parsed fields.
Reviewed-by: Wenjing Liu
From: Yihan Zhu
[WHY & HOW]
Driver disable will deallocate framebuffer to reset IPS state, this will cause
IPS start with
INIT state to blindly power gate ONO region to break power sequence. All the
gating blocks
should be powered up when releasing hw to ensure all the power optimizations
are
From: Yihan Zhu
[WHY & HOW]
No check for HUBP/DPP power gating when DSC instance is still running. Avoid
HUBP/DPP to
power gate when corresponding DSC block is still running in the power gating
calculation.
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: Duncan Ma
Signed-off-by: Yihan Zhu
Sig
From: Samson Tam
[Why & How]
Disable dynamic ODM when sharpness is enabled
Reviewed-by: Alvin Lee
Signed-off-by: Samson Tam
Signed-off-by: Roman Li
---
.../gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git
a/drivers/gpu/drm/amd/di
From: Joshua Aberback
[Why]
We want to clean up unnecessary asserts, one of which is an assert in
resource_is_pipe_type that fires if a pipe has no stream and still has
pointers to other pipes ("dangling state"). This gets hit because pipes
are not properly cleaned up in reset_back_end_for_pipe.
From: Leo Chen
[Why]
A race condition occurs between cursor movement and vertical interrupt control
thread from OS, with both threads trying to exit IPS2.
Vertical interrupt control thread clears the prev driver allow signal while not
fully
finishing the IPS2 exit process.
[How]
We want to dete
From: Samson Tam
[Why]
Pass in sharpening policy through plane state from control side
[How]
Add sharpener support through dc_caps.
Add sharpen policy to plane state and move to spl_input.
Pass sharpen policy from plane state to SPL.
Reviewed-by: Aric Cyr
Signed-off-by: Samson Tam
Signed-off-
From: Alex Hung
[WHAT]
The function core_link_read_dpcd returns status which is not used at
all, making them useless assignments.
[HOW]
Print error messages if core_link_read_dpcd does not return DC_OK.
This fixes 2 UNUSED_VALUE issues reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Signe
From: Aric Cyr
- Add sharpening policy to plane state
- Clear pipe pointers on pipe reset
- Resolve correct MALL size for dcn401
- Read Sink emission rate capability
- IPX fixes
- Coverity fixes
Reviewed-by: Roman Li
Signed-off-by: Aric Cyr
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/dis
From: Ilya Bakoulin
[Why]
There is a known HW bug that causes the internal 3DLUT fetch signal to
be lost at VREADY, regardless of whether the OTG lock is being held or
not. A workaround is necessary to make sure that this internal signal
stays up after OTG unlock.
[How]
Set the 3DLUT_ENABLE bit
From: Robin Chen
[WHY]
To get sink emission rate information for future
supported refresh rate calculation.
Reviewed-by: ChunTao Tso
Signed-off-by: Robin Chen
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 3 ++-
.../dc/link/protocols/link_dp_capability.c|
From: Roman Li
[Why]
Currently idle worker thread that checks for HPD while system is in IPS2
only supports headless and static screen use-cases.
In other display-off scenarios hotplug may not work.
[How]
For display-off only allow idle optimization when no display is connected.
Reviewed-by: Su
From: "Leo (Hanghong) Ma"
[Why && How]
Previous change for Coverity has caused regression on visual confirm
so fix it by reverting the part that affects visual confirm.
Reviewed-by: Chris Park
Signed-off-by: Leo (Hanghong) Ma
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/dc_dmub
From: Alex Hung
[WHAT & HOW]
Print error messages when programming shaper lut or 3dlut fails.
This fixes 5 UNUSED_VALUE issues reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Alex Hung
Signed-off-by: Roman Li
---
.../gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 7 ++
From: Dillon Varone
[WHY]
Code for dcn401 to calculate available MALL size for display was shared
with dcn32 and did not provide the correct result for all ASICs.
[HOW]
Add dcn401 specific function to properly calculate the available MALL
for display.
Reviewed-by: Chris Park
Signed-off-by: Dil
From: Roman Li
[Why]
Idle worker thread waits HPD_DETECTION_TIME for HPD processing complete.
Some displays require longer time for that.
[How]
Increase HPD_DETECTION_TIME to 100ms.
Reviewed-by: Sun peng Li
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c |
From: Roman Li
This DC v.3.2.305 patchset brings improvements in multiple areas. In summary,
we have:
- Add sharpening policy to plane state
- Clear pipe pointers on pipe reset
- Resolve correct MALL size for dcn401
- Read Sink emission rate capability
- IPX fixes
- Coverity fixes
Cc: Daniel
From: Alex Hung
[WHAT & HOW]
drm_dp_dpcd_write() returns negative error on failure and thus returned
values need to be checked.
This fixes 3 UNUSED_VALUE issues reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Alex Hung
Signed-off-by: Roman Li
---
.../amd/display/amdgpu_dm
From: Alex Hung
[WHAT & HOW]
dpcd_get_tunneling_device_data calls core_link_read_dpcd which can
fail. The status from core_link_read_dpcd should be checked and error
messages is printed in case of failures.
This fixes 1 UNUSED_VALUE issue reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Sig
From: Alex Hung
[WHAT & HOW]
"split_pipe" are assigned to test_pipe and then immediately are updated
to other values. The same also applies to "status" as well.
Similarly, "id", "dwb" and "unused_dpps" are assigned but the functions
immediately return, and thus they have no effects.
As a result
From: Martin Leung
- Various DML 2.1 fixes
- Fix MST Regression
- Fix module unload
- Fix construct_phy with MXM connector
- Support UHBR10 link rate on eDP
- Revert updated DCCG wrappers
Signed-off-by: Martin Leung
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 fil
From: Fangzhi Zuo
A typo is fixed for "drm/amd/display: Fix MST BW calculation Regression"
Fixes: 4b6564cb120c ("drm/amd/display: Fix MST BW calculation Regression")
Reviewed-by: Roman Li
Signed-off-by: Fangzhi Zuo
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_
From: Austin Zheng
[Why and How]
DML2.1 reintegration for several fixes and updates to the DML
code.
Reviewed-by: Dillon Varone
Signed-off-by: Austin Zheng
Signed-off-by: Roman Li fams2_required =
display_cfg->stage3.fams2_required;
dml2_core_calcs_get_global_fams2_programm
From: Tim Huang
Flexible endpoints use DIGs from available inflexible endpoints,
so only the encoders of inflexible links need to be freed.
Otherwise, a double free issue may occur when unloading the
amdgpu module.
[ 279.190523] RIP: 0010:__slab_free+0x152/0x2f0
[ 279.190577] Call Trace:
[ 27
From: Ilya Bakoulin
[Why/How]
The call to construct_phy will fail in cases where connector type is
MXM, and the dc_link won't be properly created/initialized.
Reviewed-by: Wenjing Liu
Signed-off-by: Ilya Bakoulin
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/link/link_factory.c
From: Michael Strauss
[WHY]
Previous multi-display HPO fix moved where HPO I/O enable/disable is performed.
The codepath now taken to enable/disable HPO I/O is not used for compliance
test automation, meaning that if a compliance box being driven at a DP1 rate
requests retrain at UHBR, HPO I/O wi
From: Nicholas Susanto
Removing redundant condition.
Reviewed-by: Hansen Dsouza
Signed-off-by: Nicholas Susanto
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
From: Michael Strauss
[WHY]
eDP 2.0 is introducing support for UHBR link rates, however current eDP ILR
link optimization does not account for UHBR capabilities.
Either UHBR capabilities will be provided via the same 128b/132b rate DPCD caps
that are currently used on DP2.1, or Table 4-13 may be
From: Nicholas Susanto
[Why]
Causes hard hangs when resuming after display off on extended/duplicate
modes
[How]
Set the min dispclk to 50Mhz for DCN35
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Nicholas Susanto
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35
From: Nevenko Stupar
[Why & How]
DCN4 Cursor has separate degamma block and should always
do Cursor degamma for Cursor color modes.
Reviewed-by: Chris Park
Signed-off-by: Nevenko Stupar
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c | 5 ++---
1 file ch
From: Aurabindo Pillai
when removing the amdgpu module and reinserting it, a call trace is
triggered:
[ 334.230602] RIP: 0010:hubbub2_get_dchub_ref_freq+0xbb/0xe0 [amdgpu]
[ 334.230807] Code: 25 28 00 00 00 75 3c 48 8d 65 f0 5b 41 5c 5d 31 c0 31 d2
31 c9 31 f6 31 ff 45 31 c0 45 31 c9 45 31 d2
From: Sung Joon Kim
[why]
Supporting UHBR10 link rate on eDP leverages
the existing DP2.0 code but need to add some small
adjustments in code.
[how]
Acknowledge the given DPCD caps for UHBR10
link rate support and allow DP2.0 programming
sequence and link training for eDP.
Reviewed-by: Wenjing
From: Hansen Dsouza
[Why]
Revert updated DCCG wrappers due to regression
[How]
This reverts commit 28b190df7a8f43b39e13886d744742a74a2c162d.
Reviewed-by: Chris Park
Signed-off-by: Hansen Dsouza
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 4 ++--
1 fi
From: Roman Li
Cc: Daniel Wheeler
Aurabindo Pillai (1):
drm/amd/display: remove an extraneous call for checking dchub clock
Austin Zheng (1):
drm/amd/display: DML2.1 Reintegration for Various Fixes
Fangzhi Zuo (1):
drm/amd/display: Fix a typo in revert commit
Hansen Dsouza (1):
Rever
From: Roman Li
[Why]
htmldocs warning:
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h: warning:
Function parameter or struct member 'idle_workqueue' not described in
'amdgpu_display_manager'.
[How]
Add comment section for idle_workqueue with param description.
Reported-by: Stephen Rothwell
From: Roman Li
[Why]
Compilation errors while compiling without CONFIG_DRM_AMD_DC_FP:
"undefined reference to `dc_bandwidth_in_kbps_from_timing'"
[How]
Fix Makefile to move dsc files out of DC_FP guard.
Fixes: 50253f5d9ff4 ("drm/amd/display: Add misc DC changes for DCN401")
Signed-off-by: Roman
From: Aric Cyr
This version pairs with DMUB FW Release 0.0.218.0 for dcn314/315/316,
dcn35/351, dcn401
and brings along the following:
- Fix powerpc compilation
- Fix TBT+TypeC Daisy-chain lightup
- Fix ODM combine setup
- Fix OTC underflow on dcn35
- Fix DVI config for dcn401
- Add ips status
From: Alvin Lee
[Description]
There is a corner case where we're in an ODM config that
has recout.x != 0. In these scenarios we have to take into
account the extra offset in the ODM adjustment for cursor.
Reviewed-by: Aric Cyr
Acked-by: Roman Li
Signed-off-by: Alvin Lee
---
.../drm/amd/displ
From: Roman Li
[Why]
Reset the shared dmub firmware region on dmub hw init to start with
known state.
[How]
Memset the shared region to 0 in dmub_hw_init().
Suggested-by: Nicholas Kazlauskas
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/a
From: Wenjing Liu
[why]
A recent change for ODM combine refactor contains a typo which causes ODM
combine mode programmed incorrectly.
Reviewed-by: George Shen
Acked-by: Roman Li
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2 +-
1 file changed, 1
From: Wenjing Liu
The functions are missing. These two functions are required to support
MST.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Wenjing Liu
---
.../amd/display/dc/dccg/dcn401/dcn401_dccg.c | 159 ++
.../amd/display/dc/dccg/dcn401/dcn401_dccg.h | 12 ++
.../amd/di
From: Roman Li
[Why]
Disable idle optimization for each atomic commit is unnecessary,
and can lead to a potential race condition.
[How]
Remove idle optimization check from amdgpu_dm_atomic_commit_tail()
Fixes: 196107eb1e15 ("drm/amd/display: Add IPS checks before dcn register
access")
Cc: sta
From: Cruise
[Why]
When the link BW is smaller than the request BW,
the DP LT just kept running and fallback to lower link config.
DP LT just aborted if is_hpd_pending bit is high.
But is_hpd_pending bit indicates a new HPD event received.
It doesn't mean the HPD is low.
[How]
Abort the DP LT if
From: Dillon Varone
[WHY&HOW]
At the time of block sequence construction, the exact reference DPP/DISP clock
is
not yet known, so the clock should be passed by reference to the DTO programming
function.
Reviewed-by: Alvin Lee
Acked-by: Roman Li
Signed-off-by: Dillon Varone
---
.../dc/clk_mg
From: Roman Li
[Why]
For debugging and testing purposes.
[How]
If IPS is supported create ips_status debugfs entry.
Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_status
Reviewed-by: Jerry Zuo
Acked-by: Roman Li
Signed-off-by: Roman Li
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 4
From: Ilya Bakoulin
[Why/How]
Need to be able to trigger a DMA load to update 3DLUT contents in MPC.
Adding a HWSS function to serve as the trigger.
Reviewed-by: Krunoslav Kovac
Acked-by: Roman Li
Signed-off-by: Ilya Bakoulin
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 8
From: Dillon Varone
[WHY&HOW]
Disable to improve stability for now.
Reviewed-by: Alvin Lee
Acked-by: Roman Li
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/r
From: Nicholas Susanto
[Why]
Missing check for when there is new pipe configuration but both cur_pipe
and new_pipe are both populated causing update_state of DSC for that
instance not being updated correctly.
This causes some display mode changes to cause underflow since DSCCLK
is still gated w
From: Dillon Varone
Need to select DTBCLK and DPREFCLK as DTBCLK_p source according to
hardware guidance.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --
From: Hersen Wu
[Why] Coverity reports NULL_RETURN warning.
[How] Add pointer NULL check.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Hersen Wu
---
.../gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/displ
From: Chris Park
[Why]
DML 2.1 allocates two types of memory in its ctx structure but does not
destroy them, causing memory leak whenever DML 2.1 instance is created
and destroyed.
[How]
Deallocate two instances of allocated memory whenever DML 2.1 is
destroyed.
Reviewed-by: Rodrigo Siqueira
S
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c | 2 ++
drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c
b/dr
From: Chris Park
[Why]
DVI is TMDS signal like HDMI but without audio. Current signal check
does not correctly reflect DVI clock programming.
[How]
Define a new signal check for TMDS that includes DVI to HDMI TMDS
programming.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Chris Park
---
drive
From: Samson Tam
[Why]
Enable adaptive scaler support for DCN401
[How]
- Enable build flag for SPL
- Set prefer_easf flag to true
- Apply light linear scaling policy based on transfer function and pixel
format. Choose between linear or non-linear scaling
- Set matrix_mode based on pixel forma
From: "Revalla, Harikrishna"
[why]
Cleaning up the code refactor requires hubbub to be in its own
component.
[how]
Move all DCN401 files under newly created hubbub folder and fixing the
makefiles.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Harikrishna Revalla
---
drivers/gpu/drm/amd/displa
From: Alex Hung
This fixes indentations and adjust spaces for better readability and
code styles.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile | 1 -
.../amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 1 -
drivers/gpu/dr
From: Rodrigo Siqueira
The function that commits planes calls the same set of functions twice,
and in the case of the FAMs utilization, it is not desired to call the
dmub, hwss_build and hwss_execute. This commit just removes the
unnecessary calls to those functions.
Acked-by: Roman Li
Signed-o
From: Alex Hung
The comparisons intend to be DCN401 inclusive, and fix it by adding
equal signs.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/disp
From: George Shen
Move dsc functions from dc.c to dc_dsc.c.
Co-Developed-by: George Shen
Signed-off-by: Wenjing Liu
Reviewed-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 99 -
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 96
From: Roman Li
This DC patchset brings improvements in multiple areas. In summary, we have:
- Fix powerpc compilation
- Fix TBT+TypeC Daisy-chain lightup
- Fix underflow on dcn35
- Fix DVI for dcn401
- Add 3DLUT DMA load trigger
- Modify clock programming to support DPM
From: Rodrigo Siqueira
This commit clean up some of the includes used by DCN.
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c | 4
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c | 2 --
.../gpu/drm
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dc
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dc_dp_types.h| 10 --
.../amd/display/dc/gpio/dcn21/hw_translate_dcn21.c | 13 -
2 files changed, 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/d
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
.../drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h | 4
.../include/asic_reg/dcn/dcn_3_0_0_offset.h | 24 +++
.../include/asic_reg/dcn/dcn_3_0_0_sh_mask.h | 9 +++
.../include/asic_reg
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn
From: Eric Bernstein
[Why]
DTN only logs 'pipe_count' instances of MPCC.
However in some cases there are different number of
MPCC than DPP (pipe_count).
[How]
Add mpcc_count parameter to resource_pool and set it
during pool construction and use it for DTN logging of
MPCC state.
Signed-off-by: E
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_inp
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
.../include/asic_reg/dcn/dcn_3_0_3_offset.h | 20 +++
.../include/asic_reg/dcn/dcn_3_0_3_sh_mask.h | 11
.../include/asic_reg/dcn/dcn_3_1_2_offset.h | 4 ++
.../include/asic_reg/dcn/dcn_3_1_2_sh
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c| 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
b/drivers/gpu/drm/amd/dis
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
b/drivers/gpu/dr
From: Rodrigo Siqueira
Set alpha_en to 0 in some specific color formats.
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dp
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
b/drivers/gpu/drm/amd/display/d
From: Rodrigo Siqueira
This commit drops the RESERVE0 and RESERVE1 since both of them can be
summarized as RESERVED.
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a
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