RE: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV

[AMD Public Use] OK. I will just skip the function call for SRIOV and resend. Rohit -Original Message- From: Koenig, Christian Sent: June 7, 2021 12:42 PM To: Kuehling, Felix ; Khaire, Rohit ; amd-gfx@lists.freedesktop.org; Deucher, Alexander ; Zhang, Hawking ; Deng, Emily ; Liu

RE: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV

[AMD Public Use] The hash is 5ea6f9c Rohit -Original Message- From: Koenig, Christian Sent: June 7, 2021 11:58 AM To: Khaire, Rohit ; amd-gfx@lists.freedesktop.org; Deucher, Alexander ; Zhang, Hawking ; Deng, Emily ; Liu, Monk ; Zhou, Peng Ju ; Chen, Horace Cc: Ming, Davis

RE: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV

Rohit -Original Message- From: Koenig, Christian Sent: June 7, 2021 10:31 AM To: Khaire, Rohit ; amd-gfx@lists.freedesktop.org; Deucher, Alexander ; Zhang, Hawking ; Deng, Emily ; Liu, Monk ; Zhou, Peng Ju ; Chen, Horace Cc: Ming, Davis Subject: Re: [PATCH] drm/amdgpu: Use PSP to

RE: [PATCH] drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid

[AMD Official Use Only] Thanks. I will fix that check. Rohit From: Deucher, Alexander Sent: June 4, 2021 10:56 AM To: Khaire, Rohit ; amd-gfx@lists.freedesktop.org; Zhang, Hawking ; Deng, Emily ; Liu, Monk ; Zhou, Peng Ju ; Chen, Horace Cc: Ming, Davis ; Koenig, Christian Subject: Re

RE: [PATCH] drm/amdgpu: Add new PF2VF flags for VF register access method

[AMD Public Use] Thanks Alex and Luben. I've addressed the comments and pushed the changes. Rohit -Original Message- From: Tuikov, Luben Sent: March 29, 2021 11:54 AM To: Khaire, Rohit ; amd-gfx@lists.freedesktop.org; Chang, HaiJun ; Ming, Davis ; Liu, Monk Cc: Koenig, Chri

RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid SRIOV

[AMD Public Use] Adding more reviewers to cc. Rohit -Original Message- From: Khaire, Rohit Sent: September 3, 2020 5:50 PM To: amd-gfx@lists.freedesktop.org Cc: Khaire, Rohit Subject: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid SRIOV Signed-off-by: Rohit

RE: [PATCH] drm/amdgpu: Workaround RCC_DEV0_EPF0_STRAP0 access issue for SRIOV

[AMD Public Use] Hi Alex, I discussed this with my team, we are fine with PCI_REVISION_ID for SRIOV. I am resending my patch with the change you suggested. Thanks Rohit -Original Message- From: Alex Deucher Sent: September 14, 2020 1:16 AM To: Khaire, Rohit Cc: amd-gfx list

RE: [PATCH] SWDEV-220585 - Navi12 L1 policy GC regs WAR #1

Thanks Alex! From: Deucher, Alexander Sent: February 25, 2020 1:16 PM To: Khaire, Rohit ; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] SWDEV-220585 - Navi12 L1 policy GC regs WAR #1 [AMD Public Use] Please fix up the patch title. E.g., drm/amdgpu: Don't write GCVM_L2_CNTL* re