Thanks Alex! From: Deucher, Alexander <alexander.deuc...@amd.com> Sent: February 25, 2020 1:16 PM To: Khaire, Rohit <rohit.kha...@amd.com>; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] SWDEV-220585 - Navi12 L1 policy GC regs WAR #1
[AMD Public Use] Please fix up the patch title. E.g., drm/amdgpu: Don't write GCVM_L2_CNTL* regs on navi12 VF With that fixed, patch is: Reviewed-by: Alex deuc...@amd.com<mailto:deuc...@amd.com>> ________________________________ From: amd-gfx <amd-gfx-boun...@lists.freedesktop.org<mailto:amd-gfx-boun...@lists.freedesktop.org>> on behalf of Rohit Khaire <rohit.kha...@amd.com<mailto:rohit.kha...@amd.com>> Sent: Friday, February 21, 2020 3:24 PM To: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org> <amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>> Cc: Khaire, Rohit <rohit.kha...@amd.com<mailto:rohit.kha...@amd.com>> Subject: [PATCH] SWDEV-220585 - Navi12 L1 policy GC regs WAR #1 This change disables programming of GCVM_L2_CNTL* regs on VF. Signed-off-by: Rohit Khaire <rohit.kha...@amd.com<mailto:rohit.kha...@amd.com>> --- drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c index b70c7b483c24..e0654a216ab5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c @@ -135,6 +135,10 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev) { uint32_t tmp; + /* These regs are not accessible for VF, PF will program these in SRIOV */ + if (amdgpu_sriov_vf(adev)) + return; + /* Setup L2 cache */ tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); @@ -298,9 +302,11 @@ void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev) ENABLE_ADVANCED_DRIVER_MODEL, 0); WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); - /* Setup L2 cache */ - WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); - WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); + if (!amdgpu_sriov_vf(adev)) { + /* Setup L2 cache */ + WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); + WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); + } } /** -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Calexander.deucher%40amd.com%7C52705cf7b1bc4750932a08d7b70c0e38%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637179135079462923&sdata=6YT8MUoBGMujktD%2BoYjEcxCAq2TE4gt7CO7GO4mGpoc%3D&reserved=0
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