[AMD Official Use Only - AMD Internal Distribution Only]
From: amd-gfx On Behalf Of Deng, Emily
Sent: Monday, May 26, 2025 9:51 AM
To: Chen, Xiaogang ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH v2] drm/ttm: Should to return the evict error
[AMD Official Use Only - AMD Internal Distrib
[AMD Official Use Only - AMD Internal Distribution Only]
>-Original Message-
>From: Emily Deng
>Sent: Tuesday, May 27, 2025 6:50 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Deng, Emily
>Subject: [PATCH v2] drm/amdkfd: Move the process suspend and resume out of full
>access
>
>For the susp
Add a helper to pad the ring to a multiple of the fetch size.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 29 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
2 files changed, 22 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/a
Re-emit the unprocessed state after resetting the queue.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index d
Re-emit the unprocessed state after resetting the queue.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index
Re-emit the unprocessed state after resetting the queue.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.
Enable legacy enforce isolation (just serialize kernel
GC submissions). This way we can reset a ring and
only affect the the process currently using that ring.
This mirrors what windows does.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 9 +
1 file changed, 9
We'll want to include the padding in the wptr count
for resets.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 802743efa3b39..3e05e
It doesn't work reliably and we have soft recover and
full adapter reset so drop this.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 71 ---
1 file changed, 71 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/am
Re-emit the unprocessed state after resetting the queue.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 29 +-
1 file changed, 10 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gf
Re-emit the unprocessed state after resetting the queue.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 27 ++
1 file changed, 10 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/gf
Add a new define for queue reset timeout. This will
be used for the IB tests used when validating ring resets.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgp
This set improves per queue reset support for GC10+.
When we reset the queue, the queue is lost so we need
to re-emit the unprocessed state from subsequent submissions.
To that end, in order to make sure we actually restore
unprocessed state, we need to enable legacy enforce isolation
so that we ca
Enable legacy enforce isolation (just serialize kernel
GC submissions). This way we can reset a ring and
only affect the the process currently using that ring.
This mirrors what windows does.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 9 +
1 file changed, 9
Enable legacy enforce isolation (just serialize kernel
GC submissions). This way we can reset a ring and
only affect the the process currently using that ring.
This mirrors what windows does.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 9 +
1 file changed, 9
It doesn't work reliably and we have soft recover and
full adapter reset so drop this.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 46 ---
1 file changed, 46 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/am
Re-emit the unprocessed state after resetting the queue.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 3
Re-emit the unprocessed state after resetting the queue.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 28 ++
1 file changed, 11 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gf
We need to know the wptr and sequence number associated
with a job so that we can re-emit the unprocessed state
after a ring reset. Pre-allocate storage space for
the ring buffer contents and add a helper to save off
the unprocessed state so that it can be re-emitted
after the queue is reset.
Sig
Re-emit the unprocessed state after resetting the queue.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
From: Christian König
Stopping the scheduler for queue reset is generally a good idea because
it prevents any worker from touching the ring buffer.
But using amdgpu_fence_driver_force_completion() before restarting it was
a really bad idea because it marked fences as failed while the work was
po
It doesn't work reliably and we have soft recover and
full adapter reset so drop this.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 71 ---
1 file changed, 71 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
b/drivers/gpu/drm/am
On Tue, May 27, 2025 at 12:47 PM Rodrigo Siqueira wrote:
>
> On 05/22, Alex Deucher wrote:
> > From: Christian König
> >
> > Stopping the scheduler for queue reset is generally a good idea because
> > it prevents any worker from touching the ring buffer.
> >
> > But using amdgpu_fence_driver_forc
From: Taimur Hassan
This version brings along following fixes:
- Fix brightness relevant settings
- Fix calling blanking stream twice
- Extend dc mode validation types to support more scenarios
- Update DMCUB loading sequence for DCN3.5
Acked-by: ChiaHsuan Chung
Signed-off-by: Taimur Hassan
Si
From: Cruise Hung
[Why & How]
It sent an error msg when it failed to read the DP tunneling DPCD field.
This should just be a warning msg. Use a DC log instead of a DM error msg.
Reviewed-by: Wenjing Liu
Signed-off-by: Cruise Hung
Signed-off-by: Wayne Lin
---
.../gpu/drm/amd/display/dc/link/p
From: Mario Limonciello
[Why]
DC and AC levels are advertised in a percentage, not a luminance.
[How]
Scale DC and AC levels to supported values.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4221
Reviewed-by: Alex Hung
Signed-off-by: Mario Limonciello
Signed-off-by: Wayne Lin
---
From: Mario Limonciello
[Why]
Default BIOS brightness caps are buried in ACPI.
[How]
Add extra dynamic debug that can show default brightness caps.
Reviewed-by: Alex Hung
Signed-off-by: Mario Limonciello
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7
From: Zhongwei Zhang
[Why]
We've made fix for garbage in dcn31_reset_back_end_for_pipe(), adding
blank_stream() before disable_crtc(). And set_dpms_off() will call
blank_stream() again.
[How]
Add flag to avoid calling blank_stream() twice.
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Zhongw
From: Yan Li
[Why]
The boolean fast_validate is used as an
input parameter in multiple functions. To
support more scenarios, we are
replacing it with enum dc_validate_mode.
[How]
The enum dc_validate_mode introduces three
possible values:
1) DC_VALIDATE_MODE_AND_PROGRAMMING:
Apply the mode to
From: Nicholas Kazlauskas
[Why]
New sequence from HW for reset and firmware reloading has been
provided that aims to stabilize the reload sequence in the case the
firmware is hung or has outstanding requests.
[How]
Update the sequence to remove the DMUIF reset and the redundant
writes in the rel
From: Taimur Hassan
This version brings along following fixes:
- Fixes for DML21
- Support OLED SDR with AMD ABC
- Indirect buffer transport for FAMS2 commands
- Correct stream attributes setup timing
- Correct non-OLED pre_T11_delay
- Optime boot-up consuming time
- Add support for 2nd sharpenin
From: Taimur Hassan
Add dmub command to support LSDMA
Acked-by: ChiaHsuan Chung
Signed-off-by: Taimur Hassan
Signed-off-by: Wayne Lin
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 156 ++
1 file changed, 156 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dmub/i
From: Ray Wu
[Why & How]
Move vmalloc.h include code to header file.
Reviewed-by: ChiaHsuan Chung
Signed-off-by: Ray Wu
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c | 2 --
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c| 2 --
drivers/gpu
From: Samson Tam
[Why & How]
Add support for 2nd sharpening range for cases where we want
override existing DCN sharpening range
Reviewed-by: Ilya Bakoulin
Signed-off-by: Samson Tam
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/dc/dc.h | 6 ++
.../gpu/drm/amd/displa
From: Navid Assadian
[Why]
When doing 2:1 downscaling on a YUV sub-sampled format, the chroma
scaling ratio is 1:1. Since chroma has cositing, it is needed to do
scaling on the chroma plane(s) and not to bypass chroma scaling.
[How]
Do not set the chroma taps to one when the chroma ratio is iden
From: Oleh Kuzhylnyi
[Why]
DML needs a path for FAMS methods.
[How]
Apply instance of fams2_stream_sub_params_v2 structure with
a FAMS placeholder for DML.
Reviewed-by: Alvin Lee
Signed-off-by: Oleh Kuzhylnyi
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c |
From: Jingwen Zhu
[why]
In the case of an external monitor disconnection,
the kernel mode will attempt to post new timing
validation with two path counts (eDP + external
monitor removed to virtual).
[how]
Skip validating color depth and pixel encoding in the
scenario involving a DP to HDMI activ
[Why & How]
Observe that we try to access DPCD 0x600h of disconnected DP ports.
In order not to wasting time on retrying these ports, call
dpcd_write_rx_power_ctrl() after checking its connection status.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/dc/l
From: Zhongwei Zhang
[Why]
Only OLED panels require non-zero pre_T11_delay defaultly.
Others should be controlled by power sequence.
[How]
For non OLED, pre_T11_delay delay in code should be zero.
Also post_T7_delay.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-b
From: Michael Strauss
[WHY]
If symclk RCO is enabled, stream encoder may not be receiving an
ungated clock by the time we attempt to set stream attributes when
setting dpms on. Since the clock is gated, register writes to the
stream encoder fail.
[HOW]
Move set_stream_attribute call into enable_
From: Mario Limonciello
[Why]
The `drm_*()` print macros will handle including the driver in the print
already. The extra print of the word `amdgpu` is unnecessary.
[How]
Modify all prints to drop `amdgpu: `.
Reviewed-by: Alex Hung
Signed-off-by: Mario Limonciello
Signed-off-by: Wayne Lin
-
From: Oleh Kuzhylnyi
[Why]
The quantity and duration of FAMS2 commands are set to increase
in future products. This necessitates the implementation of a new
mechanism for chaining commands together, allowing all commands
to be processed within a single transaction.
[How]
The indirect buffer acts
From: Yihan Zhu
[WHY & HOW]
Move only RMCM programming outside of dcn401. Extended HW
definition in dc for memory layout to extend support.
Reviewed-by: Jun Lei
Signed-off-by: Yihan Zhu
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/dc/dc.h | 31 ++
drivers/gpu/drm/amd/d
From: Camille Cho
[Why]
Nits programming for SDR panel is only supported by VESA ABC.
[How]
1. Loose nits programming for OLED SDR panel with AMD ABC.
2. We support two ABC methods. Disable one before we program the other
in case panel freaks out.
3. Update HDR judgement in setBR with a solid
From: Austin Zheng
- Store state related info inside mode_lib.
- Fix bad DCFCLK deep sleep
- Update FAMS structure in DMUB header
Reviewed-by: Alvin Lee
Signed-off-by: Austin Zheng
Signed-off-by: Wayne Lin
---
.../amd/display/dc/dml2/dml21/inc/dml_top.h | 1 -
.../display/dc/dml2/dml21/in
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- Fixes for DML21
- Support OLED SDR with AMD ABC
- Indirect buffer transport for FAMS2 commands
- Correct stream attributes setup timing
- Correct non-OLED pre_T11_delay
- Optime boot-up consuming time
- Add suppor
From: Taimur Hassan
Refactoring some DMUB related structs and enum.
Acked-by: Wayne Lin
Signed-off-by: Taimur Hassan
Signed-off-by: Tom Chung
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 34 +--
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu
From: Alvin Lee
[Why & How]
New enums need to be added to the end to avoid
back compat issues.
Reviewed-by: Dillon Varone
Signed-off-by: Alvin Lee
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --
On Tue, May 27, 2025 at 12:39 PM Rodrigo Siqueira wrote:
>
> On 05/20, Alex Deucher wrote:
> > On Mon, May 19, 2025 at 7:59 PM Rodrigo Siqueira
> > wrote:
> > >
> > > On 05/02, Christian König wrote:
> > > > Testing this feature turned out that it was a bit unstable. The
> > > > CP_VMID_RESET re
[Public]
> From: amd-gfx On Behalf Of Christian
> König
> Sent: Tuesday, May 27, 2025 8:24 PM
> To: Khatri, Sunil ; amd-gfx@lists.freedesktop.org;
> Deucher,
> Alexander
> Subject: Re: [PATCH] Revert "drm/amdgpu: promote the implicit sync to the
> dependent read fences"
>
> On 5/27/25 13:27, Kh
For simulation C models that don't run CP FW where adev->mes.sched_version
is not populated correctly. This causes NULL dereference in
amdgpu_amdkfd_free_gtt_mem(dev->adev, (void **)&pqn->q->wptr_bo_gart)
and warning on unpinned BO in amdgpu_bo_gpu_offset(q->properties.wptr_bo).
Compared with addi
On Tue, May 27, 2025 at 12:45 PM Rodrigo Siqueira wrote:
>
> On 05/22, Alex Deucher wrote:
> > This reverts commit b7a1a0ef12b81957584fef7b61e2d5ec049c7209.
> >
> > A user reported stuttering under heavy gfx load with this commit.
> > I suspect it's due to the fact that the gfx contexts are shared
Hi Alex,
Follow some comments and questions.
On 05/02, Alex Deucher wrote:
> Add an initial documentation page for user mode queues.
>
> Signed-off-by: Alex Deucher
> ---
> Documentation/gpu/amdgpu/index.rst | 1 +
> Documentation/gpu/amdgpu/userq.rst | 196 +
> 2
On 2025-05-27 13:06, Alex Hung wrote:
This reverts commit 46e68dd5066c9831e9695c1756db017bb9c3762c since it
breaks color enhancement in another OS, indicating these two fields are
still used by color management in dcn401.
Fixes: 46e68dd5066c ("drm/amd/display: no 3D and blnd LUT as DPP color
This reverts commit 46e68dd5066c9831e9695c1756db017bb9c3762c since it
breaks color enhancement in another OS, indicating these two fields are
still used by color management in dcn401.
Fixes: 46e68dd5066c ("drm/amd/display: no 3D and blnd LUT as DPP color caps for
DCN401")
Signed-off-by: Alex Hung
On 05/22, Alex Deucher wrote:
> From: Christian König
>
> Stopping the scheduler for queue reset is generally a good idea because
> it prevents any worker from touching the ring buffer.
>
> But using amdgpu_fence_driver_force_completion() before restarting it was
> a really bad idea because it m
On 05/22, Alex Deucher wrote:
> This reverts commit b7a1a0ef12b81957584fef7b61e2d5ec049c7209.
>
> A user reported stuttering under heavy gfx load with this commit.
> I suspect it's due to the fact that the gfx contexts are shared
> between the pipes so if there is alot of load on one pipe, we coul
On 05/20, Alex Deucher wrote:
> On Mon, May 19, 2025 at 7:59 PM Rodrigo Siqueira wrote:
> >
> > On 05/02, Christian König wrote:
> > > Testing this feature turned out that it was a bit unstable. The
> > > CP_VMID_RESET register takes the VMID which all submissions from should
> > > be canceled.
>
[Public]
This series is
Reviewed-by: Michael Chen
From: amd-gfx on behalf of Alex Deucher
Sent: Tuesday, May 27, 2025 10:46 AM
To: Deucher, Alexander
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/amdgpu/mes: add missing locking in helper func
For supported ASICs DMCU version is exported, but ASICs that support
DMCUB there is no information exported to sysfs.
Add an attribute for DMCUB.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --
kfd_lookup_process_by_pid increases process ref, the refcount is
leaking.
Fixes: 7a566d7f56f4 ("amd/amdkfd: Trigger segfault for early userptr
unmmapping")
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions
Ping on this series?
Alex
On Mon, May 19, 2025 at 4:04 PM Alex Deucher wrote:
>
> We need to take the MES lock.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 16
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/
Ping?
Alex
On Fri, May 2, 2025 at 5:00 PM Alex Deucher wrote:
>
> Add an initial documentation page for user mode queues.
>
> Signed-off-by: Alex Deucher
> ---
> Documentation/gpu/amdgpu/index.rst | 1 +
> Documentation/gpu/amdgpu/userq.rst | 196 +
> 2 files chan
On 5/27/25 13:27, Khatri, Sunil wrote:
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> -Original Message-
> From: Koenig, Christian
> Sent: Tuesday, May 27, 2025 2:32 PM
> To: Khatri, Sunil ; amd-gfx@lists.freedesktop.org;
> Deucher, Alexander
> Subject: Re: [PATCH] Rever
For the suspend and resume process, exclusive access is not required.
Therefore, it can be moved out of the full access section to reduce the
duration of exclusive access.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 16 +
drivers/gpu/drm/amd/amdgpu/amdgpu_a
[AMD Official Use Only - AMD Internal Distribution Only]
-Original Message-
From: Koenig, Christian
Sent: Tuesday, May 27, 2025 2:32 PM
To: Khatri, Sunil ; amd-gfx@lists.freedesktop.org;
Deucher, Alexander
Subject: Re: [PATCH] Revert "drm/amdgpu: promote the implicit sync to the
depend
On 5/27/25 10:58, Sunil Khatri wrote:
> This reverts commit 714bbbf20a7266e48632fab466563e695af9acb5.
> bisected to this change which is causing the flikering issue in the UI
> for various apps like glxgears and unigen heaven.
Is that flickering also there when using kernel queues?
If not then wi
This reverts commit 714bbbf20a7266e48632fab466563e695af9acb5.
bisected to this change which is causing the flikering issue in the UI
for various apps like glxgears and unigen heaven.
Also when we set user_queue=1, which enable both user and kernel submissions
the userqueue tests in IGT also fail.
On Mon, 2025-05-26 at 11:25 +0200, Christian König wrote:
> On 5/23/25 16:16, Danilo Krummrich wrote:
> > On Fri, May 23, 2025 at 04:11:39PM +0200, Danilo Krummrich wrote:
> > > On Fri, May 23, 2025 at 02:56:40PM +0200, Christian König wrote:
> > > > It turned out that we can actually massively opt
On Mon, 2025-05-26 at 13:16 +0200, Christian König wrote:
> On 5/26/25 11:34, Philipp Stanner wrote:
> > On Mon, 2025-05-26 at 11:25 +0200, Christian König wrote:
> > > On 5/23/25 16:16, Danilo Krummrich wrote:
> > > > On Fri, May 23, 2025 at 04:11:39PM +0200, Danilo Krummrich
> > > > wrote:
> > >
+Cc Matthew, again :)
On Thu, 2025-05-22 at 18:19 +0200, Christian König wrote:
> On 5/22/25 16:27, Tvrtko Ursulin wrote:
> >
> > On 22/05/2025 14:41, Christian König wrote:
> > > Since we already iterated over the xarray we know at which index
> > > the new
> > > entry should be stored. So inste
71 matches
Mail list logo