[PATCH 19/19] drm/amdgpu/gfx12: re-emit unprocessed state on kcq reset

[Alex Deucher]

Re-emit the unprocessed state after resetting the queue.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 27 ++++++++++----------------
 1 file changed, 10 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 4018464e00939..a9e8700bd5f2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -4699,21 +4699,6 @@ static void 
gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
                               ref, mask, 0x20);
 }
 
-static void gfx_v12_0_ring_soft_recovery(struct amdgpu_ring *ring,
-                                        unsigned vmid)
-{
-       struct amdgpu_device *adev = ring->adev;
-       uint32_t value = 0;
-
-       value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
-       value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
-       value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
-       value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
-       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
-       WREG32_SOC15(GC, 0, regSQ_CMD, value);
-       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
-}
-
 static void
 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
                                      uint32_t me, uint32_t pipe,
@@ -5442,6 +5427,7 @@ static int gfx_v12_0_reset_compute_pipe(struct 
amdgpu_ring *ring)
 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid)
 {
        struct amdgpu_device *adev = ring->adev;
+       unsigned int i;
        int r;
 
        if (amdgpu_sriov_vf(adev))
@@ -5466,7 +5452,15 @@ static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, 
unsigned int vmid)
                return r;
        }
 
-       return amdgpu_ring_test_ring(ring);
+       if (amdgpu_ring_alloc(ring, 8 + ring->ring_backup_entries_to_copy))
+               return -ENOMEM;
+       amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
+                              ring->ring_backup_seq, 0);
+       for (i = 0; i < ring->ring_backup_entries_to_copy; i++)
+               amdgpu_ring_write(ring, ring->ring_backup[i]);
+       amdgpu_ring_commit(ring);
+
+       return gfx_v12_0_ring_test_ib(ring, AMDGPU_QUEUE_RESET_TIMEOUT);
 }
 
 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring)
@@ -5582,7 +5576,6 @@ static const struct amdgpu_ring_funcs 
gfx_v12_0_ring_funcs_compute = {
        .emit_wreg = gfx_v12_0_ring_emit_wreg,
        .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,
        .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,
-       .soft_recovery = gfx_v12_0_ring_soft_recovery,
        .emit_mem_sync = gfx_v12_0_emit_mem_sync,
        .reset = gfx_v12_0_reset_kcq,
        .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader,
-- 
2.49.0