On 8/28/2024 10:50 AM, Prike Liang wrote:
> Implement the compute pipe reset, and the driver will
> fallback to pipe reset when queue reset fails.
> The pipe reset only deactivates the queue which is
> scheduled in the pipe, and meanwhile the MEC engine
> will be reset to the firmware _start poi
On VFs and SOCs with GC 9.4.4, VCN RRMT is disabled.
Only local register offsets should be used on JPEG v4.0.3 as they cannot
handle remote access to other AIDs. Since only local offsets are used,
the special write to MCM_ADDR register is no longer needed.
Signed-off-by: Lijo Lazar
---
v2: Restri
Implement the compute pipe reset, and the driver will
fallback to pipe reset when queue reset fails.
The pipe reset only deactivates the queue which is
scheduled in the pipe, and meanwhile the MEC engine
will be reset to the firmware _start pointer. So,
it seems pipe reset will cost more cycles tha
On 8/27/2024 7:42 PM, Christian König wrote:
> This was only used as workaround for recovering the page tables after
> VRAM was lost and is no longer necessary after the function
> amdgpu_vm_bo_reset_state_machine() started to do the same.
>
> Compute never used shadows either, so the only prop
[AMD Official Use Only - AMD Internal Distribution Only]
> From: Lazar, Lijo
> Sent: Tuesday, August 27, 2024 4:02 PM
> To: Liang, Prike ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Ma, Le
>
> Subject: Re: [PATCH v3] drm/amdgpu/gfx9.4.3: Implement compute pipe reset
>
>
>
> On 8/22
This commit adds a description for the 'ts' parameter in the
amdgpu_vm_handle_fault function's comment block.
Fixes the below with gcc W=1:
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2781: warning: Function parameter or
struct member 'ts' not described in 'amdgpu_vm_handle_fault'
Cc: Xiaogang.Chen
On Tue, Aug 20, 2024 at 12:09 AM Vignesh Raman
wrote:
>
> Set the timeout of all drm-ci jobs to 1h30m since
> some jobs takes more than 1 hour to complete.
>
> Signed-off-by: Vignesh Raman
Acked-by: Rob Clark
> ---
> drivers/gpu/drm/ci/test.yml | 5 -
> 1 file changed, 4 insertions(+), 1
Reviewed-by:JamesZhufortheseries.
On 2024-08-27 13:10, Philip Yang wrote:
1. Document how to use SMI system management interface to receive SVM
events, define string format macro for user mode.
2. Increase the event kfifo size, so less chance to drop event.
3. Output migrate end event with error
On 2024-08-27 15:53, sunpeng...@amd.com wrote:
> From: Leo Li
>
> [Why]
>
> DCN IPS interoperates with other system idle power features, such as
> Zstates.
>
> On DCN35, there is a known issue where system Z8 + DCN IPS2 causes a
> hard hang. We observe this on systems where the SBIOS allows
On Tue, 20 Aug 2024 04:08:16 -0300 Vignesh Raman wrote ---
> Set the timeout of all drm-ci jobs to 1h30m since
> some jobs takes more than 1 hour to complete.
>
> Signed-off-by: Vignesh Raman vignesh.ra...@collabora.com>
Acked-by: Helen Koike
Thanks
Helen
> ---
> driver
From: Leo Li
[Why]
DCN IPS interoperates with other system idle power features, such as
Zstates.
On DCN35, there is a known issue where system Z8 + DCN IPS2 causes a
hard hang. We observe this on systems where the SBIOS allows Z8.
Though there is a SBIOS fix, there's no guarantee that users wi
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Sreekant Somasekharan
Regards,
-Sreekant
From: amd-gfx on behalf of David
Belanger
Sent: Friday, August 23, 2024 7:58 PM
To: amd-gfx@lists.freedesktop.org
Cc: Belanger, David
Subject: [
Le 19/08/24 - 16:57, Harry Wentland a écrit :
> Not all HW will be able to do bypass on all color
> operations. Introduce an 'allow_bypass' boolean for
> all colorop init functions and only create the BYPASS
> property when it's true.
You did not change the documentation of struct drm_colorop_stat
Le 19/08/24 - 16:56, Harry Wentland a écrit :
> We add two 3x4 matrices into the VKMS color pipeline. The reason
> we're adding matrices is so that we can test that application
> of a matrix and its inverse yields an output equal to the input
> image.
>
> One complication with the matrix implement
Le 19/08/24 - 16:56, Harry Wentland a écrit :
[...]
> diff --git a/drivers/gpu/drm/vkms/vkms_composer.c
> b/drivers/gpu/drm/vkms/vkms_composer.c
> index 3d6785d081f2..3ecda70c2b55 100644
> --- a/drivers/gpu/drm/vkms/vkms_composer.c
> +++ b/drivers/gpu/drm/vkms/vkms_composer.c
> @@ -435,3 +435,7
Le 19/08/24 - 16:56, Harry Wentland a écrit :
> fixp2int always rounds down, fixp2int_ceil rounds up. We need
> the new fixp2int_round.
>
> Signed-off-by: Harry Wentland
> ---
> drivers/gpu/drm/vkms/vkms_composer.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers
Le 19/08/24 - 16:56, Harry Wentland a écrit :
> +static int vkms_initialize_color_pipeline(struct drm_plane *plane, struct
> drm_prop_enum_list *list)
> +{
> +
> + struct drm_colorop *op, *prev_op;
> + struct drm_device *dev = plane->dev;
> + int ret;
> +
> + /* 1st op: 1d curve *
Le 19/08/24 - 16:56, Harry Wentland a écrit :
> This is an RFC set for a color pipeline API, along with implementations
> in VKMS and amdgpu. It is tested with a set of IGT tests that can be
> found at [1]. The IGT tests run a pixel-by-pixel comparison with an
> allowable delta variation as the goa
Le 19/08/24 - 16:56, Harry Wentland a écrit :
[...]
> +#ifndef __DRM_COLOROP_H__
> +#define __DRM_COLOROP_H__
> +
> +#include
> +#include
> +#include
> +
> +/**
> + * struct drm_colorop_state - mutable colorop state
> + */
> +struct drm_colorop_state {
> + /** @colorop: backpointer to the
Le 19/08/24 - 16:56, Harry Wentland a écrit :
> Certain operations require us to preserve values below 0.0 and
> above 1.0 (0x0 and 0x respectively in 16 bpc unorm). One
> such operation is a BT709 encoding operation followed by its
> decoding operation, or the reverse.
>
> We'll use s32 value
On 8/22/24 3:14 PM, Fangzhi Zuo wrote:
338567d176 ("drm/amd/display: Fix MST BW calculation Regression") has been
merged
with a mistake being fixed by "drm/amd/display: Fix a mistake in revert commit"
Fix dsc enablement for Synaptics Cascaded Panamera hub is included in
"drm/amd/display:
1. Document how to use SMI system management interface to receive SVM
events, define string format macro for user mode.
2. Increase the event kfifo size, so less chance to drop event.
3. Output migrate end event with error code if migration failed.
4. Report dropped event count if fifo is full.
v3
Add new SMI event to report the dropped event count.
When the event kfifo is full, drop count is not zero, or no enough space
left to store the event message, increase drop count.
After reading event out from kfifo, if event was dropped, drop_count is
not zero, generate a dropped event record and
Add new SMI event to report the dropped event count.
When the event kfifo is full, drop count is not zero, or no enough space
left to store the event message, increase drop count.
After reading event out from kfifo, if event was dropped, drop_count is
not zero, generate a dropped event record and
Document how to use SMI system management interface to enable and
receive SVM events. Document SVM event triggers.
Define SVM events message string format macro that could be used by user
mode for sscanf to parse the event. Add it to uAPI header file to make
it obvious that is changing uAPI in fut
SMI event fifo size 1KB was enough to report GPU vm fault or reset
event, but could drop the more frequent SVM migration events. Increase
kfifo size to 8KB to store about 100 migrate events, less chance to drop
the migrate events if lots of migration happened in the short period of
time. Add KFD pr
If page migration failed, also output migrate end event to match with
migrate start event, with failure error_code added to the end of the
migrate message macro. This will not break uAPI because application uses
old message macro sscanf drop and ignore the error_code.
Signed-off-by: Philip Yang
-
From: Nicholas Susanto
[Why]
Function used to check the number of FEs connected to the current BE.
This was then used to determine if the symclk could be disabled, if
all FEs were disconnected. However, the function would skip over the
primary FE and return 0 when the primary FE was still connec
From: Dillon Varone
PMO assumes that like timings can be synchronized, but DC only allows
this if the signal types match.
Cc: sta...@vger.kernel.org
Reviewed-by: Austin Zheng
Signed-off-by: Dillon Varone
Signed-off-by: Hamza Mahfooz
---
.../display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fa
From: Hansen Dsouza
Always allow un-gating. Follow legacy workaround for repeated
dppclk dto updates
Reviewed-by: Muhammad Ahmed
Signed-off-by: Hansen Dsouza
Signed-off-by: Hamza Mahfooz
---
.../amd/display/dc/dccg/dcn20/dcn20_dccg.h| 11 +++
.../amd/display/dc/dccg/dcn35/dcn35_dccg.c
From: Aric Cyr
This version brings along the following:
- DCN35 fixes
- DML2 fixes
- IPS fixes
- ODM fixes
- Miscellaneous cleanups
- MST fixes
- SPL fixes
Acked-by: Aurabindo Pillai
Signed-off-by: Aric Cyr
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/dc/dc.h | 2
From: Relja Vojvodic
- Add interface for controlling shapness level input into DCN.
- Update SPL to support custom sharpness values.
- Add support for different sharpness values depending on YUV/RGB
content.
Reviewed-by: Samson Tam
Signed-off-by: Relja Vojvodic
Signed-off-by: Hamza Mahfooz
From: Gabe Teeger
[what]
Graphics hang observed with 3 displays connected to DP2.0 mst dock.
[why]
There's a mismatch in dml and dc between the assignments of hpo link
encoders.
[how]
Add a new array in dml that tracks the current mapping of HPO stream
encoders to HPO link encoders in dc.
Cc:
From: Dillon Varone
This reverts commit 3b837c45668c3026fd09145904692ba1130c5d12.
It is causing graphics hangs.
Reviewed-by: Martin Leung
Signed-off-by: Dillon Varone
Signed-off-by: Hamza Mahfooz
---
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 9 +---
.../amd/display/dc/hwss/dcn20/dcn2
From: Meenakshikumar Somasundaram
[Why]
To provide option to dpia control power management
[How]
By adding disable_usb4_pm_support bit field in dpia_debug option to
control dpia power management
Reviewed-by: Jun Lei
Signed-off-by: Meenakshikumar Somasundaram
Signed-off-by: Hamza Mahfooz
---
From: Qili Lu
[Why]
enable dpp rcg before we disable dppclk in hw_init cause system
hang/reboot
[How]
we remove dccg rcg related code from init into a separate function and
call it after we init pipe
Cc: sta...@vger.kernel.org # 6.10+
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Qili Lu
Si
From: Leo Li
Backlight updates require aux and/or register access. Therefore, driver
needs to disallow IPS beforehand.
So, acquire the dc lock before calling into dc to update backlight - we
should be doing this regardless of IPS. Then, while the lock is held,
disallow IPS before calling into dc
From: Samson Tam
[Why]
Certain profiles have higher HDR multiplier than SDR boost max which
is not currently supported
[How]
Disable sharpness for these profiles
Fixes: 63697e1d69c7 ("drm/amd/display: add improvements for text display and
HDR DWM and MPO")
Reviewed-by: Martin Leung
Signed-off
From: Nicholas Susanto
[Why]
Setting min dispclk to 50Mhz outside clock lowering function causes
unnecessary calls to SMU to lower dispclk and causes dentist hangs when
there is no stream on the pipes.
[How]
Move the set minimum dispclk logic inside the lowering dispclk if
statement.
Fixes: 2
From: Samson Tam
[Why]
Previous disable ODM policy due to underflow issue with sharpener.
Issue is resolved after updating sharpening policy to apply to
both windowed and fullscreen video
[How]
Remove sharpness check disabling Dynamic ODM policy
Reviewed-by: Martin Leung
Signed-off-by: Samson
From: Daniel Sa
[Why]
Some asserts are always hit on startup/Pnp when they should only be used
to indicate when something has gone wrong.
[How]
Ignore result of getting function from bios cmd table for newer asics.
Reviewed-by: Jun Lei
Signed-off-by: Daniel Sa
Signed-off-by: Hamza Mahfooz
--
Cc: Daniel Wheeler
Aric Cyr (1):
drm/amd/display: 3.2.299
Daniel Sa (1):
drm/amd/display: only trigger BIOS related assert for older ASICs
Dillon Varone (2):
Revert "drm/amd/display: Wait for all pending cleared before full
update"
drm/amd/display: Block timing sync for different si
On Sat, Aug 24, 2024 at 1:23 AM Greg KH wrote:
>
> On Fri, Aug 23, 2024 at 05:23:46PM -0400, Alex Deucher wrote:
> > On Thu, Aug 15, 2024 at 1:11 AM Greg KH wrote:
> > >
> > > On Wed, Aug 14, 2024 at 05:30:08PM -0400, Alex Deucher wrote:
> > > > On Wed, Aug 14, 2024 at 4:55 PM Felix Kuehling
>
That is clearly not something we should do upstream. The SDMA is
mandatory for the driver to work correctly.
We could do this for emulation and bringup, but in those cases the
engineer should probably enabled CPU based updates manually.
This reverts commit 23335f9577e0b509c20ad8d65d9fdedd14545b55
Am 30.07.24 um 06:36 schrieb Yifan Zhang:
avoid using SDMA if it is unavailable.
That is clearly not something we should do. The SDMA is mandatory for
the driver to work.
We could do this for emulation and bringup, but in those cases the
engineer should probably enabled CPU based updates ma
Instead of having that in the amdgpu_bo_pin() function applied for all
pinned BOs.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
This was only used as workaround for recovering the page tables after
VRAM was lost and is no longer necessary after the function
amdgpu_vm_bo_reset_state_machine() started to do the same.
Compute never used shadows either, so the only proplematic case left is
SVM and that is most likely not recov
We haven't used the functionality to pin BOs in a certain range at all
while the driver existed. Just nuke it.
Signed-off-by: Christian König
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 56 ++-
drivers/gpu/drm/amd/amd
On Tue, Aug 27, 2024 at 9:21 AM Yifan Zhang wrote:
>
> ih1 is not initialized for APUs. Don't drain it or NULL pointer
> error will be triggered.
>
> Fixes: 490fc21fe97c (drm/amdkfd: Change kfd/svm page fault drain handling)
> Signed-off-by: Yifan Zhang
Reviewed-by: Alex Deucher
> ---
> drive
[AMD Official Use Only - AMD Internal Distribution Only]
Thanks. Will send V2.
-Original Message-
From: Alex Deucher
Sent: Tuesday, August 27, 2024 9:08 PM
To: Zhang, Yifan
Cc: amd-gfx@lists.freedesktop.org; Kuehling, Felix ;
Yang, Philip ; Chen, Xiaogang
Subject: Re: [PATCH] drm/amdk
ih1 is not initialized for APUs. Don't drain it or NULL pointer
error will be triggered.
Fixes: 490fc21fe97c (drm/amdkfd: Change kfd/svm page fault drain handling)
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(
On Tue, Aug 27, 2024 at 3:26 AM Yifan Zhang wrote:
>
> ih1 is not initialized for APUs. Don't drain it or NULL pointer
> error will be triggered.
>
> Fixes: 490fc21fe97c (drm/amdkfd: Change kfd/svm page fault drain handling)
> Signed-off-by: Yifan Zhang
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_svm
On Mon, Aug 26, 2024 at 04:15:26PM -0400, Alex Deucher wrote:
> Hi Dave, Sima,
>
> New stuff for 6.12.
>
> The following changes since commit 627a24f5f25d689682f395f3df1411273be4436b:
>
> Merge tag 'amd-drm-fixes-6.11-2024-07-18' of
> https://gitlab.freedesktop.org/agd5f/linux into drm-next (
On 8/22/2024 3:08 PM, Prike Liang wrote:
> Implement the compute pipe reset and driver will
> fallback to pipe reset when queue reset failed.
>
> Signed-off-by: Prike Liang
> ---
> v3: Use the dev log and filer out the gfx9.4.4 pipe reset support.
> v2: Convert the GC logic instance to physica
ih1 is not initialized for APUs. Don't drain it or NULL pointer
error will be triggered.
Fixes: 490fc21fe97c (drm/amdkfd: Change kfd/svm page fault drain handling)
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(
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